thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
1420 lines
38 KiB
HTML
1420 lines
38 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<html xmlns="http://www.w3.org/1999/xhtml">
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<head>
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<title>datasheet for qsys_top</title>
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.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
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.parametersbox table { font-size:10px ;}
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td.parametername { font-style:italic ;}
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</head>
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<body>
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<table class="topTitle">
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<tr>
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<td class="l">qsys_top</td>
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<td class="r">
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<br/>
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<br/>
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</td>
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</tr>
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</table>
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<table class="blueBar">
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<tr>
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<td class="l">2026.05.11.21:03:53</td>
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<td class="r">Datasheet</td>
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</tr>
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</table>
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<div style="width:100% ; height:10px"> </div>
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<div class="label">Overview</div>
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<div class="greydiv">
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<div style="display:inline-block ; text-align:left">
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<table class="connectionboxes">
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<tr style="height:6px">
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<td></td>
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</tr>
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</table>
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</div><span style="display:inline-block ; width:28px"> </span>
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<div style="display:inline-block ; text-align:left"><span>Processor
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<br/>  
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<a href="#module_subsys_hps_agilex_hps"><b>subsys_hps_agilex_hps</b>
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</a> sm_hps 13.0.0
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<br/>All Components
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<br/>  
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<a href="#module_subsys_periph"><b>subsys_periph</b>
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</a> peripheral_subsys 1.0
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<br/>  
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<a href="#module_subsys_periph_button_pio"><b>subsys_periph_button_pio</b>
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</a> altera_avalon_pio 19.2.3
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<br/>  
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<a href="#module_subsys_periph_dipsw_pio"><b>subsys_periph_dipsw_pio</b>
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</a> altera_avalon_pio 19.2.3
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<br/>  
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<a href="#module_subsys_periph_led_pio"><b>subsys_periph_led_pio</b>
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</a> altera_avalon_pio 19.2.3
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<br/>  
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<a href="#module_subsys_periph_pb_cpu_0"><b>subsys_periph_pb_cpu_0</b>
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</a> altera_avalon_mm_bridge 20.1.0
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<br/>  
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<a href="#module_subsys_periph_sysid"><b>subsys_periph_sysid</b>
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</a> altera_avalon_sysid_qsys 19.1.7</span>
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</div>
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</div>
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<div style="width:100% ; height:10px"> </div>
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<div class="label">Memory Map</div>
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<table class="mmap">
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<tr>
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<td class="empty" rowspan="2"></td>
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<td class="mastermodule" colspan="2">
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<a href="#module_subsys_hps"><b>subsys_hps</b>
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</a>
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</td>
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<td class="mastermodule" colspan="2">
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<a href="#module_subsys_hps_agilex_hps"><b>subsys_hps_agilex_hps</b>
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</a>
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</td>
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<td class="mastermodule" colspan="1">
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<a href="#module_subsys_periph_pb_cpu_0"><b>subsys_periph_pb_cpu_0</b>
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</a>
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</td>
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</tr>
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<tr>
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<td class="masterl"> hps2fpga</td>
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<td class="masterr"> lwhps2fpga</td>
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<td class="masterl"> hps2fpga</td>
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<td class="masterr"> lwhps2fpga</td>
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<td class="masterlr"> m0</td>
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</tr>
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<tr>
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<td class="slavemodule"> 
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<a href="#module_subsys_hps"><b>subsys_hps</b>
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</a>
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</td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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</tr>
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<tr>
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<td class="slaveb">f2sdram </td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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</tr>
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<tr>
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<td class="slavemodule"> 
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<a href="#module_subsys_hps_agilex_hps"><b>subsys_hps_agilex_hps</b>
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</a>
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</td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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</tr>
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<tr>
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<td class="slaveb">f2sdram </td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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</tr>
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<tr>
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<td class="slavemodule"> 
|
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<a href="#module_subsys_periph"><b>subsys_periph</b>
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</a>
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</td>
|
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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</tr>
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<tr>
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<td class="slaveb">pb_cpu_0_s0 </td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
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<td class="empty"></td>
|
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</tr>
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<tr>
|
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<td class="slavemodule"> 
|
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<a href="#module_subsys_periph_button_pio"><b>subsys_periph_button_pio</b>
|
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</a>
|
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</td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
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<td class="empty"></td>
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</tr>
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<tr>
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<td class="slaveb">s1 </td>
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<td class="empty"></td>
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<td>0x0001_0060 - 0x0001_006f</td>
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<td class="empty"></td>
|
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<td>0x0001_0060 - 0x0001_006f</td>
|
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<td>0x0001_0060 - 0x0001_006f</td>
|
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</tr>
|
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<tr>
|
|
<td class="slavemodule"> 
|
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<a href="#module_subsys_periph_dipsw_pio"><b>subsys_periph_dipsw_pio</b>
|
|
</a>
|
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</td>
|
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<td class="empty"></td>
|
|
<td class="empty"></td>
|
|
<td class="empty"></td>
|
|
<td class="empty"></td>
|
|
<td class="empty"></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="slaveb">s1 </td>
|
|
<td class="empty"></td>
|
|
<td>0x0001_0070 - 0x0001_007f</td>
|
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<td class="empty"></td>
|
|
<td>0x0001_0070 - 0x0001_007f</td>
|
|
<td>0x0001_0070 - 0x0001_007f</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="slavemodule"> 
|
|
<a href="#module_subsys_periph_led_pio"><b>subsys_periph_led_pio</b>
|
|
</a>
|
|
</td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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</tr>
|
|
<tr>
|
|
<td class="slaveb">s1 </td>
|
|
<td class="empty"></td>
|
|
<td>0x0001_0080 - 0x0001_008f</td>
|
|
<td class="empty"></td>
|
|
<td>0x0001_0080 - 0x0001_008f</td>
|
|
<td>0x0001_0080 - 0x0001_008f</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="slavemodule"> 
|
|
<a href="#module_subsys_periph_pb_cpu_0"><b>subsys_periph_pb_cpu_0</b>
|
|
</a>
|
|
</td>
|
|
<td class="empty"></td>
|
|
<td class="empty"></td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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<td class="empty"></td>
|
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</tr>
|
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<tr>
|
|
<td class="slaveb">s0 </td>
|
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<td class="empty"></td>
|
|
<td>0x0000_0000 - 0x0001_ffff</td>
|
|
<td class="empty"></td>
|
|
<td>0x0000_0000 - 0x0001_ffff</td>
|
|
<td class="empty"></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="slavemodule"> 
|
|
<a href="#module_subsys_periph_sysid"><b>subsys_periph_sysid</b>
|
|
</a>
|
|
</td>
|
|
<td class="empty"></td>
|
|
<td class="empty"></td>
|
|
<td class="empty"></td>
|
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<td class="empty"></td>
|
|
<td class="empty"></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="slaveb">control_slave </td>
|
|
<td class="empty"></td>
|
|
<td>0x0001_0000 - 0x0001_0007</td>
|
|
<td class="empty"></td>
|
|
<td>0x0001_0000 - 0x0001_0007</td>
|
|
<td>0x0001_0000 - 0x0001_0007</td>
|
|
</tr>
|
|
</table>
|
|
<a name="module_clk_100"> </a>
|
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<div>
|
|
<hr/>
|
|
<h2>clk_100</h2>altera_clock_bridge v19.2.0
|
|
<br/>
|
|
<br/>
|
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<br/>
|
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<table class="flowbox">
|
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<tr>
|
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<td class="parametersbox">
|
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<h2>Parameters</h2>
|
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<table>
|
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<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
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<td class="parametervalue">false</td>
|
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</tr>
|
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</table>
|
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</td>
|
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</tr>
|
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</table>  
|
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<table class="flowbox">
|
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<tr>
|
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<td class="parametersbox">
|
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<h2>Software Assignments</h2>(none)</td>
|
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</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_rst_in"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>rst_in</h2>altera_reset_bridge v19.2.0
|
|
<br/>
|
|
<br/>
|
|
<br/>
|
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<table class="flowbox">
|
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<tr>
|
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<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
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</tr>
|
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</table>  
|
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<table class="flowbox">
|
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<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_user_rst_clkgate_0"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>user_rst_clkgate_0</h2>intel_user_rst_clkgate v1.0.1
|
|
<br/>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_hps"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_hps</h2>hps_subsys v1.0
|
|
<br/>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_hps_agilex_hps"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_hps_agilex_hps</h2>intel_agilex_5_soc v13.0.0
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_hps_emif_hps">subsys_hps_emif_hps</a>
|
|
</td>
|
|
<td class="from">io96b0_to_hps  </td>
|
|
<td class="main" rowspan="24">subsys_hps_agilex_hps</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  io96b0_to_hps</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="6">
|
|
<a href="#module_clk_100">clk_100</a>
|
|
</td>
|
|
<td class="from">out_clk  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  f2sdram_axi_clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="from">out_clk  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  hps2fpga_axi_clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="from">out_clk  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  lwhps2fpga_axi_clock</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="6">
|
|
<a href="#module_rst_in">rst_in</a>
|
|
</td>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  f2sdram_axi_reset</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  hps2fpga_axi_reset</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  lwhps2fpga_axi_reset</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">lwhps2fpga  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_pb_cpu_0">subsys_periph_pb_cpu_0</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  s0</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">fpga2hps_interrupt_irq0  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_button_pio">subsys_periph_button_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  irq</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">fpga2hps_interrupt_irq0  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_dipsw_pio">subsys_periph_dipsw_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  irq</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">CPU_FREQ</td>
|
|
<td class="parametervalue">50000000u</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_hps_emif_hps"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_hps_emif_hps</h2>emif_io96b_hps v4.0.0
|
|
<br/>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph</h2>peripheral_subsys v1.0
|
|
<br/>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph_button_pio"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph_button_pio</h2>altera_avalon_pio v19.2.3
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_pb_cpu_0">subsys_periph_pb_cpu_0</a>
|
|
</td>
|
|
<td class="from">m0  </td>
|
|
<td class="main" rowspan="11">subsys_periph_button_pio</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  s1</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_clk">subsys_periph_periph_clk</a>
|
|
</td>
|
|
<td class="from">out_clk  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_rst_in">subsys_periph_periph_rst_in</a>
|
|
</td>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_hps_agilex_hps">subsys_hps_agilex_hps</a>
|
|
</td>
|
|
<td class="from">fpga2hps_interrupt_irq0  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  irq</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">CAPTURE</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DATA_WIDTH</td>
|
|
<td class="parametervalue">4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DO_TEST_BENCH_WIRING</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DRIVEN_SIM_VALUE</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">EDGE_TYPE</td>
|
|
<td class="parametervalue">FALLING</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">FREQ</td>
|
|
<td class="parametervalue">100000000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_IN</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_OUT</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_TRI</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">IRQ_TYPE</td>
|
|
<td class="parametervalue">EDGE</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">RESET_VALUE</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph_dipsw_pio"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph_dipsw_pio</h2>altera_avalon_pio v19.2.3
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_pb_cpu_0">subsys_periph_pb_cpu_0</a>
|
|
</td>
|
|
<td class="from">m0  </td>
|
|
<td class="main" rowspan="11">subsys_periph_dipsw_pio</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  s1</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_clk">subsys_periph_periph_clk</a>
|
|
</td>
|
|
<td class="from">out_clk  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_rst_in">subsys_periph_periph_rst_in</a>
|
|
</td>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_hps_agilex_hps">subsys_hps_agilex_hps</a>
|
|
</td>
|
|
<td class="from">fpga2hps_interrupt_irq0  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  irq</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">CAPTURE</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DATA_WIDTH</td>
|
|
<td class="parametervalue">4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DO_TEST_BENCH_WIRING</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DRIVEN_SIM_VALUE</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">EDGE_TYPE</td>
|
|
<td class="parametervalue">FALLING</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">FREQ</td>
|
|
<td class="parametervalue">100000000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_IN</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_OUT</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_TRI</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">IRQ_TYPE</td>
|
|
<td class="parametervalue">EDGE</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">RESET_VALUE</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph_led_pio"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph_led_pio</h2>altera_avalon_pio v19.2.3
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_pb_cpu_0">subsys_periph_pb_cpu_0</a>
|
|
</td>
|
|
<td class="from">m0  </td>
|
|
<td class="main" rowspan="8">subsys_periph_led_pio</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  s1</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_clk">subsys_periph_periph_clk</a>
|
|
</td>
|
|
<td class="from">out_clk  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_rst_in">subsys_periph_periph_rst_in</a>
|
|
</td>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">CAPTURE</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DATA_WIDTH</td>
|
|
<td class="parametervalue">3</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DO_TEST_BENCH_WIRING</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">DRIVEN_SIM_VALUE</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">EDGE_TYPE</td>
|
|
<td class="parametervalue">NONE</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">FREQ</td>
|
|
<td class="parametervalue">100000000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_IN</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_OUT</td>
|
|
<td class="parametervalue">1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">HAS_TRI</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">IRQ_TYPE</td>
|
|
<td class="parametervalue">NONE</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">RESET_VALUE</td>
|
|
<td class="parametervalue">7</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph_pb_cpu_0"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph_pb_cpu_0</h2>altera_avalon_mm_bridge v20.1.0
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_clk">subsys_periph_periph_clk</a>
|
|
</td>
|
|
<td class="from">out_clk  </td>
|
|
<td class="main" rowspan="19">subsys_periph_pb_cpu_0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_rst_in">subsys_periph_periph_rst_in</a>
|
|
</td>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_hps_agilex_hps">subsys_hps_agilex_hps</a>
|
|
</td>
|
|
<td class="from">lwhps2fpga  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">m0  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_sysid">subsys_periph_sysid</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  control_slave</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">m0  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_led_pio">subsys_periph_led_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  s1</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">m0  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_dipsw_pio">subsys_periph_dipsw_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  s1</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">m0  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_button_pio">subsys_periph_button_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  s1</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph_periph_clk"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph_periph_clk</h2>altera_clock_bridge v19.2.0
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_clk_100">clk_100</a>
|
|
</td>
|
|
<td class="from">out_clk  </td>
|
|
<td class="main" rowspan="16">subsys_periph_periph_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  in_clk</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_clk  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_sysid">subsys_periph_sysid</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_clk  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_pb_cpu_0">subsys_periph_pb_cpu_0</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_clk  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_led_pio">subsys_periph_led_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_clk  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_dipsw_pio">subsys_periph_dipsw_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_clk  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_button_pio">subsys_periph_button_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph_periph_rst_in"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph_periph_rst_in</h2>altera_reset_bridge v19.2.0
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_rst_in">rst_in</a>
|
|
</td>
|
|
<td class="from">out_reset  </td>
|
|
<td class="main" rowspan="16">subsys_periph_periph_rst_in</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  in_reset</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_reset  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_sysid">subsys_periph_sysid</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_reset  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_led_pio">subsys_periph_led_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_reset  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_dipsw_pio">subsys_periph_dipsw_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_reset  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_button_pio">subsys_periph_button_pio</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="from">out_reset  </td>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_pb_cpu_0">subsys_periph_pb_cpu_0</a>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td></td>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>(none)</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<a name="module_subsys_periph_sysid"> </a>
|
|
<div>
|
|
<hr/>
|
|
<h2>subsys_periph_sysid</h2>altera_avalon_sysid_qsys v19.1.7
|
|
<br/>
|
|
<div class="greydiv">
|
|
<table class="connectionboxes">
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_pb_cpu_0">subsys_periph_pb_cpu_0</a>
|
|
</td>
|
|
<td class="from">m0  </td>
|
|
<td class="main" rowspan="8">subsys_periph_sysid</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  control_slave</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_clk">subsys_periph_periph_clk</a>
|
|
</td>
|
|
<td class="from">out_clk  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  clk</td>
|
|
</tr>
|
|
<tr style="height:6px">
|
|
<td></td>
|
|
</tr>
|
|
<tr>
|
|
<td class="neighbor" rowspan="2">
|
|
<a href="#module_subsys_periph_periph_rst_in">subsys_periph_periph_rst_in</a>
|
|
</td>
|
|
<td class="from">out_reset  </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="to">  reset</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<br/>
|
|
<br/>
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Parameters</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">generateLegacySim</td>
|
|
<td class="parametervalue">false</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>  
|
|
<table class="flowbox">
|
|
<tr>
|
|
<td class="parametersbox">
|
|
<h2>Software Assignments</h2>
|
|
<table>
|
|
<tr>
|
|
<td class="parametername">ID</td>
|
|
<td class="parametervalue">-1395275010</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="parametername">TIMESTAMP</td>
|
|
<td class="parametervalue">0</td>
|
|
</tr>
|
|
</table>
|
|
</td>
|
|
</tr>
|
|
</table>
|
|
</div>
|
|
<table class="blueBar">
|
|
<tr>
|
|
<td class="l">generation took 0.01 seconds</td>
|
|
<td class="r">rendering took 0.08 seconds</td>
|
|
</tr>
|
|
</table>
|
|
</body>
|
|
</html>
|