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thejayman77 ec82764bef Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-06-29 20:10:50 -04:00

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component peripheral_subsys is
port (
button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
button_pio_irq_irq : out std_logic; -- irq
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
dipsw_pio_irq_irq : out std_logic; -- irq
led_pio_external_connection_in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port
led_pio_external_connection_out_port : out std_logic_vector(2 downto 0); -- out_port
pb_cpu_0_s0_waitrequest : out std_logic; -- waitrequest
pb_cpu_0_s0_readdata : out std_logic_vector(31 downto 0); -- readdata
pb_cpu_0_s0_readdatavalid : out std_logic; -- readdatavalid
pb_cpu_0_s0_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
pb_cpu_0_s0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
pb_cpu_0_s0_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
pb_cpu_0_s0_write : in std_logic := 'X'; -- write
pb_cpu_0_s0_read : in std_logic := 'X'; -- read
pb_cpu_0_s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
pb_cpu_0_s0_debugaccess : in std_logic := 'X'; -- debugaccess
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component peripheral_subsys;