Files
thejayman77 ec82764bef Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-06-29 20:10:50 -04:00

30 lines
2.4 KiB
Plaintext

set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_VERSION "26.1"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_reset_bridge"
set_global_assignment -entity "rst_in" -library "rst_in" -name PRE_COMPILED_MODULE "ON"
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_FILE [file join $::quartus(qip_path) "../rst_in.ip"]
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_TYPE "altera_reset_bridge"
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_VERSION "19.2.0"
set_global_assignment -entity "rst_in" -library "rst_in" -name OCS_IP_HASH "xf2264i"
set_global_assignment -library "rst_in" -name SOPCINFO_FILE [file join $::quartus(qip_path) "rst_in.sopcinfo"]
set_global_assignment -entity "rst_in" -library "rst_in" -name SLD_INFO "QSYS_NAME rst_in HAS_SOPCINFO 1 GENERATION_ID 0"
set_global_assignment -library "rst_in" -name MISC_FILE [file join $::quartus(qip_path) "rst_in.cmp"]
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "rst_in" -name MISC_FILE [file join $::quartus(qip_path) "../rst_in.ip"]
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_NAME "cnN0X2lu"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "rst_in" -library "rst_in" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -library "rst_in" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/rst_in.v"]