thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
105 lines
3.3 KiB
XML
105 lines
3.3 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2026.05.11.21:03:48"
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outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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type="Integer"
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defaultValue="0"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_UNIQUE_ID"
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type="String"
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defaultValue=""
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_FAMILY"
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type="String"
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defaultValue="Agilex 5"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE"
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type="String"
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defaultValue="A5EB013BB23BE4SCS"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_SPEEDGRADE"
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type="String"
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defaultValue="6"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_BOARD"
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type="String"
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defaultValue="default"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_IN_CLK_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_IN_CLK_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_IN_CLK_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<interface name="in_clk" kind="clock" start="0">
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<property name="clockRate" value="0" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="in_clk" direction="input" role="clk" width="1" />
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</interface>
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<interface name="out_clk" kind="clock" start="1">
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<property name="associatedDirectClock" value="in_clk" />
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<property name="clockRate" value="100000000" />
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<property name="clockRateKnown" value="true" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="out_clk" direction="output" role="clk" width="1" />
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</interface>
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</perimeter>
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<entity kind="clk_100" version="1.0" name="clk_100">
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
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<parameter name="AUTO_IN_CLK_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
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<parameter name="AUTO_BOARD" value="default" />
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<parameter name="AUTO_IN_CLK_RESET_DOMAIN" value="-1" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
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<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN" value="-1" />
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<generatedFiles>
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<file
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path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/synth/clk_100.v"
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attributes="CONTAINS_INLINE_CONFIGURATION" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100/synth/clk_100.v"
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attributes="CONTAINS_INLINE_CONFIGURATION" />
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</childGeneratedFiles>
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<sourceFiles>
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<file
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path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/clk_100.ip" />
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</sourceFiles>
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<childSourceFiles/>
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<messages>
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<message level="Info" culprit="clk_100">"Generating: clk_100"</message>
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</messages>
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</entity>
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</deploy>
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