# Ch419 — request-path timing root cut plus rabbit/bench completion (prefit)

## Objective

Make one owner compile carry two concrete advances:

1. remove the actual Ch418 310 MHz setup topology instead of rerolling placement;
2. append a bounded set of authentic missing rabbit/bench draws to the accepted
   Ch417 framebuffer, without regenerating or perturbing its 263 accepted epochs.

Ch418's captured 512x448-to-640x480 presentation mapping is retained unchanged.

## Ch418 fit diagnosis

The 2026-07-18 owner fit completed placement and routing but failed only the
EMIF setup domain:

- setup WNS `-0.388 ns`, TNS `-7.218 ns` at 310 MHz;
- hold `0.000 ns` and every other reported timing check clean;
- 38,328 / 46,800 ALMs (82%), 336 / 358 RAM blocks (94%).

The first nine setup endpoints are the same structural family:

```
u_zc_emit|req_rd
  -> u_zc_emit|u_req|mem...ram_block...~reg1 (RAM enable)
```

`req_rd` has netlist fan-out 747.  The worst paths contain no logic levels:
`3.370 ns` data delay is almost entirely the `3.035 ns` interconnect route to
the wide request FIFO's physical RAM enables.  This is not a scanout-mapping
path and is not a seed-quality diagnosis.

The next distinct setup family is `-0.331 ns` inside `u_lpddr_rd_arb`, from a
duplicated encoded `grant` bit back into `grant` through response-completion
selection.

## Structural timing cuts

### Request FIFO RAM enable

In `gs_async_fifo` registered-read mode, the inferred synchronous RAM head is
now sampled every read clock instead of qualifying every physical RAM bank with
`rd`.  The read pointer still advances only on an accepted pop and `rdata`
retains its one-cycle registered-read contract.

This removes `req_rd` from the 747-load RAM-enable net entirely; it is a
topology change, not a fitter hint or another seed roll.

### Read-arbiter grant release

`gs_lpddr_rd_arb` now registers the terminal accepted `RLAST` handshake and
releases ownership on the following cycle.  `ARVALID/ARREADY` are masked after
the address handshake and throughout the deliberate release bubble, so a
selected requester cannot accidentally issue a second address.

This breaks the requester-`RREADY` selection cone out of the encoded grant
register's direct D path while preserving AXI ownership through response
acceptance.

## Fidelity batch

The accepted `zsrt139f17` fixture remains byte-for-byte intact.  Ch419 appends
21 authentic opaque PSMT8 draw runs missing between the accepted group heads in
the PCSX2 rabbit/bench region:

```
71361, 71574, 72000, 72213, 72639, 72852, 73278,
73491, 73917, 74130, 74556, 74769, 75195, 75408,
75834, 76047, 76473, 76686, 77112, 77325, 77538
```

Capacity-safe grouping produces 20 appended epochs and 7,496 independently
covered reference pixels.  The merged `zsrt139f18` scene has 283 epochs total.
Persistent authentic Z decides visibility against the accepted base.

This is deliberately bounded.  An exhaustive supported-draw plan expanded to
6,977 epochs and was rejected as operationally useless before deployment.

## Prefit verification

The full production-control replay uses the exact board gradient-divider
selection and settle FSM, the modified request FIFO, the modified read arbiter,
one persistent color/Z memory, and all 283 chronological epochs:

- 1,177,489 fragments fed;
- 984,845 fragments passed authentic Z;
- 283 ordered markers and 283 fresh drains;
- zero fragment drops, color overflow, or AXI response errors;
- final Z mismatch `0 / 307,200`;
- final color mismatch `0 / 235,963` written pixels;
- testbench `PASS` with `errors=0`.

Final framebuffer SHA-256:

`a88f1f6c926dd0db2b72ae2873c399e7dc5666f8003190184c34d360b13a5f44`

Relative to the accepted Ch417 production replay, the tail changes 4,446
framebuffer pixels at `x=342..416, y=214..363`, the intended right-center
rabbit/bench region.  Twelve pixels add previously empty coverage; the rest
replace Z-visible surface color/detail.  Ch417's prior hash was:

`3d22b4421194d444677f3bc9f938e43fd856c6615b92585a10209093d982a625`

Supporting regressions also pass:

- async FIFO: 3,284 exact writes/reads, no duplicate/drop;
- read arbiter contention/priority: PASS;
- Z/color emit: 1,500 fragments across three epochs, exact;
- horizontal-stretch scanout: 600 pixels exact, no underflow/read errors;
- PSMCT32 linebuffer: 49,152 pixels exact, no underflow/read errors;
- full-frame scanout: 105,968 pixels checked, exact beat count, no errors;
- concurrent scanout/reload/probe: 16,384 pixels exact;
- host scheduler build and complete 283-epoch asset dry-run: PASS;
- board staging set: 323 unique assets, 21,733,472 bytes (duplicates removed);
- relevant `git diff --check`: PASS.

## Owner fit gate

This is ready for one owner-controlled Quartus 26.1 GUI compile.  It is not
claimed timing-clean until that report exists.

Acceptance for the fit:

- the `req_rd -> request RAM enable` family is absent (not merely moved down);
- the encoded read-arbiter `grant -> grant` response family is absent or clean;
- setup, hold, recovery, removal, and minimum pulse all close;
- synthesis still infers the request FIFO RAM and remains inside device limits.

After a clean fit, deploy the RBF, stage `zsrt139f18`, run the 283-epoch board
scene, and require board framebuffer equality with the production replay hash
above before accepting the chapter.

## Owner fit result — 2026-07-18 11:07

The fit was successful, but setup remained narrowly red:

- setup improved from `-0.388 ns / -7.218 ns` to
  `-0.115 ns / -1.150 ns`;
- hold improved to `+0.001 ns`; all other timing checks remained clean;
- ALMs decreased from 38,328 to 38,234; RAM use remained 336 / 358.

Both Ch419 targets disappeared completely from the violated top ten:

- no `req_rd -> request RAM enable` path;
- no encoded read-arbiter `grant -> grant` path.

All ten remaining violations are one newly exposed zero-logic family:

```
u_zc_emit|u_req|rbin[6]
  -> u_zc_emit|u_req|mem...ram_block...portbaddr[6]
```

The launch bit has fan-out 713.  Of the `3.192 ns` data delay, `2.892 ns`
(91%) is routing.  Ch419 therefore succeeded as a structural peel, but is not
accepted for deployment.  Ch420 applies the corresponding dedicated read-RAM
address stage before the next owner fit.