Intel Corporation
dipsw_pio
altera_avalon_pio_inst
19.2.4
clk
clk
clk
clockRate
Clock rate
0
externallyDriven
Externally driven
false
ptfSchematicName
PTF schematic name
reset
reset_n
reset_n
associatedClock
Associated clock
clk
synchronousEdges
Synchronous edges
DEASSERT
s1
address
address
write_n
write_n
writedata
writedata
chipselect
chipselect
readdata
readdata
addressAlignment
Agent addressing
NATIVE
addressGroup
Address group
0
addressSpan
Address span
4
addressUnits
Address units
WORDS
alwaysBurstMaxBurst
Always burst maximum burst
false
associatedClock
Associated clock
clk
associatedReset
Associated reset
reset
bitsPerSymbol
Bits per symbol
8
bridgedAddressOffset
Bridged Address Offset
0
bridgesToMaster
Bridges to host
burstOnBurstBoundariesOnly
Burst on burst boundaries only
false
burstcountUnits
Burstcount units
WORDS
constantBurstBehavior
Constant burst behavior
false
explicitAddressSpan
Explicit address span
0
holdTime
Hold
0
interleaveBursts
Interleave bursts
false
isBigEndian
Big endian
false
isFlash
Flash memory
false
isMemoryDevice
Memory device
false
isNonVolatileStorage
Non-volatile storage
false
linewrapBursts
Linewrap bursts
false
maximumPendingReadTransactions
Maximum pending read transactions
0
maximumPendingWriteTransactions
Maximum pending write transactions
0
minimumReadLatency
minimumReadLatency
1
minimumResponseLatency
Minimum response latency
1
minimumUninterruptedRunLength
Minimum uninterrupted run length
1
prSafe
Partial Reconfiguration Safe
false
printableDevice
Can receive stdout/stderr
false
readLatency
Read latency
0
readWaitStates
Read wait states
1
readWaitTime
Read wait
1
registerIncomingSignals
Register incoming signals
false
registerOutgoingSignals
Register outgoing signals
false
setupTime
Setup
0
timingUnits
Timing units
Cycles
transparentBridge
Transparent bridge
false
waitrequestAllowance
Waitrequest allowance
0
waitrequestTimeout
Waitrequest Timeout
1024
wellBehavedWaitrequest
Well-behaved waitrequest
false
writeLatency
Write latency
0
writeWaitStates
Write wait states
0
writeWaitTime
Write wait
0
dfhFeatureGuid
Feature GUID
0
dfhGroupId
Group ID
0
dfhParameterId
ID
dfhParameterName
Name
dfhParameterVersion
Version
dfhParameterData
Data (HEX/DEC)
dfhParameterDataLength
Data length
dfhFeatureMajorVersion
Feature major version
0
dfhFeatureMinorVersion
Feature minor version
0
dfhFeatureId
Feature ID
35
dfhFeatureType
Feature Type
3
embeddedsw.configuration.isFlash
0
embeddedsw.configuration.isMemoryDevice
0
embeddedsw.configuration.isNonVolatileStorage
0
embeddedsw.configuration.isPrintableDevice
0
external_connection
export
in_port
associatedClock
associatedClock
associatedReset
associatedReset
prSafe
Partial Reconfiguration Safe
false
irq
irq
irq
associatedAddressablePoint
Associated addressable interface
dipsw_pio.s1
associatedClock
Associated clock
clk
associatedReset
Associated reset
reset
bridgedReceiverOffset
Bridged receiver offset
0
bridgesToReceiver
Bridges to receiver
irqScheme
Interrupt scheme
NONE
embeddedsw.dts.irq.tx_type
RISING_EDGE
QUARTUS_SYNTH
:quartus.altera.com:
QUARTUS_SYNTH
QUARTUS_SYNTH
altera_avalon_pio
QUARTUS_SYNTH
clk
in
STD_LOGIC
QUARTUS_SYNTH
reset_n
in
STD_LOGIC
QUARTUS_SYNTH
address
in
0
1
STD_LOGIC_VECTOR
QUARTUS_SYNTH
write_n
in
STD_LOGIC
QUARTUS_SYNTH
writedata
in
0
31
STD_LOGIC_VECTOR
QUARTUS_SYNTH
chipselect
in
STD_LOGIC
QUARTUS_SYNTH
readdata
out
0
31
STD_LOGIC_VECTOR
QUARTUS_SYNTH
in_port
in
0
3
STD_LOGIC_VECTOR
QUARTUS_SYNTH
irq
out
STD_LOGIC
QUARTUS_SYNTH
Intel Corporation
dipsw_pio
altera_avalon_pio
19.2.4
bitClearingEdgeCapReg
Enable bit-clearing for edge capture register
true
bitModifyingOutReg
Enable individual bit setting/clearing
false
captureEdge
Synchronously capture
true
direction
Direction
Input
edgeType
Edge Type
FALLING
generateIRQ
Generate IRQ
true
irqType
IRQ Type
EDGE
resetValue
Output Port Reset Value
0
simDoTestBenchWiring
Hardwire PIO inputs in test bench
false
simDrivenValue
Drive inputs to field.
0
width
Width (1-32 bits)
4
clockRate
clockRate
100000000
DEVICE_FAMILY
DEVICE_FAMILY
Agilex 5
embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
1
embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER
0
embeddedsw.CMacro.CAPTURE
1
embeddedsw.CMacro.DATA_WIDTH
4
embeddedsw.CMacro.DO_TEST_BENCH_WIRING
0
embeddedsw.CMacro.DRIVEN_SIM_VALUE
0
embeddedsw.CMacro.EDGE_TYPE
FALLING
embeddedsw.CMacro.FREQ
100000000
embeddedsw.CMacro.HAS_IN
1
embeddedsw.CMacro.HAS_OUT
0
embeddedsw.CMacro.HAS_TRI
0
embeddedsw.CMacro.IRQ_TYPE
EDGE
embeddedsw.CMacro.RESET_VALUE
0
embeddedsw.dts.compatible
altr,pio-1.0
embeddedsw.dts.group
gpio
embeddedsw.dts.name
pio
embeddedsw.dts.params.altr,gpio-bank-width
4
embeddedsw.dts.params.altr,interrupt-type
2
embeddedsw.dts.params.altr,interrupt_type
2
embeddedsw.dts.params.edge_type
1
embeddedsw.dts.params.level_trigger
0
embeddedsw.dts.params.resetvalue
0
embeddedsw.dts.vendor
altr
board
Board
default
device
Device
A5ED065BB32AE6SR0
deviceFamily
Device family
Agilex 5
deviceSpeedGrade
Device Speed Grade
6
generationId
Generation Id
0
bonusData
bonusData
bonusData
{
element altera_avalon_pio_inst
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
hideFromIPCatalog
Hide from IP Catalog
false
lockedInterfaceDefinition
lockedInterfaceDefinition
<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>s1</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>address</name>
<role>address</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>write_n</name>
<role>write_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>chipselect</name>
<role>chipselect</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>NATIVE</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>4</value>
</entry>
<entry>
<key>addressUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>0</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>1</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>1</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
<cmsisInfo>
<cmsisSrcFileContents><?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
<peripherals>
<peripheral>
<name>altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device> </cmsisSrcFileContents>
<addressGroup></addressGroup>
<cmsisVars/>
</cmsisInfo>
</interface>
<interface>
<name>external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_port</name>
<role>export</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>irq</name>
<type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
<name>irq</name>
<role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.dts.irq.tx_type</key>
<value>RISING_EDGE</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
<value>dipsw_pio.s1</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bridgedReceiverOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToReceiver</key>
</entry>
<entry>
<key>irqScheme</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
systemInfos
systemInfos
<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
<entry>
<key>s1</key>
<value>
<connectionPointName>s1</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='s1' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>32</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition>
dflBitArray
dflBitArray
cpuInfo
cpuInfo
false
false