Info: Generated by version: 25.3.1 build 100
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top.qsys --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top --family="Agilex 5" --part=A5EB013BB23BE4SCS
Progress: Loading qsys/qsys_top.qsys
Progress: Reading input file
Progress: Parameterizing module clk_100
Progress: Parameterizing module rst_in
Progress: Parameterizing module subsys_hps
Progress: Parameterizing module subsys_periph
Progress: Parameterizing module user_rst_clkgate_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: qsys_top: "Transforming system: qsys_top"
Info: Interconnect is inserted between master subsys_hps.lwhps2fpga and slave subsys_periph.pb_cpu_0_s0 because the master is of type axi4 and the slave is of type avalon.
Warning: subsys_hps.f2h_irq0_in: Cannot connect clock for irq_mapper.sender
Warning: subsys_hps.f2h_irq0_in: Cannot connect reset for irq_mapper.sender
Info: qsys_top: "Naming system components in system: qsys_top"
Info: qsys_top: "Processing generation queue"
Info: qsys_top: "Generating: qsys_top"
Info: qsys_top: "Generating: clk_100"
Info: qsys_top: "Generating: rst_in"
Info: qsys_top: "Generating: user_rst_clkgate_0"
Info: qsys_top: "Generating: qsys_top_altera_mm_interconnect_1920_6wkpj2i"
Info: qsys_top: "Generating: qsys_top_altera_irq_mapper_2001_lp4cnei"
Info: qsys_top: "Generating: altera_reset_controller"
Info: qsys_top: "Generating: qsys_top_altera_merlin_axi_translator_1986_4khp5ei"
Info: qsys_top: "Generating: qsys_top_altera_merlin_slave_translator_191_xg7rzxi"
Info: qsys_top: "Generating: qsys_top_altera_merlin_axi_master_ni_19116_f5viiry"
Info: qsys_top: "Generating: qsys_top_altera_merlin_slave_agent_1930_jxauz3i"
Info: qsys_top: "Generating: qsys_top_altera_avalon_sc_fifo_1932_22gxxgi"
Info: qsys_top: "Generating: qsys_top_altera_merlin_router_1921_ox5xuhq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_router_1921_sxavatq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy"
Info: my_altera_avalon_st_pipeline_stage: "Generating: my_altera_avalon_st_pipeline_stage"
Info: qsys_top: "Generating: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q"
Info: qsys_top: "Generating: qsys_top_altera_merlin_multiplexer_1922_666s25q"
Info: qsys_top: "Generating: qsys_top_altera_merlin_demultiplexer_1921_qyizksq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_multiplexer_1922_yjgptii"
Info: qsys_top: "Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"
Info: qsys_top: "Generating: qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"
Info: qsys_top: Done "qsys_top" with 23 modules, 32 files
Info: Finished: Create HDL design files for synthesis