Altera Corporation
qsys_top
qsys_top
1.0
$${FILENAME}
$${FILENAME}
1.0
Systems
QsysPro
board
Board
default
bonusData
bonusData
bonusData
{
element clk_100
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element rst_in
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element subsys_hps
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element subsys_periph
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element user_rst_clkgate_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
}
cpuInfo
cpuInfo
designId
designId
device
Device
A5EB013BB23BE4SCS
deviceFamily
Device family
Agilex 5
deviceSpeedGrade
Device Speed Grade
4
dflBitArray
dflBitArray
fabricMode
fabricMode
QSYS
generateLegacySim
generateLegacySim
false
generationId
Generation Id
0
globalResetBus
Global reset
false
hdlLanguage
hdlLanguage
VERILOG
hideFromIPCatalog
Hide from IP Catalog
false
lockedInterfaceDefinition
lockedInterfaceDefinition
sopcBorderPoints
Use SOPC Builder port naming
false
systemHash
systemHash
0
systemInfos
systemInfos
<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>clk_100</key>
<value>
<connectionPointName>clk_100</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
<entry>
<key>emif_hps_emif_ref_clk_0</key>
<value>
<connectionPointName>emif_hps_emif_ref_clk_0</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
</entry>
<entry>
<key>CLOCK_RATE</key>
</entry>
<entry>
<key>RESET_DOMAIN</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
<entry>
<key>f2h_irq1_in</key>
<value>
<connectionPointName>f2h_irq1_in</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>INTERRUPTS_USED</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
<entry>
<key>f2sdram</key>
<value>
<connectionPointName>f2sdram</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CPU_INFO_ID</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='subsys_hps.f2sdram' start='0x0' end='0x100000000' datawidth='256' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>32</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
<value>256</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>subsys_hps_hps2fpga</key>
<value>
<connectionPointName>subsys_hps_hps2fpga</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfosDefinition>
systemScripts
systemScripts
testBenchDutName
Use Test Bench Naming Pattern
timeStamp
timeStamp
0
useTestBenchNamingPattern
Use Test Bench Naming Pattern
false
Altera Corporation
clk_100
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>100000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_clock_bridge</className>
<version>19.2.0</version>
<displayName>Clock Bridge IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>DERIVED_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>in_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>in_clk</key>
<value>
<connectionPointName>in_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>0</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>out_clk</key>
<value>
<connectionPointName>out_clk</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>in_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_clk</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>in_clk</value>
</entry>
<entry>
<key>clockRate</key>
<value>100000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>clk_100</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>clk_100</fileSetName>
<fileSetFixedName>clk_100</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>clk_100</fileSetName>
<fileSetFixedName>clk_100</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>clk_100</fileSetName>
<fileSetFixedName>clk_100</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>clk_100</fileSetName>
<fileSetFixedName>clk_100</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>clk_100</fileSetName>
<fileSetFixedName>clk_100</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_clock_bridge_inst
logicalView
Logical view
ip/qsys_top/clk_100.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
System Verilog Interface definition
transformParameters
Transform Parameters
<transformParameterDescriptorDefinitionList/>
Altera Corporation
rst_in
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>in_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
<value>in_reset</value>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>in_reset</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>altera_reset_bridge</className>
<version>19.2.0</version>
<displayName>Reset Bridge IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_CLK_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos/>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>in_reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>in_reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>out_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>out_reset_n</name>
<role>reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
<value>in_reset</value>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>in_reset</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>rst_in</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>rst_in</fileSetName>
<fileSetFixedName>rst_in</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>rst_in</fileSetName>
<fileSetFixedName>rst_in</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>rst_in</fileSetName>
<fileSetFixedName>rst_in</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>rst_in</fileSetName>
<fileSetFixedName>rst_in</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>rst_in</fileSetName>
<fileSetFixedName>rst_in</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
altera_reset_bridge_inst
logicalView
Logical view
ip/qsys_top/rst_in.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
System Verilog Interface definition
transformParameters
Transform Parameters
<transformParameterDescriptorDefinitionList/>
Altera Corporation
subsys_hps
altera_generic_component
1.0
bspCpu
BSP CPU
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>h2f_reset</name>
<type>reset</type>
<isStart>true</isStart>
<ports>
<port>
<name>h2f_reset_reset</name>
<role>reset</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedDirectReset</key>
</entry>
<entry>
<key>associatedResetSinks</key>
<value>none</value>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps2fpga_clk_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga_rst</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps2fpga_rst_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps2fpga</name>
<type>axi4</type>
<isStart>true</isStart>
<ports>
<port>
<name>hps2fpga_awid</name>
<role>awid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awaddr</name>
<role>awaddr</role>
<direction>Output</direction>
<width>38</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awlen</name>
<role>awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awsize</name>
<role>awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awburst</name>
<role>awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awlock</name>
<role>awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awcache</name>
<role>awcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awprot</name>
<role>awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awvalid</name>
<role>awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_awready</name>
<role>awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wdata</name>
<role>wdata</role>
<direction>Output</direction>
<width>128</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wstrb</name>
<role>wstrb</role>
<direction>Output</direction>
<width>16</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wlast</name>
<role>wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wvalid</name>
<role>wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_wready</name>
<role>wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bid</name>
<role>bid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bresp</name>
<role>bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bvalid</name>
<role>bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_bready</name>
<role>bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arid</name>
<role>arid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_araddr</name>
<role>araddr</role>
<direction>Output</direction>
<width>38</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arlen</name>
<role>arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arsize</name>
<role>arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arburst</name>
<role>arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arlock</name>
<role>arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arcache</name>
<role>arcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arprot</name>
<role>arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arvalid</name>
<role>arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_arready</name>
<role>arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rid</name>
<role>rid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rdata</name>
<role>rdata</role>
<direction>Input</direction>
<width>128</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rresp</name>
<role>rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rlast</name>
<role>rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rvalid</name>
<role>rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps2fpga_rready</name>
<role>rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>hps2fpga_clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>hps2fpga_rst</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
<entry>
<key>noRepeatedIdsBetweenSubordinates</key>
<value>0</value>
</entry>
<entry>
<key>issuesINCRBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesWRAPBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesFIXEDBursts</key>
<value>true</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>lwhps2fpga_clk_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga_rst</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>lwhps2fpga_rst_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>lwhps2fpga</name>
<type>axi4</type>
<isStart>true</isStart>
<ports>
<port>
<name>lwhps2fpga_awid</name>
<role>awid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awaddr</name>
<role>awaddr</role>
<direction>Output</direction>
<width>29</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awlen</name>
<role>awlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awsize</name>
<role>awsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awburst</name>
<role>awburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awlock</name>
<role>awlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awcache</name>
<role>awcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awprot</name>
<role>awprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awvalid</name>
<role>awvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_awready</name>
<role>awready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wdata</name>
<role>wdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wstrb</name>
<role>wstrb</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wlast</name>
<role>wlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wvalid</name>
<role>wvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_wready</name>
<role>wready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bid</name>
<role>bid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bresp</name>
<role>bresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bvalid</name>
<role>bvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_bready</name>
<role>bready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arid</name>
<role>arid</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_araddr</name>
<role>araddr</role>
<direction>Output</direction>
<width>29</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arlen</name>
<role>arlen</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arsize</name>
<role>arsize</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arburst</name>
<role>arburst</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arlock</name>
<role>arlock</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arcache</name>
<role>arcache</role>
<direction>Output</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arprot</name>
<role>arprot</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arvalid</name>
<role>arvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_arready</name>
<role>arready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rid</name>
<role>rid</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rdata</name>
<role>rdata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rresp</name>
<role>rresp</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rlast</name>
<role>rlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rvalid</name>
<role>rvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>lwhps2fpga_rready</name>
<role>rready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>lwhps2fpga_clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>lwhps2fpga_rst</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedIssuingCapability</key>
<value>16</value>
</entry>
<entry>
<key>enableConcurrentSubordinateAccess</key>
<value>0</value>
</entry>
<entry>
<key>noRepeatedIdsBetweenSubordinates</key>
<value>0</value>
</entry>
<entry>
<key>issuesINCRBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesWRAPBursts</key>
<value>true</value>
</entry>
<entry>
<key>issuesFIXEDBursts</key>
<value>true</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>h2f_warm_reset_handshake</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>h2f_warm_reset_handshake_reset_req</name>
<role>reset_req</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>h2f_warm_reset_handshake_reset_ack</name>
<role>reset_ack</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>hps_io</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>hps_io_hps_osc_clk</name>
<role>hps_osc_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data0</name>
<role>sdmmc_data0</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data1</name>
<role>sdmmc_data1</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_cclk</name>
<role>sdmmc_cclk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data2</name>
<role>sdmmc_data2</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_data3</name>
<role>sdmmc_data3</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_sdmmc_cmd</name>
<role>sdmmc_cmd</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_clk</name>
<role>usb0_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_stp</name>
<role>usb0_stp</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_dir</name>
<role>usb0_dir</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data0</name>
<role>usb0_data0</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data1</name>
<role>usb0_data1</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_nxt</name>
<role>usb0_nxt</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data2</name>
<role>usb0_data2</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data3</name>
<role>usb0_data3</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data4</name>
<role>usb0_data4</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data5</name>
<role>usb0_data5</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data6</name>
<role>usb0_data6</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_usb0_data7</name>
<role>usb0_data7</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_tx_clk</name>
<role>emac0_tx_clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_tx_ctl</name>
<role>emac0_tx_ctl</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rx_clk</name>
<role>emac0_rx_clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rx_ctl</name>
<role>emac0_rx_ctl</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd0</name>
<role>emac0_txd0</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd1</name>
<role>emac0_txd1</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd0</name>
<role>emac0_rxd0</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd1</name>
<role>emac0_rxd1</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd2</name>
<role>emac0_txd2</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_txd3</name>
<role>emac0_txd3</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd2</name>
<role>emac0_rxd2</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_emac0_rxd3</name>
<role>emac0_rxd3</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_mdio0_mdio</name>
<role>mdio0_mdio</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_mdio0_mdc</name>
<role>mdio0_mdc</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_uart1_tx</name>
<role>uart1_tx</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_uart1_rx</name>
<role>uart1_rx</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_i2c1_sda</name>
<role>i2c1_sda</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_i2c1_scl</name>
<role>i2c1_scl</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio28</name>
<role>gpio28</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio34</name>
<role>gpio34</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio40</name>
<role>gpio40</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>hps_io_gpio41</name>
<role>gpio41</role>
<direction>Bidir</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2h_irq1_in</name>
<type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
<name>f2h_irq1_in_irq</name>
<role>irq</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
</entry>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
<value></value>
</entry>
<entry>
<key>irqMap</key>
</entry>
<entry>
<key>irqScheme</key>
<value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2h_irq0_in</name>
<type>interrupt</type>
<isStart>true</isStart>
<ports>
<port>
<name>f2h_irq0_in_irq</name>
<role>irq</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
</entry>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
<value></value>
</entry>
<entry>
<key>irqMap</key>
</entry>
<entry>
<key>irqScheme</key>
<value>INDIVIDUAL_REQUESTS</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_clk_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram_rst</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_rst_reset</name>
<role>reset</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>f2sdram</name>
<type>axi4</type>
<isStart>false</isStart>
<ports>
<port>
<name>f2sdram_araddr</name>
<role>araddr</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arburst</name>
<role>arburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arcache</name>
<role>arcache</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arid</name>
<role>arid</role>
<direction>Input</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arlen</name>
<role>arlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arlock</name>
<role>arlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arprot</name>
<role>arprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arqos</name>
<role>arqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arready</name>
<role>arready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arsize</name>
<role>arsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arvalid</name>
<role>arvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awaddr</name>
<role>awaddr</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awburst</name>
<role>awburst</role>
<direction>Input</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awcache</name>
<role>awcache</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awid</name>
<role>awid</role>
<direction>Input</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awlen</name>
<role>awlen</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awlock</name>
<role>awlock</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awprot</name>
<role>awprot</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awqos</name>
<role>awqos</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awready</name>
<role>awready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awsize</name>
<role>awsize</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awvalid</name>
<role>awvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bid</name>
<role>bid</role>
<direction>Output</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bready</name>
<role>bready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bresp</name>
<role>bresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_bvalid</name>
<role>bvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rdata</name>
<role>rdata</role>
<direction>Output</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rid</name>
<role>rid</role>
<direction>Output</direction>
<width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rlast</name>
<role>rlast</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rready</name>
<role>rready</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rresp</name>
<role>rresp</role>
<direction>Output</direction>
<width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_rvalid</name>
<role>rvalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wdata</name>
<role>wdata</role>
<direction>Input</direction>
<width>256</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wlast</name>
<role>wlast</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wready</name>
<role>wready</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wstrb</name>
<role>wstrb</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wvalid</name>
<role>wvalid</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_aruser</name>
<role>aruser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awuser</name>
<role>awuser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_wuser</name>
<role>wuser</role>
<direction>Input</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_buser</name>
<role>buser</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_arregion</name>
<role>arregion</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_ruser</name>
<role>ruser</role>
<direction>Output</direction>
<width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>f2sdram_awregion</name>
<role>awregion</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
<value>f2sdram_clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>f2sdram_rst</value>
</entry>
<entry>
<key>optionalAssociatedReset</key>
<value>false</value>
</entry>
<entry>
<key>trustzoneAware</key>
<value>true</value>
</entry>
<entry>
<key>wakeupSignals</key>
<value>false</value>
</entry>
<entry>
<key>uniqueIdSupport</key>
<value>false</value>
</entry>
<entry>
<key>poison</key>
<value>false</value>
</entry>
<entry>
<key>traceSignals</key>
<value>false</value>
</entry>
<entry>
<key>isTranslator</key>
<value>false</value>
</entry>
<entry>
<key>maximumOutstandingReads</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingWrites</key>
<value>1</value>
</entry>
<entry>
<key>maximumOutstandingTransactions</key>
<value>1</value>
</entry>
<entry>
<key>dataCheck</key>
<value>false</value>
</entry>
<entry>
<key>addressCheck</key>
<value>false</value>
</entry>
<entry>
<key>securityAttribute</key>
<value>false</value>
</entry>
<entry>
<key>userData</key>
<value>false</value>
</entry>
<entry>
<key>readAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>writeAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>combinedAcceptanceCapability</key>
<value>16</value>
</entry>
<entry>
<key>readDataReorderingDepth</key>
<value>1</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
<entry>
<key>noNarrowTransfer</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>emif_hps_emif_mem_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>emif_hps_emif_mem_0_mem_cs</name>
<role>mem_cs</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>emif_hps_emif_mem_0_mem_ca</name>
<role>mem_ca</role>
<direction>Output</direction>
<width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>emif_hps_emif_mem_0_mem_cke</name>
<role>mem_cke</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>emif_hps_emif_mem_0_mem_dq</name>
<role>mem_dq</role>
<direction>Bidir</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>emif_hps_emif_mem_0_mem_dqs_t</name>
<role>mem_dqs_t</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>emif_hps_emif_mem_0_mem_dqs_c</name>
<role>mem_dqs_c</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>emif_hps_emif_mem_0_mem_dmi</name>
<role>mem_dmi</role>
<direction>Bidir</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>emif_hps_emif_mem_ck_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>emif_hps_emif_mem_ck_0_mem_ck_t</name>
<role>mem_ck_t</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>emif_hps_emif_mem_ck_0_mem_ck_c</name>
<role>mem_ck_c</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>emif_hps_emif_mem_reset_n</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>emif_hps_emif_mem_reset_n_mem_reset_n</name>
<role>mem_reset_n</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>emif_hps_emif_oct_0</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>emif_hps_emif_oct_0_oct_rzqin</name>
<role>oct_rzqin</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>emif_hps_emif_ref_clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>emif_hps_emif_ref_clk_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>hps_subsys</className>
<displayName>hps_subsys</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>default</parameterDefaultValue>
<parameterName>AUTO_BOARD</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>BOARD</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>A5EB013BB23BE4SCS</parameterDefaultValue>
<parameterName>AUTO_DEVICE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>Agilex 5</parameterDefaultValue>
<parameterName>AUTO_DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>4</parameterDefaultValue>
<parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_EMIF_HPS_EMIF_REF_CLK_CLOCK_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>emif_hps_emif_ref_clk</systemInfoArgs>
<systemInfotype>CLOCK_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_EMIF_HPS_EMIF_REF_CLK_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>emif_hps_emif_ref_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_EMIF_HPS_EMIF_REF_CLK_RESET_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>emif_hps_emif_ref_clk</systemInfoArgs>
<systemInfotype>RESET_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_F2H_IRQ0_IN_INTERRUPTS_USED</parameterName>
<parameterType>java.math.BigInteger</parameterType>
<systemInfoArgs>f2h_irq0_in</systemInfoArgs>
<systemInfotype>INTERRUPTS_USED</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_F2H_IRQ1_IN_INTERRUPTS_USED</parameterName>
<parameterType>java.math.BigInteger</parameterType>
<systemInfoArgs>f2h_irq1_in</systemInfoArgs>
<systemInfotype>INTERRUPTS_USED</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_F2SDRAM_CLK_CLOCK_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>f2sdram_clk</systemInfoArgs>
<systemInfotype>CLOCK_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_F2SDRAM_CLK_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>f2sdram_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_F2SDRAM_CLK_RESET_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>f2sdram_clk</systemInfoArgs>
<systemInfotype>RESET_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>AUTO_F2SDRAM_CPU_INFO_ID</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>f2sdram</systemInfoArgs>
<systemInfotype>CPU_INFO_ID</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>AUTO_GENERATION_ID</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfotype>GENERATION_ID</systemInfotype>
</descriptor>
<descriptor>
<parameterName>AUTO_HPS2FPGA_ADDRESS_MAP</parameterName>
<parameterType>com.altera.entityinterfaces.moduleext.AddressMap</parameterType>
<systemInfoArgs>hps2fpga</systemInfoArgs>
<systemInfotype>ADDRESS_MAP</systemInfotype>
</descriptor>
<descriptor>
<parameterName>AUTO_HPS2FPGA_ADDRESS_WIDTH</parameterName>
<parameterType>com.altera.entityinterfaces.moduleext.AddressWidthType</parameterType>
<systemInfoArgs>hps2fpga</systemInfoArgs>
<systemInfotype>ADDRESS_WIDTH</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_HPS2FPGA_CLK_CLOCK_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>hps2fpga_clk</systemInfoArgs>
<systemInfotype>CLOCK_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_HPS2FPGA_CLK_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>hps2fpga_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_HPS2FPGA_CLK_RESET_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>hps2fpga_clk</systemInfoArgs>
<systemInfotype>RESET_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterName>AUTO_LWHPS2FPGA_ADDRESS_MAP</parameterName>
<parameterType>com.altera.entityinterfaces.moduleext.AddressMap</parameterType>
<systemInfoArgs>lwhps2fpga</systemInfoArgs>
<systemInfotype>ADDRESS_MAP</systemInfotype>
</descriptor>
<descriptor>
<parameterName>AUTO_LWHPS2FPGA_ADDRESS_WIDTH</parameterName>
<parameterType>com.altera.entityinterfaces.moduleext.AddressWidthType</parameterType>
<systemInfoArgs>lwhps2fpga</systemInfoArgs>
<systemInfotype>ADDRESS_WIDTH</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_LWHPS2FPGA_CLK_CLOCK_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>lwhps2fpga_clk</systemInfoArgs>
<systemInfotype>CLOCK_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_LWHPS2FPGA_CLK_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>lwhps2fpga_clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_LWHPS2FPGA_CLK_RESET_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>lwhps2fpga_clk</systemInfoArgs>
<systemInfotype>RESET_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>AUTO_UNIQUE_ID</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>UNIQUE_ID</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>emif_hps_emif_ref_clk</key>
<value>
<connectionPointName>emif_hps_emif_ref_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>-1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>-1</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>-1</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>f2h_irq0_in</key>
<value>
<connectionPointName>f2h_irq0_in</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>INTERRUPTS_USED</key>
<value>3</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>f2h_irq1_in</key>
<value>
<connectionPointName>f2h_irq1_in</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>INTERRUPTS_USED</key>
<value>-1</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>f2sdram</key>
<value>
<connectionPointName>f2sdram</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos>
<entry>
<key>CPU_INFO_ID</key>
<value></value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>f2sdram_clk</key>
<value>
<connectionPointName>f2sdram_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>1</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>hps2fpga</key>
<value>
<connectionPointName>hps2fpga</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value></value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>hps2fpga_clk</key>
<value>
<connectionPointName>hps2fpga_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>1</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>lwhps2fpga</key>
<value>
<connectionPointName>lwhps2fpga</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value><address-map><slave name='subsys_periph.pb_cpu_0_s0' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>17</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>lwhps2fpga_clk</key>
<value>
<connectionPointName>lwhps2fpga_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>1</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>hps_subsys</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>hps_subsys</fileSetName>
<fileSetFixedName>hps_subsys</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>hps_subsys</fileSetName>
<fileSetFixedName>hps_subsys</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>hps_subsys</fileSetName>
<fileSetFixedName>hps_subsys</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>hps_subsys</fileSetName>
<fileSetFixedName>hps_subsys</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>hps_subsys</fileSetName>
<fileSetFixedName>hps_subsys</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
logicalView
Logical view
hps_subsys/hps_subsys.qsys
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
System Verilog Interface definition
transformParameters
Transform Parameters
<transformParameterDescriptorDefinitionList/>
Altera Corporation
subsys_periph
altera_generic_component
1.0
bspCpu
BSP CPU
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>button_pio_external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>button_pio_external_connection_export</name>
<role>export</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>button_pio_irq</name>
<type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
<name>button_pio_irq_irq</name>
<role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.dts.irq.tx_type</key>
<value>RISING_EDGE</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
<value>subsys_periph.pb_cpu_0_s0</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bridgedReceiverOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToReceiver</key>
</entry>
<entry>
<key>irqScheme</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>dipsw_pio_external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>dipsw_pio_external_connection_export</name>
<role>export</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>dipsw_pio_irq</name>
<type>interrupt</type>
<isStart>false</isStart>
<ports>
<port>
<name>dipsw_pio_irq_irq</name>
<role>irq</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.dts.irq.tx_type</key>
<value>RISING_EDGE</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedAddressablePoint</key>
<value>subsys_periph.pb_cpu_0_s0</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bridgedReceiverOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToReceiver</key>
</entry>
<entry>
<key>irqScheme</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>led_pio_external_connection</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>led_pio_external_connection_in_port</name>
<role>in_port</role>
<direction>Input</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>led_pio_external_connection_out_port</name>
<role>out_port</role>
<direction>Output</direction>
<width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>pb_cpu_0_s0</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
<name>pb_cpu_0_s0_waitrequest</name>
<role>waitrequest</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_readdata</name>
<role>readdata</role>
<direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_readdatavalid</name>
<role>readdatavalid</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_burstcount</name>
<role>burstcount</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_writedata</name>
<role>writedata</role>
<direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_address</name>
<role>address</role>
<direction>Input</direction>
<width>17</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_write</name>
<role>write</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_read</name>
<role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_byteenable</name>
<role>byteenable</role>
<direction>Input</direction>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
<terminationValue>0</terminationValue>
</port>
<port>
<name>pb_cpu_0_s0_debugaccess</name>
<role>debugaccess</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap>
<entry>
<key>embeddedsw.configuration.isFlash</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isMemoryDevice</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isNonVolatileStorage</key>
<value>0</value>
</entry>
<entry>
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
<value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
<value>0</value>
</entry>
<entry>
<key>addressSpan</key>
<value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
<value>SYMBOLS</value>
</entry>
<entry>
<key>alwaysBurstMaxBurst</key>
<value>false</value>
</entry>
<entry>
<key>associatedClock</key>
<value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
<value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
<value>8</value>
</entry>
<entry>
<key>bridgedAddressOffset</key>
<value>0</value>
</entry>
<entry>
<key>bridgesToMaster</key>
</entry>
<entry>
<key>burstOnBurstBoundariesOnly</key>
<value>false</value>
</entry>
<entry>
<key>burstcountUnits</key>
<value>WORDS</value>
</entry>
<entry>
<key>constantBurstBehavior</key>
<value>false</value>
</entry>
<entry>
<key>explicitAddressSpan</key>
<value>0</value>
</entry>
<entry>
<key>holdTime</key>
<value>0</value>
</entry>
<entry>
<key>interleaveBursts</key>
<value>false</value>
</entry>
<entry>
<key>isBigEndian</key>
<value>false</value>
</entry>
<entry>
<key>isFlash</key>
<value>false</value>
</entry>
<entry>
<key>isMemoryDevice</key>
<value>false</value>
</entry>
<entry>
<key>isNonVolatileStorage</key>
<value>false</value>
</entry>
<entry>
<key>linewrapBursts</key>
<value>false</value>
</entry>
<entry>
<key>maximumPendingReadTransactions</key>
<value>1</value>
</entry>
<entry>
<key>maximumPendingWriteTransactions</key>
<value>0</value>
</entry>
<entry>
<key>minimumReadLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumResponseLatency</key>
<value>1</value>
</entry>
<entry>
<key>minimumUninterruptedRunLength</key>
<value>1</value>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
<entry>
<key>printableDevice</key>
<value>false</value>
</entry>
<entry>
<key>readLatency</key>
<value>0</value>
</entry>
<entry>
<key>readWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>readWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>registerIncomingSignals</key>
<value>false</value>
</entry>
<entry>
<key>registerOutgoingSignals</key>
<value>false</value>
</entry>
<entry>
<key>setupTime</key>
<value>0</value>
</entry>
<entry>
<key>timingUnits</key>
<value>Cycles</value>
</entry>
<entry>
<key>transparentBridge</key>
<value>false</value>
</entry>
<entry>
<key>waitrequestAllowance</key>
<value>0</value>
</entry>
<entry>
<key>waitrequestTimeout</key>
<value>1024</value>
</entry>
<entry>
<key>wellBehavedWaitrequest</key>
<value>false</value>
</entry>
<entry>
<key>writeLatency</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitStates</key>
<value>0</value>
</entry>
<entry>
<key>writeWaitTime</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureGuid</key>
<value>0</value>
</entry>
<entry>
<key>dfhGroupId</key>
<value>0</value>
</entry>
<entry>
<key>dfhParameterId</key>
</entry>
<entry>
<key>dfhParameterName</key>
</entry>
<entry>
<key>dfhParameterVersion</key>
</entry>
<entry>
<key>dfhParameterData</key>
</entry>
<entry>
<key>dfhParameterDataLength</key>
</entry>
<entry>
<key>dfhFeatureMajorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureMinorVersion</key>
<value>0</value>
</entry>
<entry>
<key>dfhFeatureId</key>
<value>35</value>
</entry>
<entry>
<key>dfhFeatureType</key>
<value>3</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
<name>clk_clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>clockRate</key>
<value>0</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>false</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>reset</name>
<type>reset</type>
<isStart>false</isStart>
<ports>
<port>
<name>reset_reset_n</name>
<role>reset_n</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>synchronousEdges</key>
<value>NONE</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>peripheral_subsys</className>
<displayName>peripheral_subsys</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue>default</parameterDefaultValue>
<parameterName>AUTO_BOARD</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>BOARD</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_CLK_CLOCK_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_CLK_CLOCK_RATE</parameterName>
<parameterType>java.lang.Long</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>CLOCK_RATE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>-1</parameterDefaultValue>
<parameterName>AUTO_CLK_RESET_DOMAIN</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfoArgs>clk</systemInfoArgs>
<systemInfotype>RESET_DOMAIN</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>A5ED065BB32AE6SR0</parameterDefaultValue>
<parameterName>AUTO_DEVICE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>Agilex 5</parameterDefaultValue>
<parameterName>AUTO_DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>6</parameterDefaultValue>
<parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue>0</parameterDefaultValue>
<parameterName>AUTO_GENERATION_ID</parameterName>
<parameterType>java.lang.Integer</parameterType>
<systemInfotype>GENERATION_ID</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>AUTO_PB_CPU_0_S0_CPU_INFO_ID</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfoArgs>pb_cpu_0_s0</systemInfoArgs>
<systemInfotype>CPU_INFO_ID</systemInfotype>
</descriptor>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>AUTO_UNIQUE_ID</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>UNIQUE_ID</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos>
<entry>
<key>clk</key>
<value>
<connectionPointName>clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_DOMAIN</key>
<value>1</value>
</entry>
<entry>
<key>CLOCK_RATE</key>
<value>100000000</value>
</entry>
<entry>
<key>RESET_DOMAIN</key>
<value>1</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>pb_cpu_0_s0</key>
<value>
<connectionPointName>pb_cpu_0_s0</connectionPointName>
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos>
<entry>
<key>CPU_INFO_ID</key>
<value></value>
</entry>
</consumedSystemInfos>
</value>
</entry>
</connPtSystemInfos>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>peripheral_subsys</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>peripheral_subsys</fileSetName>
<fileSetFixedName>peripheral_subsys</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>peripheral_subsys</fileSetName>
<fileSetFixedName>peripheral_subsys</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>peripheral_subsys</fileSetName>
<fileSetFixedName>peripheral_subsys</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>peripheral_subsys</fileSetName>
<fileSetFixedName>peripheral_subsys</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>peripheral_subsys</fileSetName>
<fileSetFixedName>peripheral_subsys</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
logicalView
Logical view
peripheral_subsys/peripheral_subsys.qsys
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
System Verilog Interface definition
transformParameters
Transform Parameters
<transformParameterDescriptorDefinitionList/>
Altera Corporation
user_rst_clkgate_0
altera_generic_component
1.0
bspCpu
BSP CPU
false
componentDefinition
Component definition
<componentDefinition>
<boundary>
<interfaces>
<interface>
<name>ninit_done</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>ninit_done</name>
<role>ninit_done</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundary>
<originalModuleInfo>
<className>intel_user_rst_clkgate</className>
<version>1.0.1</version>
<displayName>Reset Release IP</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
<descriptor>
<parameterDefaultValue></parameterDefaultValue>
<parameterName>DEVICE_FAMILY</parameterName>
<parameterType>java.lang.String</parameterType>
<systemInfotype>DEVICE_FAMILY</systemInfotype>
</descriptor>
</descriptors>
</systemInfoParameterDescriptors>
<systemInfos>
<connPtSystemInfos/>
</systemInfos>
</componentDefinition>
cpuHashInfo
CPU Hash Info
<cpuHashInfoDefinition>
<cpuHashInfoMap/>
</cpuHashInfoDefinition>
cpuInfo
Cpu Info
defaultBoundary
Default boundary
<boundaryDefinition>
<interfaces>
<interface>
<name>ninit_done</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
<name>ninit_done</name>
<role>ninit_done</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
<terminationValue>0</terminationValue>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedClock</key>
</entry>
<entry>
<key>associatedReset</key>
</entry>
<entry>
<key>prSafe</key>
<value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
</interfaces>
</boundaryDefinition>
generationInfoDefinition
Generation Behavior
<generationInfoDefinition>
<hdlLibraryName>user_rst_clkgate_0</hdlLibraryName>
<fileSets>
<fileSet>
<fileSetName>user_rst_clkgate_0</fileSetName>
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>user_rst_clkgate_0</fileSetName>
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>user_rst_clkgate_0</fileSetName>
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>user_rst_clkgate_0</fileSetName>
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
<fileSetKind>CDC</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
<fileSet>
<fileSetName>user_rst_clkgate_0</fileSetName>
<fileSetFixedName>user_rst_clkgate_0</fileSetFixedName>
<fileSetKind>CDC_VHDL</fileSetKind>
<fileSetFiles/>
<fileSetFileChangeDefs/>
</fileSet>
</fileSets>
</generationInfoDefinition>
hdlParameters
HDL Parameters
<hdlParameterDescriptorDefinitionList/>
hlsFile
HLS file
liveModuleName
Live Module Name
intel_user_rst_clkgate_inst
logicalView
Logical view
ip/qsys_top/user_rst_clkgate_0.ip
moduleAssignmentDefinition
Module Assignments
<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>
svInterfaceDefinition
System Verilog Interface definition
transformParameters
Transform Parameters
<transformParameterDescriptorDefinitionList/>
Intel Corporation
addressMap
addressMap
1.0
subsys_hps.hps2fpga
subsys_periph.pb_cpu_0_s0
subsys_hps.lwhps2fpga
0x0000_0000
subsys_hps.lwhps2fpga
subsys_periph.pb_cpu_0_s0
0x0000_0000
0x0002_0000
false
false