Altera user_rst_clkgate_0 intel_user_rst_clkgate_inst 1.0.1 ninit_done ninit_done ninit_done associatedClock associatedClock associatedReset associatedReset prSafe Partial Reconfiguration Safe false QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH intel_user_rst_clkgate QUARTUS_SYNTH ninit_done out STD_LOGIC QUARTUS_SYNTH Altera user_rst_clkgate_0 intel_user_rst_clkgate 1.0.1 outputType Type of reset output port Conduit Interface DEVICE_FAMILY Device family Agilex 5 board Board default device Device A5EB013BB23BE4SCS deviceFamily Device family Agilex 5 deviceSpeedGrade Device Speed Grade 6 generationId Generation Id 0 bonusData bonusData bonusData { element $system { datum _originalDeviceFamily { value = "Agilex 5"; type = "String"; } } element intel_user_rst_clkgate_inst { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog false lockedInterfaceDefinition lockedInterfaceDefinition <boundaryDefinition> <interfaces> <interface> <name>ninit_done</name> <type>conduit</type> <isStart>false</isStart> <ports> <port> <name>ninit_done</name> <role>ninit_done</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedReset</key> </entry> <entry> <key>prSafe</key> <value>false</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> dflBitArray dflBitArray cpuInfo cpuInfo false false