Intel Corporation rst_in altera_reset_bridge_inst 19.2.0 in_reset reset_n in_reset_n associatedClock Associated clock synchronousEdges Synchronous edges NONE out_reset reset_n out_reset_n associatedClock Associated clock associatedDirectReset Associated direct reset in_reset associatedResetSinks Associated reset sinks in_reset synchronousEdges Synchronous edges NONE QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_reset_bridge QUARTUS_SYNTH in_reset_n in STD_LOGIC QUARTUS_SYNTH out_reset_n out STD_LOGIC QUARTUS_SYNTH Intel Corporation rst_in altera_reset_bridge 19.2.0 ACTIVE_LOW_RESET Active low reset 1 SYNCHRONOUS_EDGES Input Synchronous edges none NUM_RESET_OUTPUTS Number of reset outputs 1 USE_RESET_REQUEST Use reset request signal 0 SYNC_RESET Use synchronous resets 0 AUTO_CLK_CLOCK_RATE Auto CLOCK_RATE -1 board Board default device Device A5EB013BB23BE4SCS deviceFamily Device family Agilex 5 deviceSpeedGrade Device Speed Grade 6 generationId Generation Id 0 bonusData bonusData bonusData { element $system { datum _originalDeviceFamily { value = "Agilex 5"; type = "String"; } } element altera_reset_bridge_inst { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog false lockedInterfaceDefinition lockedInterfaceDefinition <boundaryDefinition> <interfaces> <interface> <name>in_reset</name> <type>reset</type> <isStart>false</isStart> <ports> <port> <name>in_reset_n</name> <role>reset_n</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>out_reset</name> <type>reset</type> <isStart>true</isStart> <ports> <port> <name>out_reset_n</name> <role>reset_n</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedClock</key> </entry> <entry> <key>associatedDirectReset</key> <value>in_reset</value> </entry> <entry> <key>associatedResetSinks</key> <value>in_reset</value> </entry> <entry> <key>synchronousEdges</key> <value>NONE</value> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos/> </systemInfosDefinition> dflBitArray dflBitArray cpuInfo cpuInfo false false