Intel Corporation clk_100 altera_clock_bridge_inst 19.2.0 in_clk clk in_clk clockRate Clock rate 0 externallyDriven Externally driven false ptfSchematicName PTF schematic name out_clk clk out_clk associatedDirectClock Associated direct clock in_clk clockRate Clock rate 100000000 clockRateKnown Clock rate known true externallyDriven Externally driven false ptfSchematicName PTF schematic name QUARTUS_SYNTH :quartus.altera.com: QUARTUS_SYNTH QUARTUS_SYNTH altera_clock_bridge QUARTUS_SYNTH in_clk in STD_LOGIC QUARTUS_SYNTH out_clk out STD_LOGIC QUARTUS_SYNTH Intel Corporation clk_100 altera_clock_bridge 19.2.0 DERIVED_CLOCK_RATE Derived clock rate 0 EXPLICIT_CLOCK_RATE Explicit clock rate 100000000 NUM_CLOCK_OUTPUTS Number of Clock Outputs 1 board Board default device Device A5EB013BB23BE4SCS deviceFamily Device family Agilex 5 deviceSpeedGrade Device Speed Grade 6 generationId Generation Id 0 bonusData bonusData bonusData { element $system { datum _originalDeviceFamily { value = "Agilex 5"; type = "String"; } } element altera_clock_bridge_inst { datum _sortIndex { value = "0"; type = "int"; } } } hideFromIPCatalog Hide from IP Catalog false lockedInterfaceDefinition lockedInterfaceDefinition <boundaryDefinition> <interfaces> <interface> <name>in_clk</name> <type>clock</type> <isStart>false</isStart> <ports> <port> <name>in_clk</name> <role>clk</role> <direction>Input</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>clockRate</key> <value>0</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> <interface> <name>out_clk</name> <type>clock</type> <isStart>true</isStart> <ports> <port> <name>out_clk</name> <role>clk</role> <direction>Output</direction> <width>1</width> <lowerBound>0</lowerBound> <vhdlType>STD_LOGIC</vhdlType> <terminationValue>0</terminationValue> </port> </ports> <assignments> <assignmentValueMap/> </assignments> <parameters> <parameterValueMap> <entry> <key>associatedDirectClock</key> <value>in_clk</value> </entry> <entry> <key>clockRate</key> <value>100000000</value> </entry> <entry> <key>clockRateKnown</key> <value>true</value> </entry> <entry> <key>externallyDriven</key> <value>false</value> </entry> <entry> <key>ptfSchematicName</key> </entry> </parameterValueMap> </parameters> </interface> </interfaces> </boundaryDefinition> systemInfos systemInfos <systemInfosDefinition> <connPtSystemInfos> <entry> <key>in_clk</key> <value> <connectionPointName>in_clk</connectionPointName> <suppliedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>0</value> </entry> </suppliedSystemInfos> <consumedSystemInfos/> </value> </entry> <entry> <key>out_clk</key> <value> <connectionPointName>out_clk</connectionPointName> <suppliedSystemInfos/> <consumedSystemInfos> <entry> <key>CLOCK_RATE</key> <value>100000000</value> </entry> </consumedSystemInfos> </value> </entry> </connPtSystemInfos> </systemInfosDefinition> dflBitArray dflBitArray cpuInfo cpuInfo false false