# retroDE_ps2 simulation driver
#
# Targets:
#   make lint                  run verilator --lint-only across all RTL (strict)
#   make tb_ee_fetch           build + run tb_ee_fetch_stub (iverilog)
#   make tb_gs                 build + run tb_gs_stub
#   make tb_intc               build + run tb_intc_stub
#   make tb_platform_video     build + run tb_platform_video_stub (Milestone A)
#   make tb_bgcolor_via_dma    build + run tb_bgcolor_via_dma (Milestone A+)
#   make tb_sif_mailbox        build + run tb_sif_mailbox_stub
#   make tb_sif_command_echo   build + run tb_sif_command_echo (EE↔peer)
#   make tb_sif_command_echo_rearm  build + run re-armable multi-command TB
#   make tb_sif_negative_path  build + run stall/malformed-lifecycle TB
#   make tb_sif_dma_smoke      build + run first SIF DMA receive test (ch5)
#   make tb_sif_dma_mid_stall  build + run mid-transfer backpressure test
#   make tb_sif_dma_overflow   build + run full-stop backpressure test
#   make tb_sif_combined_ctrl_data  build + run first combined ctrl+data SIF handshake
#   make tb_iop_ram            build + run first IOP-side primitive test
#   make tb_iop_memory_map     build + run IOP memory map decode test
#   make tb_iop_fetch_through_map  build + run IOP fetch → map → RAM integration
#   make tb_sif_iop_bridge_smoke   build + run SIF-to-IOP-RAM bridge write test
#   make tb_sif_iop_bridge_exec    build + run execution-visible bridge test
#   make tb_iop_to_sif_via_map     build + run IOP reaches SIF via real map
#   make tb_iop_dmac_via_map       build + run IOP DMAC ch9 through the real map
#   make tb_sif_ee_landing_via_dmac  build + run first reverse-direction SIF DMA
#   make tb_sif_iop_driven_combined  build + run IOP-driven combined ctrl+data handshake
#   make tb_ee_dmac_intc             build + run first EE DMAC completion → INTC flow
#   make tb_iop_dmac_intc            build + run IOP DMAC ch9 → IOP INTC through real map
#   make tb_iop_self_driven          build + run first self-driven IOP transaction
#   make tb_iop_autonomous_two_xfers build + run first autonomous multi-transaction script
#   make tb_iop_core_basic           build + run first real MIPS-decode IOP core run
#   make tb_iop_core_interrupts      build + run first exception-driven IOP program
#   make tb_iop_core_bootstrap       build + run first BIOS-sourced bootstrap (Phase 1)
#   make tb_iop_core_bootstrap_intc  build + run BIOS-sourced interrupt flow (Phase 2)
#   make tb_iop_core_bios_smoke      build + run strict-mode BIOS smoke (first-unsupported halt)
#   make tb_ee_core_basic            build + run first EE-side real-decode run
#   make tb_ee_core_memops           build + run EE CPU→RAM SW/LW round-trip
#   make tb_ee_core_dmac             build + run EE core programming DMAC ch2 via SW
#   make tb_ee_core_dmac_poll        build + run EE core polling CHCR + DONE_COUNT
#   make tb_ee_core_dmac_intc        build + run EE core DMAC-through-INTC exception flow
#   make tb_ee_core_bios_smoke       build + run EE strict-mode BIOS smoke (first-unsupported halt)
#   make tb_ee_core_bios_smoke BIOS=/path/to/bios.hex  # same TB, real BIOS image
#   make tb_ee_core_slti             build + run EE SLTI/SLTIU coverage (first real-BIOS-driven op growth)
#   make tb_ee_core_addi             build + run EE ADDI coverage (second real-BIOS-driven op growth)
#   make tb_ee_core_andi             build + run EE ANDI coverage (third real-BIOS-driven op growth)
#   make tb_ee_core_rtype_logic      build + run EE R-type AND/OR/XOR/NOR coverage (fourth growth)
#   make tb_ee_core_sb               build + run EE SB byte-store coverage (fifth growth)
#   make tb_ee_core_lb               build + run EE LB sign-extended byte-load (sixth growth)
#   make tb_ee_core_jal              build + run EE JAL jump-and-link (seventh growth)
#   make tb_ee_core_rtype_addu       build + run EE R-type ADDU/SUBU coverage (eighth growth)
#   make tb_ee_core_slt              build + run EE R-type SLT/SLTU coverage (ninth growth)
#   make tb_ee_core_lh               build + run EE LH sign-extended halfword load (tenth growth)
#   make tb_ee_core_lhu              build + run EE LHU zero-extended halfword load (tenth growth, paired)
#   make tb_ee_core_shift            build + run EE SLL/SRL/SRA shift family coverage (eleventh growth)
#   make tb_ee_core_sh               build + run EE SH halfword-store coverage (twelfth growth)
#   make tb_ee_core_jalr             build + run EE JALR register-indirect call + link (thirteenth growth)
#   make tb_ee_core_add_sub          build + run EE R-type ADD/SUB coverage (fourteenth growth; overflow-trap deferred)
#   make tb_ee_core_cop0_count       build + run EE COP0 Count coverage (first machine-state chapter)
#   make tb_ee_bootstrap_mmio        build + run EE bootstrap MMIO stub unit test (latched register file)
#   make tb_ee_biu_mmio              build + run EE BIU/cache-control stub unit test (0xFFFE_0xxx window)
#   make run                   run all fifty-three testbenches
#   make all_checks            lint + run (RTL + benches; the default gate)
#   make full_checks           all_checks + test_compare (widest regression)
#   make golden_nop            generate the NOP-sled golden trace
#   make compare_ee_fetch      diff RTL ee_fetch.trace vs. NOP-sled golden
#   make test_compare          run the comparator against all three documented
#                              exit-code paths (acceptance criteria 4/5/6 from
#                              sim/golden/trace_compare_spec.md)
#   make traces                show what's in sim/traces/rtl/
#   make clean                 remove build artifacts and traces
#
# Trace files are written to sim/traces/rtl/ (Make cds there before running
# each testbench so the trace_sink_stub FILENAME parameters resolve into
# that directory).

SIM_DIR       := $(CURDIR)
REPO_ROOT     := $(abspath $(SIM_DIR)/..)
# Ch245 — shared retroDE platform OSD lives in the sibling retroDE_splash
# repo, NOT inside this core. Sibling cores reference it the same way.
SPLASH_PLATFORM_RTL := $(abspath $(REPO_ROOT)/../retroDE_splash/rtl/platform)
BUILD_DIR     := $(SIM_DIR)/build
TRACE_DIR     := $(SIM_DIR)/traces/rtl
GOLD_TRC_DIR  := $(SIM_DIR)/traces/golden
GOLDEN_DIR    := $(SIM_DIR)/golden

RTL_ROOT      := $(REPO_ROOT)/rtl
TB_ROOT       := $(SIM_DIR)/tb

PYTHON        := python3

# ---------------------------------------------------------------------
# Ch147 — Top-wrapper fixture bake (top_psmct32_raster_demo).
# ---------------------------------------------------------------------
# The Ch146 hardware top reads two .mem fixtures via $readmemh:
#   bios.mem    — 1024 32-bit words (4 KiB BIOS BRAM, 18 active)
#   payload.mem — 256 128-bit qwords (4 KiB EE-RAM BRAM, 40 active)
# Both are produced deterministically by sim/data/top_psmct32_raster_demo/
# bake.py from the same procedural pattern Ch123 uses. Ch147 makes the
# bake first-class so the .mem files can't drift from the script:
#   `make top_psmct32_raster_demo_mem`        — re-runs the bake
#   `make top_psmct32_raster_demo_mem_check`  — verifies fixture sizes
#   tb_top_psmct32_raster_demo depends on top_psmct32_raster_demo_mem
#   so a stale fixture is impossible.
TOP_PSMCT32_DEMO_DATA_DIR := $(SIM_DIR)/data/top_psmct32_raster_demo
TOP_PSMCT32_DEMO_BAKE_PY  := $(TOP_PSMCT32_DEMO_DATA_DIR)/bake.py
TOP_PSMCT32_DEMO_BIOS     := $(TOP_PSMCT32_DEMO_DATA_DIR)/bios.mem
TOP_PSMCT32_DEMO_PAYLOAD  := $(TOP_PSMCT32_DEMO_DATA_DIR)/payload.mem

# Both .mem files share a single recipe — they're produced atomically
# by one bake.py invocation. Make `bios.mem` the canonical target;
# `payload.mem` rebuilds whenever bios.mem does via the same recipe.
$(TOP_PSMCT32_DEMO_BIOS) $(TOP_PSMCT32_DEMO_PAYLOAD) &: $(TOP_PSMCT32_DEMO_BAKE_PY)
	@echo "=== bake top_psmct32_raster_demo .mem fixtures ==="
	$(PYTHON) $(TOP_PSMCT32_DEMO_BAKE_PY)

top_psmct32_raster_demo_mem: $(TOP_PSMCT32_DEMO_BIOS) $(TOP_PSMCT32_DEMO_PAYLOAD)

# Ch357 persistent-Z signoff fixture. This is the canonical ZSCHED emit mode:
# integerized XY geometry in both the feeder data and the reference maps,
# e2 PSCALE pinned at the measured best global value, and authentic Z.
SH3_ZSCHED_FIXTURE_PY    := $(REPO_ROOT)/tools/gs_make_sh3_scheduler_fixture.py
SH3_ZSCHED_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsched_params.vh
SH3_ZSCHED_FIXTURE_FLAGS := --draw-list 8634,12757,145742 --authz --tag zsched \
                            --pscale auto,auto,384 --xy-quant round,round,round --ref-xy-quant --emit
SH3_ZSCHED_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsched_board_fb.mem
SH3_ZSCHED_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsched_zint_fb.mem

$(SH3_ZSCHED_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zsched persistent-Z integer-XY fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZSCHED_FIXTURE_FLAGS)

sh3_zsched_fixture: $(SH3_ZSCHED_FIXTURE)

# Ch358 — the SAME strong-reject persistent-Z scene at NATIVE 640x480 (authentic screen coords, no union
# translation). Identical draw list / pscale / xy-quant spec as the zsched signoff fixture; only the FB
# geometry differs (--fb640). Integer-XY reference is the signoff default for this tag too.
SH3_ZS640_FIXTURE        := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640_params.vh
SH3_ZS640_FIXTURE_FLAGS  := --draw-list 8634,12757,145742 --authz --fb640 --tag zs640 \
                            --pscale auto,auto,384 --xy-quant round,round,round --ref-xy-quant --emit
SH3_ZS640_BOARD_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640_board_fb.mem
SH3_ZS640_ZINT_FB        := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640_zint_fb.mem

$(SH3_ZS640_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640 native-640x480 persistent-Z integer-XY fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640_FIXTURE_FLAGS)

sh3_zs640_fixture: $(SH3_ZS640_FIXTURE)

# Ch359 (Codex: zs640c6) — SIX shared-texture draws (PSMT8 tbp=8192/cbp=13888, authentic GEQUAL/ZMSK=0 PSMZ16S)
# grouped into TWO ordered 204-triangle feeder lists at native 640x480. Epoch 1 sets an EXPLICIT reuse flag: the
# texture cache stays RESIDENT (one fill total). Same integer-XY signoff contract; fail-closed gates in the emit.
SH3_ZS640C6_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c6_params.vh
SH3_ZS640C6_FIXTURE_FLAGS := --draw-list 119471,119684,119897,120110,120323,120536 --group-size 3 \
                             --authz --fb640 --tag zs640c6 --pscale auto,auto --xy-quant round,round \
                             --ref-xy-quant --emit
SH3_ZS640C6_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c6_board_fb.mem
SH3_ZS640C6_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c6_zint_fb.mem
SH3_ZSRT3_BOARD_FB        := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrt3_board_fb.mem
SH3_ZSRT3_ZINT_FB         := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrt3_zint_fb.mem
SH3_ZSRT24_BOARD_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrt24_board_fb.mem
SH3_ZSRT24_ZINT_FB        := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrt24_zint_fb.mem
SH3_ZSRT24_REQ_DEPTH ?= 4096
SH3_ZSRT24_TRACE ?= 0
SH3_ZSRTB24_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrtb24_board_fb.mem
SH3_ZSRTB24_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrtb24_zint_fb.mem
SH3_ZSRTB24_REQ_DEPTH ?= 4096
SH3_ZSRTB24_START_EPOCH ?=
SH3_ZSRTM28_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrtm28_board_fb.mem
SH3_ZSRTM28_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrtm28_zint_fb.mem
SH3_ZSRTM28_REQ_DEPTH ?= 4096
SH3_ZSRTC24_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrtc24_board_fb.mem
SH3_ZSRTC24_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrtc24_zint_fb.mem
SH3_ZSRTC24_REQ_DEPTH ?= 4096
SH3_ZSRTE3_BOARD_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte3_board_fb.mem
SH3_ZSRTE3_ZINT_FB        := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte3_zint_fb.mem
SH3_ZSRTE3_REQ_DEPTH ?= 4096
SH3_ZSRTE6_REQ_DEPTH ?= 4096
SH3_ZSRTE8_BOARD_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte8_board_fb.mem
SH3_ZSRTE8_ZINT_FB        := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte8_zint_fb.mem
SH3_ZSRTE8_REQ_DEPTH ?= 4096
SH3_ZSRTE11_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte11_board_fb.mem
SH3_ZSRTE11_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte11_zint_fb.mem
SH3_ZSRTE11_REQ_DEPTH ?= 4096
SH3_ZSRTE17_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte17_board_fb.mem
SH3_ZSRTE17_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte17_zint_fb.mem
SH3_ZSRTE17_REQ_DEPTH ?= 4096
SH3_ZSRTE18_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte18_board_fb.mem
SH3_ZSRTE18_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte18_zint_fb.mem
SH3_ZSRTE18_REQ_DEPTH ?= 4096
SH3_ZSRTE19_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte19_board_fb.mem
SH3_ZSRTE19_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zsrte19_zint_fb.mem
SH3_ZSRTE19_REQ_DEPTH ?= 4096
SH3_ZSRTE22_REQ_DEPTH ?= 4096
SH3_ZSRTE25_REQ_DEPTH ?= 4096
SH3_ZSRTE28_REQ_DEPTH ?= 4096
SH3_ZSRTE31_REQ_DEPTH ?= 4096
SH3_ZSRTE34_REQ_DEPTH ?= 4096
SH3_ZSRTE43_REQ_DEPTH ?= 4096
SH3_ZSRTE45_REQ_DEPTH ?= 4096
SH3_ZSRTF3E18_REQ_DEPTH ?= 4096
SH3_ZSRTF3E30_REQ_DEPTH ?= 4096
SH3_ZSRTF3C30_REQ_DEPTH ?= 4096
SH3_ZSRTF3C34_REQ_DEPTH ?= 4096
SH3_ZSRTF3C41_REQ_DEPTH ?= 4096
SH3_ZSRTF3C49_REQ_DEPTH ?= 4096
SH3_ZSRTF3C57_REQ_DEPTH ?= 4096
SH3_ZSRTF3C57X_REQ_DEPTH ?= 4096
# Ch394 — matching-capture (224139) opaque foundation.  Three two-draw epochs
# share the authentic PSMT8 texture/CLUT and retain native 640x480 coordinates.
SH3_ZSRT139O6_REQ_DEPTH ?= 4096
# Ch395 — wider 224139 opaque A1: left panel + centre + bench, in five
# staging-safe epochs (three texture fills, then two resident-texture reuses).
SH3_ZSRT139A1_REQ_DEPTH ?= 4096
# Ch396 — wider 224139 opaque A2: adds the in-order right-side bench band.
SH3_ZSRT139A2_REQ_DEPTH ?= 4096

$(SH3_ZS640C6_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640c6 shared-texture 2x204-tri persistent-Z fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640C6_FIXTURE_FLAGS)

sh3_zs640c6_fixture: $(SH3_ZS640C6_FIXTURE)

# Ch360 (zs640c12) — twelve shared-texture draws in FOUR existing-size 204-triangle epochs. This deliberately
# scales draw count and residency reuse without changing feeder-list capacity, RTL, clocks, or the board RBF.
SH3_ZS640C12_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c12_params.vh
SH3_ZS640C12_FIXTURE_FLAGS := --draw-list 119471,119684,119897,120110,120323,120536,120749,120962,121175,121388,121601,121814 --group-size 3 \
                              --authz --fb640 --tag zs640c12 --pscale 1024,1024,1024,1024 --xy-quant round,round,round,round \
                              --ref-xy-quant --emit
SH3_ZS640C12_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c12_board_fb.mem
SH3_ZS640C12_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c12_zint_fb.mem

$(SH3_ZS640C12_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640c12 shared-texture 4x204-tri persistent-Z fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640C12_FIXTURE_FLAGS)

sh3_zs640c12_fixture: $(SH3_ZS640C12_FIXTURE)

# Ch361 (zs640c18) -- eighteen compatible SH3 draws in six existing-size 204-triangle epochs. This extends only
# draw-count and cache residency; geometry, depth mode, clocks, and the board core remain those proven by Ch360.
SH3_ZS640C18_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c18_params.vh
SH3_ZS640C18_FIXTURE_FLAGS := --draw-list 119471,119684,119897,120110,120323,120536,120749,120962,121175,121388,121601,121814,122027,122240,124082,129389,129602,129815 --group-size 3 \
                              --authz --fb640 --tag zs640c18 --pscale 1024,1024,1024,1024,1024,1024 --xy-quant round,round,round,round,round,round \
                              --ref-xy-quant --emit
SH3_ZS640C18_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c18_zint_fb.mem

$(SH3_ZS640C18_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640c18 shared-texture 6x204-tri persistent-Z fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640C18_FIXTURE_FLAGS)

sh3_zs640c18_fixture: $(SH3_ZS640C18_FIXTURE)

# Ch362 (zs640c24) -- twenty-four authentic draws in eight existing-size epochs. The final candidate skips idx131306,
# whose authentic Y extent exceeds the native framebuffer; every retained draw is in-bounds and shares the C18 state.
SH3_ZS640C24_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c24_params.vh
SH3_ZS640C24_FIXTURE_FLAGS := --draw-list 119471,119684,119897,120110,120323,120536,120749,120962,121175,121388,121601,121814,122027,122240,124082,129389,129602,129815,130241,130454,130667,130880,131093,132158 --group-size 3 \
                              --authz --fb640 --tag zs640c24 --pscale 1024,1024,1024,1024,1024,1024,1024,1024 --xy-quant round,round,round,round,round,round,round,round \
                              --ref-xy-quant --emit

$(SH3_ZS640C24_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640c24 shared-texture 8x204-tri persistent-Z fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640C24_FIXTURE_FLAGS)

sh3_zs640c24_fixture: $(SH3_ZS640C24_FIXTURE)

# Ch363 (zs640mt5) -- five ordered authentic draws with distinct texture/CLUT bindings. This is the first
# post-C24 content rung that exercises cache rebinds rather than further shared-texture residency.
SH3_ZS640MT5_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640mt5_params.vh
SH3_ZS640MT5_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640mt5_board_fb.mem
SH3_ZS640MT5_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640mt5_zint_fb.mem
SH3_ZS640MT5_FIXTURE_FLAGS := --draw-list 5328,11671,77112,89164,119471 \
                              --authz --fb640 --tag zs640mt5 --pscale 1024,1024,1024,1024,1024 --xy-quant round,round,round,round,round \
                              --ref-xy-quant --emit

$(SH3_ZS640MT5_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640mt5 five-texture persistent-Z fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640MT5_FIXTURE_FLAGS)

sh3_zs640mt5_fixture: $(SH3_ZS640MT5_FIXTURE)

# Ch364 (zs640m28) -- ordered mixed-residency scene: four distinct early texture epochs followed by the 24-draw
# C24 cluster in eight 204-triangle lists. This proves texture rebinds followed by bounded same-texture residency.
SH3_ZS640M28_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640m28_params.vh
SH3_ZS640M28_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640m28_board_fb.mem
SH3_ZS640M28_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640m28_zint_fb.mem
SH3_ZS640M28_FIXTURE_FLAGS := --draw-list 5328,11671,77112,89164,119471,119684,119897,120110,120323,120536,120749,120962,121175,121388,121601,121814,122027,122240,124082,129389,129602,129815,130241,130454,130667,130880,131093,132158 \
                              --group-sizes 1,1,1,1,3,3,3,3,3,3,3,3 --authz --fb640 --tag zs640m28 --chapter Ch364 \
                              --pscale 1024,1024,1024,1024,1024,1024,1024,1024,1024,1024,1024,1024 \
                              --xy-quant round,round,round,round,round,round,round,round,round,round,round,round --ref-xy-quant --emit

$(SH3_ZS640M28_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640m28 mixed-residency persistent-Z fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640M28_FIXTURE_FLAGS)

sh3_zs640m28_fixture: $(SH3_ZS640M28_FIXTURE)

# Ch365 frame B -- adjacent-capture, native 640x480 texture-cluster state. Its CLUT is relocated after Ch364's
# five preloaded palettes so a future two-frame bootlet can contain both frames without aliasing.
SH3_ZS640B24_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640b24_params.vh
SH3_ZS640B24_BOARD_FB      := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640motion_b_board_fb.mem
SH3_ZS640B24_ZINT_FB       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640b24_zint_fb.mem
SH3_ZS640B24_FIXTURE_FLAGS := captures/gs/silenthill3/Silent\ Hill\ 3_SLUS-20622_20260624224121.gs.zst \
                              --draw-list 114590,114803,115016,115229,115442,115655,115925,116138,117386,117599,117812,118451,118982,119195,123656,126542,126755,126968,127394,127607,127820,128033,128246,128459 \
                              --group-size 3 --authz --fb640 --tag zs640b24 --chapter Ch365 --cbp-base 500 \
                              --pscale 1024,1024,1024,1024,1024,1024,1024,1024 \
                              --xy-quant round,round,round,round,round,round,round,round --ref-xy-quant --emit

$(SH3_ZS640B24_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640b24 adjacent-capture frame-B fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640B24_FIXTURE_FLAGS)

sh3_zs640b24_fixture: $(SH3_ZS640B24_FIXTURE)

# Ch366 frame C -- the next adjacent capture reuses the eight-epoch, 24-draw shape but has distinct texture/CLUT
# bytes despite its matching lightweight texture sum. It receives CBP 504 after the A/B union's six palette banks.
SH3_ZS640C24C_FIXTURE       := $(TOP_PSMCT32_DEMO_DATA_DIR)/sh3_zs640c24c_params.vh
SH3_ZS640C24C_FIXTURE_FLAGS := captures/gs/silenthill3/Silent\ Hill\ 3_SLUS-20622_20260624224139.gs.zst \
                               --draw-list 119471,119684,119897,120110,120323,120536,120749,120962,121175,121388,121601,121814,122027,122240,124082,129389,129602,129815,130241,130454,130667,130880,131093,132158 \
                               --group-size 3 --authz --fb640 --tag zs640c24c --chapter Ch366 --cbp-base 504 \
                               --pscale 1024,1024,1024,1024,1024,1024,1024,1024 \
                               --xy-quant round,round,round,round,round,round,round,round --ref-xy-quant --emit

$(SH3_ZS640C24C_FIXTURE): $(SH3_ZSCHED_FIXTURE_PY)
	@echo "=== emit sh3_zs640c24c adjacent-capture frame-C fixtures ==="
	$(PYTHON) $(SH3_ZSCHED_FIXTURE_PY) $(SH3_ZS640C24C_FIXTURE_FLAGS)

sh3_zs640c24c_fixture: $(SH3_ZS640C24C_FIXTURE)

# Ch365 motion bootlet -- union of the already-generated frame-A and frame-B palette preload packets. The six
# relocated palettes occupy CBPs 480,484,488,492,496,500 and fit in the 512-qword production boot payload.
SH3_ZS640MOTION_BOOTLET_PY := $(REPO_ROOT)/tools/gs_merge_scheduler_bootlets.py
SH3_ZS640MOTION_BOOTLET    := $(TOP_PSMCT32_DEMO_DATA_DIR)/payload_sh3_zs640motionab.mem

$(SH3_ZS640MOTION_BOOTLET): $(SH3_ZS640M28_FIXTURE) $(SH3_ZS640B24_FIXTURE) $(SH3_ZS640MOTION_BOOTLET_PY)
	@echo "=== emit sh3_zs640motionab union bootlet ==="
	$(PYTHON) $(SH3_ZS640MOTION_BOOTLET_PY) zs640motionab zs640m28 zs640b24

sh3_zs640motion_bootlet: $(SH3_ZS640MOTION_BOOTLET)

SH3_ZS640MOTIONABC_BOOTLET := $(TOP_PSMCT32_DEMO_DATA_DIR)/payload_sh3_zs640motionabc.mem

$(SH3_ZS640MOTIONABC_BOOTLET): $(SH3_ZS640M28_FIXTURE) $(SH3_ZS640B24_FIXTURE) $(SH3_ZS640C24C_FIXTURE) $(SH3_ZS640MOTION_BOOTLET_PY)
	@echo "=== emit sh3_zs640motionabc union bootlet ==="
	$(PYTHON) $(SH3_ZS640MOTION_BOOTLET_PY) zs640motionabc zs640m28 zs640b24 zs640c24c

sh3_zs640motionabc_bootlet: $(SH3_ZS640MOTIONABC_BOOTLET)

# Size check — bios.mem must be 1024 lines of payload (header lines
# excluded), payload.mem must be 256 lines of payload. We strip
# blanks + `// ...` comment-only lines and count the rest.
top_psmct32_raster_demo_mem_check: top_psmct32_raster_demo_mem
	@echo "=== check top_psmct32_raster_demo fixture sizes ==="
	@bios_lines=$$(grep -cvE '^\s*(//.*)?$$' $(TOP_PSMCT32_DEMO_BIOS)); \
	 if [ $$bios_lines -ne 1024 ]; then \
	     echo "FAIL: bios.mem has $$bios_lines payload lines, expected 1024"; \
	     exit 1; \
	 fi; \
	 echo "  bios.mem    : $$bios_lines payload lines (expected 1024)  OK"
	@payload_lines=$$(grep -cvE '^\s*(//.*)?$$' $(TOP_PSMCT32_DEMO_PAYLOAD)); \
	 if [ $$payload_lines -ne 256 ]; then \
	     echo "FAIL: payload.mem has $$payload_lines payload lines, expected 256"; \
	     exit 1; \
	 fi; \
	 echo "  payload.mem : $$payload_lines payload lines (expected 256)   OK"

# ---------------------------------------------------------------------
# Ch148 — synthesis scaffold validator (DE25-Nano).
# ---------------------------------------------------------------------
# Verifies that every path listed in
# synth/de25_nano/top_psmct32_raster_demo/files.f resolves to a real
# file relative to the repo root, AND that the two .mem fixtures
# exist. Strips comments / blank lines from files.f the same way the
# Quartus / Vivado parsers will. Exits non-zero on any miss.
TOP_PSMCT32_DEMO_SYNTH_DIR := $(REPO_ROOT)/synth/de25_nano/top_psmct32_raster_demo
TOP_PSMCT32_DEMO_FILELIST  := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/files.f

top_psmct32_raster_demo_synth_check: top_psmct32_raster_demo_mem_check
	@echo "=== check top_psmct32_raster_demo synthesis scaffold ==="
	@if [ ! -f $(TOP_PSMCT32_DEMO_FILELIST) ]; then \
	    echo "FAIL: filelist missing: $(TOP_PSMCT32_DEMO_FILELIST)"; \
	    exit 1; \
	fi
	@missing=0; total=0; \
	 while IFS= read -r line; do \
	     stripped=$$(echo "$$line" | sed -E 's/[#].*$$//; s/^[[:space:]]+//; s/[[:space:]]+$$//'); \
	     if [ -z "$$stripped" ]; then continue; fi; \
	     total=$$((total + 1)); \
	     if [ ! -f $(REPO_ROOT)/$$stripped ]; then \
	         echo "  MISSING: $$stripped"; \
	         missing=$$((missing + 1)); \
	     fi; \
	 done < $(TOP_PSMCT32_DEMO_FILELIST); \
	 if [ $$missing -ne 0 ]; then \
	     echo "FAIL: $$missing of $$total files in files.f are missing"; \
	     exit 1; \
	 fi; \
	 echo "  files.f     : $$total entries, all resolve  OK"
	@echo "  fixtures    : bios.mem + payload.mem present  OK"

# ---------------------------------------------------------------------
# Ch150 — Quartus scaffold validator (DE25-Nano).
# ---------------------------------------------------------------------
# Verifies the .qsf + .sdc exist next to files.f, that the .qsf names
# the Ch149 board wrapper as the top entity (NOT the inner Ch146 top),
# that the Ch150 in-scope pins (CLOCK2_50, KEY[0], LED[2:0]) each have
# a `set_location_assignment` line, that the deferred VIDEO_* outputs
# are marked `VIRTUAL_PIN ON` so Quartus can't auto-place them on
# arbitrary package pins, and that the .sdc declares the CLOCK2_50
# 50 MHz period clock constraint. Exits non-zero on any miss.
# Intended as a lightweight pre-Quartus sanity gate.
TOP_PSMCT32_DEMO_QSF := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/de25_nano_psmct32_raster_demo_top.qsf
TOP_PSMCT32_DEMO_SDC := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/de25_nano_psmct32_raster_demo_top.sdc

top_psmct32_raster_demo_quartus_scaffold_check: top_psmct32_raster_demo_synth_check
	@echo "=== check top_psmct32_raster_demo Quartus scaffold ==="
	@if [ ! -f $(TOP_PSMCT32_DEMO_QSF) ]; then \
	    echo "FAIL: .qsf missing: $(TOP_PSMCT32_DEMO_QSF)"; exit 1; \
	fi
	@if [ ! -f $(TOP_PSMCT32_DEMO_SDC) ]; then \
	    echo "FAIL: .sdc missing: $(TOP_PSMCT32_DEMO_SDC)"; exit 1; \
	fi
	@echo "  qsf+sdc     : both present  OK"
	@if ! grep -qE '^set_global_assignment -name TOP_LEVEL_ENTITY de25_nano_psmct32_raster_demo_top' $(TOP_PSMCT32_DEMO_QSF); then \
	    echo "FAIL: .qsf does not set TOP_LEVEL_ENTITY = de25_nano_psmct32_raster_demo_top"; exit 1; \
	fi
	@echo "  top entity  : de25_nano_psmct32_raster_demo_top  OK"
	@missing=0; \
	 for pin in CLOCK2_50 "KEY\\[0\\]" "LED\\[0\\]" "LED\\[1\\]" "LED\\[2\\]"; do \
	     if ! grep -qE "set_location_assignment .* -to $$pin\$$" $(TOP_PSMCT32_DEMO_QSF); then \
	         echo "  MISSING pin assignment: $$pin"; \
	         missing=$$((missing + 1)); \
	     fi; \
	 done; \
	 if [ $$missing -ne 0 ]; then \
	     echo "FAIL: $$missing required pin assignments missing"; exit 1; \
	 fi; \
	 echo "  pins        : CLOCK2_50 + KEY[0] + LED[2:0] all assigned  OK"
	@missing_v=0; \
	 for vp in "VIDEO_R\\[0\\]" "VIDEO_G\\[0\\]" "VIDEO_B\\[0\\]" "VIDEO_HSYNC" "VIDEO_VSYNC" "VIDEO_DE"; do \
	     if ! grep -qE "set_instance_assignment -name VIRTUAL_PIN ON -to $$vp([[:space:]]|\$$)" $(TOP_PSMCT32_DEMO_QSF); then \
	         echo "  MISSING VIRTUAL_PIN ON: $$vp"; \
	         missing_v=$$((missing_v + 1)); \
	     fi; \
	 done; \
	 if [ $$missing_v -ne 0 ]; then \
	     echo "FAIL: $$missing_v deferred video outputs are not marked VIRTUAL_PIN ON (Quartus may auto-place them on arbitrary package pins)"; exit 1; \
	 fi; \
	 echo "  video pins  : VIDEO_R/G/B/HSYNC/VSYNC/DE virtualized (sim/TB compat)  OK"
	@missing_h=0; missing_io=0; \
	 hdmi_pins="HDMI_TX_CLK HDMI_TX_HS HDMI_TX_VS HDMI_TX_DE"; \
	 for n in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23; do \
	     hdmi_pins="$$hdmi_pins HDMI_TX_D\\[$$n\\]"; \
	 done; \
	 for hp in $$hdmi_pins; do \
	     if ! grep -qE "set_location_assignment PIN_[A-Z0-9]+ +-to $$hp\$$" $(TOP_PSMCT32_DEMO_QSF); then \
	         echo "  MISSING HDMI pin assignment: $$hp"; \
	         missing_h=$$((missing_h + 1)); \
	     fi; \
	     if ! grep -qE "set_instance_assignment -name IO_STANDARD .* -to $$hp([[:space:]]|\$$)" $(TOP_PSMCT32_DEMO_QSF); then \
	         echo "  MISSING HDMI IO_STANDARD : $$hp"; \
	         missing_io=$$((missing_io + 1)); \
	     fi; \
	 done; \
	 if [ $$missing_h -ne 0 ] || [ $$missing_io -ne 0 ]; then \
	     echo "FAIL: $$missing_h missing pin assignments + $$missing_io missing IO_STANDARDs across the Ch164 HDMI pin set"; exit 1; \
	 fi; \
	 echo "  hdmi pins   : HDMI_TX_CLK + HDMI_TX_D[0..23] + HS/VS/DE all pin-assigned + IO_STANDARD'd (Ch164)  OK"
	@missing_c=0; \
	 for cp in "HDMI_I2C_SCL" "HDMI_I2C_SDA" "HDMI_TX_INT" "HDMI_MCLK"; do \
	     if ! grep -qE "set_location_assignment PIN_[A-Z0-9]+ +-to $$cp\$$" $(TOP_PSMCT32_DEMO_QSF); then \
	         echo "  MISSING ADV7513 control pin: $$cp"; \
	         missing_c=$$((missing_c + 1)); \
	     fi; \
	     if ! grep -qE "set_instance_assignment -name IO_STANDARD .* -to $$cp([[:space:]]|\$$)" $(TOP_PSMCT32_DEMO_QSF); then \
	         echo "  MISSING ADV7513 IO_STANDARD : $$cp"; \
	         missing_c=$$((missing_c + 1)); \
	     fi; \
	 done; \
	 if [ $$missing_c -ne 0 ]; then \
	     echo "FAIL: $$missing_c missing assignments across the Ch165 ADV7513 control pins"; exit 1; \
	 fi; \
	 echo "  hdmi ctrl   : HDMI_I2C_SCL/SDA + HDMI_TX_INT + HDMI_MCLK all pin-assigned + IO_STANDARD'd (Ch165)  OK"
	@if ! grep -qE 'create_clock -name CLOCK2_50 -period (20\.000|33\.333)' $(TOP_PSMCT32_DEMO_SDC); then \
	    echo "FAIL: .sdc does not declare CLOCK2_50 period 20.000 ns (50 MHz) or 33.333 ns (30 MHz Ch160 down-clock)"; exit 1; \
	fi
	@grep -E 'create_clock -name CLOCK2_50 -period (20\.000|33\.333)' $(TOP_PSMCT32_DEMO_SDC) | head -1 | awk '{print "  clock       : CLOCK2_50 period " $$5 " ns  OK"}'

# ---------------------------------------------------------------------
# Quartus compile driver (DE25-Nano) — added Ch152, retargeted Ch160.
# ---------------------------------------------------------------------
# Runs the full quartus_syn → quartus_fit → quartus_sta → quartus_asm
# flow against the Ch150 .qsf scaffold via build_quartus.sh. The asm
# step is gated on a clean STA so a .sof is produced only when
# timing closes (Ch160). USE_PLL_IP stays undefined so the Ch151
# self-contained PLL stub path is what gets tested.
#
# Logs land in synth/de25_nano/top_psmct32_raster_demo/output_files/
# build_logs/. The companion report-parser target below summarizes
# resource usage, unconstrained paths, and key warning classes.
TOP_PSMCT32_DEMO_BUILD_SH := $(TOP_PSMCT32_DEMO_SYNTH_DIR)/build_quartus.sh

quartus_compile: top_psmct32_raster_demo_quartus_scaffold_check
	@echo "=== quartus_compile : full syn → fit → sta flow ==="
	@$(TOP_PSMCT32_DEMO_BUILD_SH)

quartus_compile_clean: top_psmct32_raster_demo_quartus_scaffold_check
	@echo "=== quartus_compile_clean : wipe outputs then full flow ==="
	@$(TOP_PSMCT32_DEMO_BUILD_SH) clean

quartus_syn_only: top_psmct32_raster_demo_quartus_scaffold_check
	@echo "=== quartus_syn_only : synthesis only (fast smoke) ==="
	@$(TOP_PSMCT32_DEMO_BUILD_SH) syn-only

quartus_compile_report: top_psmct32_raster_demo_quartus_scaffold_check
	@echo "=== quartus_compile_report : parse + summarize last build ==="
	@$(PYTHON) $(TOP_PSMCT32_DEMO_SYNTH_DIR)/parse_reports.py \
	    $(TOP_PSMCT32_DEMO_SYNTH_DIR)/output_files

# ---------------------------------------------------------------------
# Ch153 — memory-forensics experiments.
# ---------------------------------------------------------------------
# Compiles a small set of standalone Quartus projects (one per
# experiment subdirectory under synth/de25_nano/experiments/) that
# isolate one or more memory-shape features at a time. Each project
# targets the same Agilex 5 part as the main board top so resource
# deltas are apples-to-apples.
#
# Current experiments:
#   exp_a_bram_friendly  — single-port sync read + sync write +
#                          per-byte WE, 2048×32-bit (Intel-friendly).
#   exp_b_vram_shape     — exact vram_stub shape (8192×8-bit, dual
#                          combinational read, byte-WE + per-bit
#                          mask RMW).
EXPERIMENTS_DIR := $(REPO_ROOT)/synth/de25_nano/experiments

quartus_experiments:
	@echo "=== quartus_experiments : compile Ch153 memory-forensics projects ==="
	@$(EXPERIMENTS_DIR)/run_experiments.sh

quartus_experiments_clean:
	@echo "=== quartus_experiments_clean : wipe outputs then compile ==="
	@$(EXPERIMENTS_DIR)/run_experiments.sh clean

quartus_experiments_report:
	@echo "=== quartus_experiments_report : side-by-side resource summary ==="
	@$(PYTHON) $(EXPERIMENTS_DIR)/parse_experiments.py $(EXPERIMENTS_DIR)/exp_*


# Must compile in dependency order; trace_pkg first.
RTL_SRCS := \
	$(RTL_ROOT)/debug/trace_pkg.sv \
	$(RTL_ROOT)/debug/trace_sink_stub.sv \
	$(RTL_ROOT)/memory/bios_rom_stub.sv \
	$(RTL_ROOT)/memory/ee_memory_map_stub.sv \
	$(RTL_ROOT)/memory/ee_ram_stub.sv \
	$(RTL_ROOT)/ee/ee_fetch_stub.sv \
	$(RTL_ROOT)/ee/ee_core_stub.sv \
	$(RTL_ROOT)/ee/ee_bootstrap_mmio_stub.sv \
	$(RTL_ROOT)/ee/ee_biu_mmio_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_grad_divider.sv \
	$(RTL_ROOT)/gif_gs/gs_prim_list_feeder.sv \
	$(RTL_ROOT)/gif_gs/gif_path_stub.sv \
	$(RTL_ROOT)/gif_gs/gif_packed_stub.sv \
	$(RTL_ROOT)/gif_gs/vram_stub.sv \
	$(RTL_ROOT)/gif_gs/vram_bram_stub.sv \
	$(RTL_ROOT)/gif_gs/vram_normalize_pkg.sv \
	$(RTL_ROOT)/gif_gs/gs_pcrtc_stub.sv \
	$(RTL_ROOT)/gif_gs/clut_stub.sv \
	$(RTL_ROOT)/gif_gs/clut_loader_stub.sv \
	$(RTL_ROOT)/gif_gs/gif_image_xfer_stub.sv \
	$(RTL_ROOT)/gif_gs/ee_gs_priv_bridge_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_swizzle_psmct32_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_swizzle_psmct16_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_swizzle_psmt8_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_swizzle_psmt4_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_texel_addr.sv \
	$(RTL_ROOT)/gif_gs/gs_texture_unit.sv \
	$(RTL_ROOT)/gif_gs/gs_reciprocal_stub.sv \
	$(RTL_ROOT)/gif_gs/gs_persp_uv.sv \
	$(RTL_ROOT)/gif_gs/gs_tile_ram.sv \
	$(RTL_ROOT)/gif_gs/gs_alpha_blend.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_color_blend.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_fb_writer.sv \
	$(RTL_ROOT)/gif_gs/gs_async_fifo.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_map_pkg.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_axi_master.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_z_rmw.sv \
	$(RTL_ROOT)/gif_gs/gs_axi_w_regbuf.sv \
	$(RTL_ROOT)/gif_gs/gs_axi_aw_regbuf.sv \
	$(RTL_ROOT)/gif_gs/gs_axi_r_regbuf.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_zc_emit.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_rd_probe.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_scanout.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_rd_arb.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_scanout_lb.sv \
	$(RTL_ROOT)/gif_gs/gs_texture_cache.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_wr_probe.sv \
	$(RTL_ROOT)/gif_gs/gs_lpddr_wr_arb.sv \
	$(RTL_ROOT)/gif_gs/gs_tile_reload.sv \
	$(RTL_ROOT)/gif_gs/gs_z_flush_writer.sv \
	$(RTL_ROOT)/platform/platform_video_stub.sv \
	$(RTL_ROOT)/platform/I2C_Controller.v \
	$(RTL_ROOT)/platform/I2C_HDMI_Config.v \
	$(RTL_ROOT)/platform/ps2_hps_bridge_null.sv \
	$(RTL_ROOT)/platform/ps2_hps_bridge.sv \
	$(RTL_ROOT)/platform/clut_stage_cdc.sv \
	$(RTL_ROOT)/platform/tile_ram_cdc.sv \
	$(SPLASH_PLATFORM_RTL)/osd_overlay.sv \
	$(SPLASH_PLATFORM_RTL)/osd_font_rom.sv \
	$(SPLASH_PLATFORM_RTL)/osd_menu_fsm.sv \
	$(SPLASH_PLATFORM_RTL)/ds2_controller.sv \
	$(REPO_ROOT)/qsys/qsys_top/qsys_top_bb.v \
	$(RTL_ROOT)/intc/intc_stub.sv \
	$(RTL_ROOT)/dmac/dmac_reg_stub.sv \
	$(RTL_ROOT)/dmac/ee_dmac_ctrl_stub.sv \
	$(RTL_ROOT)/dmac/ee_dmac_passive_chan_stub.sv \
	$(RTL_ROOT)/sif/sif_mailbox_stub.sv \
	$(RTL_ROOT)/sif/sif_mailbox_peer_stub.sv \
	$(RTL_ROOT)/sif/sif_dma_stub.sv \
	$(RTL_ROOT)/sif/sif_dma_ack_peer_stub.sv \
	$(RTL_ROOT)/sif/sif_dma_iop_ram_bridge_stub.sv \
	$(RTL_ROOT)/sif/sif_dma_ee_ram_bridge_stub.sv \
	$(RTL_ROOT)/sif/sif_dma_ee_ack_peer_stub.sv \
	$(RTL_ROOT)/sif/boot_install_agent_stub.sv \
	$(RTL_ROOT)/iop/iop_ram_stub.sv \
	$(RTL_ROOT)/iop/sio2_input_stub.sv \
	$(RTL_ROOT)/iop/iop_memory_map_stub.sv \
	$(RTL_ROOT)/iop/iop_fetch_stub.sv \
	$(RTL_ROOT)/iop/iop_dmac_reg_stub.sv \
	$(RTL_ROOT)/iop/iop_exec_stub.sv \
	$(RTL_ROOT)/iop/iop_core_stub.sv \
	$(RTL_ROOT)/top/top_psmct32_raster_demo.sv \
	$(RTL_ROOT)/top/top_psmct32_raster_demo_bram.sv \
	$(RTL_ROOT)/top/de25_nano_pll_stub.sv \
	$(RTL_ROOT)/top/de25_nano_psmct32_raster_demo_top.sv

IVERILOG      := iverilog
IVERILOG_FLGS := -g2012 -Wall
VVP           := vvp

VERILATOR       := verilator
VERILATOR_FLAGS := --lint-only -sv -Wall -Wno-UNUSED -Wno-DECLFILENAME \
                   --timing

.PHONY: tb_ee_core_bios_long
.PHONY: top_psmct32_raster_demo_mem top_psmct32_raster_demo_mem_check top_psmct32_raster_demo_synth_check top_psmct32_raster_demo_quartus_scaffold_check sh3_zsched_fixture quartus_compile quartus_compile_clean quartus_syn_only quartus_compile_report quartus_experiments quartus_experiments_clean quartus_experiments_report
.PHONY: all lint run clean traces tb_ee_fetch tb_gs tb_intc tb_platform_video tb_bgcolor_via_dma \
        tb_sif_mailbox tb_sif_command_echo tb_sif_command_echo_rearm tb_sif_negative_path \
        tb_sif_dma_smoke tb_sif_dma_mid_stall tb_sif_dma_overflow tb_sif_combined_ctrl_data \
        tb_iop_ram tb_iop_memory_map tb_iop_memory_map_collision tb_iop_fetch_through_map tb_sif_iop_bridge_smoke \
        tb_sif_iop_bridge_exec tb_iop_to_sif_via_map tb_iop_dmac_via_map \
        tb_sif_ee_landing_via_dmac tb_sif_iop_driven_combined \
        tb_ee_dmac_intc tb_iop_dmac_intc tb_iop_self_driven \
        tb_iop_autonomous_two_xfers tb_iop_responder_ee_ram_landing \
        tb_iop_core_basic tb_iop_core_interrupts \
        tb_iop_core_bootstrap tb_iop_core_bootstrap_intc tb_iop_core_bios_smoke \
        tb_ee_core_basic tb_ee_core_memops tb_ee_core_dmac \
        tb_ee_core_dmac_poll tb_ee_core_dmac_intc tb_ee_core_bios_smoke \
        tb_ee_core_slti tb_ee_core_addi tb_ee_core_andi tb_ee_core_cache \
        tb_ee_core_rtype_logic tb_ee_core_sb tb_ee_core_lb tb_ee_core_jal \
        tb_ee_core_rtype_addu tb_ee_core_slt tb_ee_core_lh tb_ee_core_lhu \
        tb_ee_core_shift tb_ee_core_sh tb_ee_core_jalr tb_ee_core_add_sub \
        tb_ee_core_branch_zero tb_ee_core_lbu tb_ee_core_divu_mflo tb_ee_core_multu_mflo \
        tb_ee_core_align tb_ee_core_align_exc tb_ee_core_bev \
        tb_ee_core_cop0_count tb_ee_bootstrap_mmio tb_ee_biu_mmio \
        tb_ee_core_gif_packed tb_ee_core_gif_reglist tb_ee_core_gif_primitive tb_ee_core_gif_primitive_observer tb_ee_core_gif_primitive_strip tb_ee_core_gif_primitive_gouraud tb_ee_core_gif_pixel_emit tb_ee_core_gif_pixel_emit_psm tb_ee_core_gif_raster_basic tb_ee_core_gif_raster_topleft tb_ee_core_gif_raster_gouraud tb_ee_core_gif_raster_queue tb_gs_raster_queue_full_pop tb_gs_raster_pipeline tb_gs_prim_list_feeder tb_gs_vram_writeback tb_vram_stub tb_vram_bram_stub_equivalence tb_vram_normalize_write tb_gs_scanout_basic tb_gs_scanout_dbx_dby tb_gs_scanout_display_window tb_gs_scanout_magh_magv tb_gs_scanout_psm16 tb_gs_scanout_psmt8 tb_gs_scanout_psmt8_clut tb_gs_tex0_clut tb_gs_clut_load tb_gs_clut_load_ct16 tb_gs_clut_load_cld_modes tb_gs_clut_load_csa_window tb_gs_scanout_psmt4_clut tb_gs_psmt4_round_trip tb_gs_raster_psmct16 tb_gs_raster_psmt8 tb_gs_textured_sprite tb_gs_textured_alpha_sprite tb_gs_psmt8_alpha_sprite tb_gs_psmt8_clut_triangle tb_clut_loader_csm1 tb_gs_raster_psmct4 tb_gs_demo_psmt4_e2e tb_gs_demo_psmt4_e2e_packed tb_gs_demo_psmt4_e2e_dmac tb_gs_demo_psmt4_e2e_trxdir tb_gs_demo_psmt4_e2e_eemmio tb_gs_demo_psmt4_e2e_eemap tb_gs_demo_psmt4_e2e_ee_program tb_gs_demo_psmt4_e2e_ee_full_bootlet tb_ee_ram_cpu_dmac_contention tb_gs_image_xfer_psmct16 tb_gs_image_xfer_psmt8 tb_gs_image_xfer_psmt4 tb_gs_swizzle_psmct32 tb_gs_swizzle_psmct16 tb_gs_swizzle_psmt8 tb_gs_swizzle_psmt4 tb_gs_scanout_swizzle_psmt4 tb_gs_image_xfer_swizzle_psmt4 tb_gs_raster_swizzle_psmt4 tb_gs_demo_psmt4_swizzle_e2e tb_gs_demo_psmt4_swizzle_trxdir_e2e tb_top_psmct32_raster_demo tb_top_psmct32_textured_demo tb_top_psmct32_raster_demo_bram tb_top_psmct32_raster_demo_bram_textured tb_top_psmct32_raster_demo_bram_ch171 tb_gs_raster_backpressure_stress tb_ps2_hps_bridge tb_gs_raster_bram_psmct16 tb_gs_raster_bram_psmt8 tb_gs_raster_bram_psmt4 tb_gs_scanout_bram_psmct16 tb_gs_scanout_bram_psmt8 tb_de25_nano_psmct32_raster_demo_top tb_hdmi_i2c_wake_smoke tb_gs_scanout_swizzle_psmt8 tb_gs_image_xfer_swizzle_psmt8 tb_gs_raster_swizzle_psmt8 tb_gs_demo_psmt8_swizzle_e2e tb_gs_demo_psmt8_swizzle_trxdir_e2e tb_gs_scanout_swizzle_psmct16 tb_gs_image_xfer_swizzle_psmct16 tb_gs_scanout_swizzle_psmct32 tb_gs_image_xfer_swizzle_psmct32 tb_gs_raster_swizzle_psmct32 tb_gs_raster_swizzle_psmct16 tb_gs_demo_psmct32_swizzle_e2e tb_gs_demo_psmct32_swizzle_trxdir_e2e tb_gs_demo_psmct16_swizzle_e2e tb_gs_demo_psmct16_swizzle_trxdir_e2e tb_ee_core_varshift tb_ee_install_agent_smoke tb_ee_install_agent_external_image tb_tile_ram_cdc tb_sio2_input_stub tb_bridge_iop_pad_input tb_pad_state_via_sif_to_ee tb_ee_pad_buffer_branch tb_lpddr_tex_staging tb_osd_platform_cell_adapter tb_ee_core_elf_runner tb_ee_core_sq tb_ee_core_daddu tb_ee_core_syscall_hle tb_ee_core_beql tb_ee_core_sd tb_ee_core_dsll tb_ee_core_bnel tb_ee_core_pcpyld tb_ee_core_lq tb_ee_core_psubb tb_ee_core_pnor tb_ee_core_pand tb_ee_core_pcpyud tb_ee_core_ld tb_ee_core_ei tb_ee_dmac_ctrl_stub tb_ee_dmac_passive_chan_stub tb_ee_core_sync tb_ee_core_pcpyh tb_ee_core_dsubu tb_gs_async_fifo tb_gs_lpddr_fb_writer tb_gs_lpddr_axi_master tb_gs_lpddr_axi_master_elastic tb_gs_lpddr_scanout_fb tb_gs_lpddr_rd_probe tb_gs_lpddr_scanout tb_gs_lpddr_scanout_psm32 tb_gs_lpddr_scanout_concurrency tb_gs_lpddr_scanout_lb_psm32 tb_gs_lpddr_scanout_lb_psm32_256 tb_gs_lpddr_rd_arb tb_gs_lpddr_scanout_lb tb_gs_texture_cache tb_gs_lpddr_wr_probe tb_gs_lpddr_wr_arb tb_gs_tile_reload tb_gs_tile_reload_grid tb_gs_z_flush_writer tb_gs_alpha_blend tb_top_psmct32_alpha_blend_demo tb_top_psmct32_texalpha_demo tb_gs_zbuffer tb_top_psmct32_zbuffer_demo tb_gs_tri_interp tb_gs_fog tb_gs_fog_persp tb_gs_feeder_fog_e2e tb_gs_fog_disabled tb_top_psmct32_triangle_demo tb_gs_textured_triangle tb_top_psmct32_raster_demo_bram_tritex tb_top_psmct32_raster_demo_bram_lpddrtex tb_gs_texture_psmt8_clut tb_gs_texture_wrap tb_gs_texture_bilinear tb_top_psmct32_raster_demo_bram_clut tb_gs_texture_psmt4_clut tb_gs_texture_swizzle_psmt4_clut tb_top_psmct32_raster_demo_bram_clut4 tb_top_psmct32_raster_demo_bram_swz4 tb_gs_texture_swizzle_psmt8_clut tb_top_psmct32_raster_demo_bram_swz8 tb_gs_texture_swizzle_psmct32 tb_top_psmct32_raster_demo_bram_swz32 tb_gs_reciprocal tb_gs_persp_uv tb_gs_persp_uv_farw tb_gs_grad_divider tb_top_psmct32_perspective_demo tb_top_psmct32_persp_floor_demo tb_top_psmct32_combined_demo tb_gs_tile_ram tb_top_psmct32_tile_demo tb_gs_tile_zflush tb_gs_tile_spill_reload tb_gs_tile_spill_lpddr tb_gs_tile_spill_grid_lpddr tb_gs_tile_spill_grid8x8_lpddr tb_gs_tile_spill_lpddr_neg tb_top_psmct32_tile2x2_demo tb_top_psmct32_tile_multiprim_demo tb_top_psmct32_tile_scissor_demo tb_top_psmct32_tile_wrap_demo tb_top_psmct32_tile_psmct16_demo tb_top_psmct32_tile_alpha_demo tb_top_psmct32_tile_bilinear_demo tb_top_psmct32_tile_bin_demo tb_top_psmct32_tile_bin4x4_demo tb_top_psmct32_tile_psmct16fb_demo tb_top_psmct32_tile_lpddr128_demo tb_top_psmct32_tile_palbilinear_demo tb_top_psmct32_tile_cap_demo tb_top_psmct32_tile_cap_overflow_demo tb_top_psmct32_tile_sprite18_demo tb_top_psmct32_tile_cap64_demo tb_top_psmct32_feeder_equiv_demo tb_top_psmct32_feeder_runtime_demo tb_top_psmct32_feeder_bridge_demo tb_top_psmct32_feeder_scenes_demo tb_top_psmct32_feeder_shapes_demo tb_top_psmct32_feeder_colors_demo tb_top_psmct32_feeder_native_demo tb_top_psmct32_feeder_gouraud_demo tb_top_psmct32_feeder_accum_demo tb_top_psmct32_feeder_scene_retrigger_demo tb_top_psmct32_feeder_zpersist_demo tb_top_psmct32_feeder_persp_demo tb_top_psmct32_feeder_sprite_demo tb_top_psmct32_tile_late_demo tb_top_psmct32_tile_lpddrfb_demo \
        dirs all_checks full_checks golden_nop compare_ee_fetch test_compare

all: run

# ---------------------------------------------------------------------
# Aggregate quality gate
# ---------------------------------------------------------------------
#
# "make lint" alone does not compile the testbenches — it only runs
# Verilator over RTL. "make all_checks" is the documented gate: lint +
# every testbench builds and runs.
#
all_checks: lint run
	@echo
	@echo "=== all_checks: lint + all testbenches green ==="

# Full regression: lint + all testbenches + golden-harness comparator
# (exercises the 0/1/3 exit-code paths). Use this when you want the widest
# possible "everything green" gate; use `all_checks` when you only care
# about RTL + bench health.
full_checks: all_checks test_compare
	@echo
	@echo "=== full_checks: all_checks + test_compare green ==="

dirs:
	@mkdir -p $(BUILD_DIR) $(TRACE_DIR) $(GOLD_TRC_DIR)
	@# Ch245 — the platform osd_font_rom.sv uses a CWD-relative
	@# `$$readmemh("rtl/platform/cp437_8x8.mem", ...)`. When vvp
	@# runs from $(TRACE_DIR), it needs that path to resolve.
	@# Symlink retroDE_splash/rtl tree under it so the read works.
	@mkdir -p $(TRACE_DIR)/rtl
	@if [ ! -L $(TRACE_DIR)/rtl/platform ]; then \
	    ln -snf $(SPLASH_PLATFORM_RTL) $(TRACE_DIR)/rtl/platform; \
	fi

# ---------------------------------------------------------------------
# Lint (Verilator, strict)
# ---------------------------------------------------------------------

lint:
	@echo "=== verilator lint ==="
	$(VERILATOR) $(VERILATOR_FLAGS) \
	    --top-module trace_sink_stub \
	    $(RTL_SRCS)
	@echo "lint: OK"

# ---------------------------------------------------------------------
# Individual testbenches (Icarus Verilog)
# ---------------------------------------------------------------------

tb_ee_fetch: dirs
	@echo "=== build tb_ee_fetch_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_fetch_stub.vvp \
	    -s tb_ee_fetch_stub \
	    $(RTL_SRCS) $(TB_ROOT)/ee/tb_ee_fetch_stub.sv
	@echo "=== run tb_ee_fetch_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_fetch_stub.vvp

tb_gs: dirs
	@echo "=== build tb_gs_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_stub.vvp \
	    -s tb_gs_stub \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_stub.sv
	@echo "=== run tb_gs_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_stub.vvp

tb_gs_prim_list_feeder: dirs
	@echo "=== build tb_gs_prim_list_feeder ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_prim_list_feeder.vvp \
	    -s tb_gs_prim_list_feeder \
	    $(RTL_ROOT)/gif_gs/gs_prim_list_feeder.sv $(TB_ROOT)/gif_gs/tb_gs_prim_list_feeder.sv
	@echo "=== run tb_gs_prim_list_feeder ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_prim_list_feeder.vvp

tb_gs_raster_queue_full_pop: dirs
	@echo "=== build tb_gs_raster_queue_full_pop ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_queue_full_pop.vvp \
	    -s tb_gs_raster_queue_full_pop \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_queue_full_pop.sv
	@echo "=== run tb_gs_raster_queue_full_pop ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_queue_full_pop.vvp

GS_RASTER_PIPELINE_IVERILOG_ARGS ?=
tb_gs_raster_pipeline: dirs
	@echo "=== build tb_gs_raster_pipeline ==="
	$(IVERILOG) $(IVERILOG_FLGS) $(GS_RASTER_PIPELINE_IVERILOG_ARGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_pipeline.vvp \
	    -s tb_gs_raster_pipeline \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_pipeline.sv
	@echo "=== run tb_gs_raster_pipeline ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_pipeline.vvp

tb_gs_subpixel_xy:
	@$(MAKE) GS_RASTER_PIPELINE_IVERILOG_ARGS="-Ptb_gs_raster_pipeline.USE_SUBPIXEL=1 -Ptb_gs_raster_pipeline.GRAD_CYCLES=5" tb_gs_raster_pipeline

tb_gs_vram_writeback: dirs
	@echo "=== build tb_gs_vram_writeback ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_vram_writeback.vvp \
	    -s tb_gs_vram_writeback \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_vram_writeback.sv
	@echo "=== run tb_gs_vram_writeback ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_vram_writeback.vvp

tb_vram_stub: dirs
	@echo "=== build tb_vram_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_vram_stub.vvp \
	    -s tb_vram_stub \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_vram_stub.sv
	@echo "=== run tb_vram_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_vram_stub.vvp

tb_vram_bram_stub_equivalence: dirs
	@echo "=== build tb_vram_bram_stub_equivalence ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_vram_bram_stub_equivalence.vvp \
	    -s tb_vram_bram_stub_equivalence \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_vram_bram_stub_equivalence.sv
	@echo "=== run tb_vram_bram_stub_equivalence ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_vram_bram_stub_equivalence.vvp

tb_vram_normalize_write: dirs
	@echo "=== build tb_vram_normalize_write ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_vram_normalize_write.vvp \
	    -s tb_vram_normalize_write \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_vram_normalize_write.sv
	@echo "=== run tb_vram_normalize_write ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_vram_normalize_write.vvp

tb_gs_scanout_basic: dirs
	@echo "=== build tb_gs_scanout_basic ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_basic.vvp \
	    -s tb_gs_scanout_basic \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_basic.sv
	@echo "=== run tb_gs_scanout_basic ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_basic.vvp

tb_gs_scanout_dbx_dby: dirs
	@echo "=== build tb_gs_scanout_dbx_dby ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_dbx_dby.vvp \
	    -s tb_gs_scanout_dbx_dby \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_dbx_dby.sv
	@echo "=== run tb_gs_scanout_dbx_dby ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_dbx_dby.vvp

tb_gs_scanout_display_window: dirs
	@echo "=== build tb_gs_scanout_display_window ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_display_window.vvp \
	    -s tb_gs_scanout_display_window \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_display_window.sv
	@echo "=== run tb_gs_scanout_display_window ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_display_window.vvp

tb_gs_scanout_magh_magv: dirs
	@echo "=== build tb_gs_scanout_magh_magv ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_magh_magv.vvp \
	    -s tb_gs_scanout_magh_magv \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_magh_magv.sv
	@echo "=== run tb_gs_scanout_magh_magv ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_magh_magv.vvp

tb_gs_scanout_psm16: dirs
	@echo "=== build tb_gs_scanout_psm16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_psm16.vvp \
	    -s tb_gs_scanout_psm16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psm16.sv
	@echo "=== run tb_gs_scanout_psm16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psm16.vvp

tb_gs_raster_psmct16: dirs
	@echo "=== build tb_gs_raster_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_psmct16.vvp \
	    -s tb_gs_raster_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_psmct16.sv
	@echo "=== run tb_gs_raster_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_psmct16.vvp

tb_gs_raster_psmt8: dirs
	@echo "=== build tb_gs_raster_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_psmt8.vvp \
	    -s tb_gs_raster_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_psmt8.sv
	@echo "=== run tb_gs_raster_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_psmt8.vvp

tb_gs_textured_sprite: dirs
	@echo "=== build tb_gs_textured_sprite ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_textured_sprite.vvp \
	    -s tb_gs_textured_sprite \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_textured_sprite.sv
	@echo "=== run tb_gs_textured_sprite ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_textured_sprite.vvp

# Ch344 — synthetic textured + source-over alpha SPRITE unit test (SPRITE_TEX_ALPHA=1).
# Proves: no read2 overlap (tex_rd_en & fb_rd_en never both high), As from the texel, MODULATE by
# the vertex tint, output matches an independent software source-over reference.
tb_gs_textured_alpha_sprite: dirs
	@echo "=== build tb_gs_textured_alpha_sprite ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_textured_alpha_sprite.vvp \
	    -s tb_gs_textured_alpha_sprite \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_textured_alpha_sprite.sv
	@echo "=== run tb_gs_textured_alpha_sprite ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_textured_alpha_sprite.vvp


tb_gs_textured_triangle: dirs
	@echo "=== build tb_gs_textured_triangle ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_textured_triangle.vvp \
	    -s tb_gs_textured_triangle \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_textured_triangle.sv
	@echo "=== run tb_gs_textured_triangle ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_textured_triangle.vvp

# Ch296 — PSMT8 indexed texture sampling (gs_texture_unit + clut_stub):
# index-fetch -> CLUT lookup -> PSMCT32 color. The 4 sampler proofs.
tb_gs_texture_psmt8_clut: dirs
	@echo "=== build tb_gs_texture_psmt8_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_psmt8_clut.vvp \
	    -s tb_gs_texture_psmt8_clut \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_psmt8_clut.sv
	@echo "=== run tb_gs_texture_psmt8_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_psmt8_clut.vvp

tb_gs_psmt8_alpha_sprite: dirs
	@echo "=== build tb_gs_psmt8_alpha_sprite ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_psmt8_alpha_sprite.vvp \
	    -s tb_gs_psmt8_alpha_sprite \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_psmt8_alpha_sprite.sv
	@echo "=== run tb_gs_psmt8_alpha_sprite ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_psmt8_alpha_sprite.vvp

tb_gs_psmt8_clut_triangle: dirs
	@echo "=== build tb_gs_psmt8_clut_triangle ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_psmt8_clut_triangle.vvp \
	    -s tb_gs_psmt8_clut_triangle \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_psmt8_clut_triangle.sv
	@echo "=== run tb_gs_psmt8_clut_triangle ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_psmt8_clut_triangle.vvp

tb_clut_loader_csm1: dirs
	@echo "=== build tb_clut_loader_csm1 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_clut_loader_csm1.vvp \
	    -s tb_clut_loader_csm1 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_clut_loader_csm1.sv
	@echo "=== run tb_clut_loader_csm1 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_clut_loader_csm1.vvp

tb_gs_sh3_clut_sprite: dirs
	@echo "=== build tb_gs_sh3_clut_sprite ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_sh3_clut_sprite.vvp \
	    -s tb_gs_sh3_clut_sprite \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_sh3_clut_sprite.sv
	@echo "=== run tb_gs_sh3_clut_sprite ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_sh3_clut_sprite.vvp

tb_gs_texture_wrap: dirs
	@echo "=== build tb_gs_texture_wrap ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_wrap.vvp \
	    -s tb_gs_texture_wrap \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_wrap.sv
	@echo "=== run tb_gs_texture_wrap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_wrap.vvp

tb_gs_texture_bilinear: dirs
	@echo "=== build tb_gs_texture_bilinear ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_bilinear.vvp \
	    -s tb_gs_texture_bilinear \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_bilinear.sv
	@echo "=== run tb_gs_texture_bilinear ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_bilinear.vvp

# Ch297 — PSMT4 indexed texture sampling (gs_texture_unit nibble extract +
# clut_stub): nibble-select -> CLUT lookup -> PSMCT32 color. The 4 sampler
# proofs (incl. SEL_DELAY=1 nibble re-pair) + PSMT8/PSMCT32 bit-identical.
tb_gs_texture_psmt4_clut: dirs
	@echo "=== build tb_gs_texture_psmt4_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_psmt4_clut.vvp \
	    -s tb_gs_texture_psmt4_clut \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_psmt4_clut.sv
	@echo "=== run tb_gs_texture_psmt4_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_psmt4_clut.vvp

# Ch298 — SWIZZLED PSMT4 texture sampling (gs_texture_unit PSMT4_SWIZZLE=1 ->
# gs_swizzle_psmt4_stub addr/nibble). Proves swizzled read recovers the logical
# pattern across BLOCK and PAGE boundaries, swizzled!=linear for the same bytes,
# CLUT indirection, and SEL_DELAY=1 alignment of the swizzled selectors.
tb_gs_texture_swizzle_psmt4_clut: dirs
	@echo "=== build tb_gs_texture_swizzle_psmt4_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_swizzle_psmt4_clut.vvp \
	    -s tb_gs_texture_swizzle_psmt4_clut \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_swizzle_psmt4_clut.sv
	@echo "=== run tb_gs_texture_swizzle_psmt4_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_swizzle_psmt4_clut.vvp

tb_gs_texture_swizzle_psmt8_clut: dirs
	@echo "=== build tb_gs_texture_swizzle_psmt8_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_swizzle_psmt8_clut.vvp \
	    -s tb_gs_texture_swizzle_psmt8_clut \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_swizzle_psmt8_clut.sv
	@echo "=== run tb_gs_texture_swizzle_psmt8_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_swizzle_psmt8_clut.vvp

tb_gs_texture_swizzle_psmct32: dirs
	@echo "=== build tb_gs_texture_swizzle_psmct32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_swizzle_psmct32.vvp \
	    -s tb_gs_texture_swizzle_psmct32 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_swizzle_psmct32.sv
	@echo "=== run tb_gs_texture_swizzle_psmct32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_swizzle_psmct32.vvp

tb_gs_reciprocal: dirs
	@echo "=== build tb_gs_reciprocal ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_reciprocal.vvp \
	    -s tb_gs_reciprocal \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_reciprocal.sv
	@echo "=== run tb_gs_reciprocal ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_reciprocal.vvp

tb_gs_persp_uv_farw: dirs
	@echo "=== build tb_gs_persp_uv_farw ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_persp_uv_farw.vvp \
	    -s tb_gs_persp_uv_farw \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_persp_uv_farw.sv
	@echo "=== run tb_gs_persp_uv_farw ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_persp_uv_farw.vvp

tb_gs_persp_uv: dirs
	@echo "=== build tb_gs_persp_uv ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_persp_uv.vvp \
	    -s tb_gs_persp_uv \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_persp_uv.sv
	@echo "=== run tb_gs_persp_uv ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_persp_uv.vvp

tb_gs_tile_ram: dirs
	@echo "=== build tb_gs_tile_ram ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_tile_ram.vvp \
	    -s tb_gs_tile_ram \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tile_ram.sv
	@echo "=== run tb_gs_tile_ram ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_ram.vvp

tb_gs_alpha_blend: dirs
	@echo "=== build tb_gs_alpha_blend ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_alpha_blend.vvp \
	    -s tb_gs_alpha_blend \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_alpha_blend.sv
	@echo "=== run tb_gs_alpha_blend ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_alpha_blend.vvp

tb_gs_lpddr_color_blend: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -o $(BUILD_DIR)/tb_gs_lpddr_color_blend.vvp -s tb_gs_lpddr_color_blend $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_color_blend.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_color_blend.vvp

tb_gs_lpddr_fb_writer: dirs
	@echo "=== build tb_gs_lpddr_fb_writer ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_fb_writer.vvp \
	    -s tb_gs_lpddr_fb_writer \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_fb_writer.sv
	@echo "=== run tb_gs_lpddr_fb_writer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_fb_writer.vvp

tb_gs_lpddr_axi_master: dirs
	@echo "=== build tb_gs_lpddr_axi_master ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_axi_master.vvp \
	    -s tb_gs_lpddr_axi_master \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_axi_master.sv
	@echo "=== run tb_gs_lpddr_axi_master ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_axi_master.vvp

tb_gs_lpddr_axi_master_elastic: dirs
	@echo "=== build tb_gs_lpddr_axi_master_elastic ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_axi_master_elastic.vvp \
	    -s tb_gs_lpddr_axi_master_elastic \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_axi_master_elastic.sv
	@echo "=== run tb_gs_lpddr_axi_master_elastic ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_axi_master_elastic.vvp

tb_gs_async_fifo: dirs
	@echo "=== build tb_gs_async_fifo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_async_fifo.vvp \
	    -s tb_gs_async_fifo \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_async_fifo.sv
	@echo "=== run tb_gs_async_fifo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_async_fifo.vvp

tb_gs_async_fifo_banked: dirs
	@echo "=== build tb_gs_async_fifo_banked ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -P tb_gs_async_fifo.TEST_BANKED=1 \
	    -o $(BUILD_DIR)/tb_gs_async_fifo_banked.vvp \
	    -s tb_gs_async_fifo \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_async_fifo.sv
	@echo "=== run tb_gs_async_fifo_banked ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_async_fifo_banked.vvp

tb_gs_async_fifo_quadrant: dirs
	@echo "=== build tb_gs_async_fifo_quadrant ==="
	$(IVERILOG) -g2012 -Wall \
	    -P tb_gs_async_fifo.TEST_QUADRANT=1 \
	    -o $(BUILD_DIR)/tb_gs_async_fifo_quadrant.vvp \
	    -s tb_gs_async_fifo \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_async_fifo.sv
	@echo "=== run tb_gs_async_fifo_quadrant ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_async_fifo_quadrant.vvp

tb_gs_async_fifo_quad_width4: dirs
	@echo "=== build tb_gs_async_fifo_quad_width4 ==="
	$(IVERILOG) -g2012 -Wall \
	    -P tb_gs_async_fifo.TEST_QUAD_WIDTH4=1 \
	    -o $(BUILD_DIR)/tb_gs_async_fifo_quad_width4.vvp \
	    -s tb_gs_async_fifo \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_async_fifo.sv
	@echo "=== run tb_gs_async_fifo_quad_width4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_async_fifo_quad_width4.vvp

tb_gs_async_fifo_registered: dirs
	@echo "=== build tb_gs_async_fifo_registered ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -P tb_gs_async_fifo.TEST_REGISTERED=1 \
	    -o $(BUILD_DIR)/tb_gs_async_fifo_registered.vvp \
	    -s tb_gs_async_fifo \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_async_fifo.sv
	@echo "=== run tb_gs_async_fifo_registered ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_async_fifo_registered.vvp

# Ch357 gate 1 — standalone packed PSMZ16S LPDDR Z read-modify-write engine unit test.
tb_gs_lpddr_z_rmw: dirs
	@echo "=== build tb_gs_lpddr_z_rmw ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_z_rmw.vvp \
	    -s tb_gs_lpddr_z_rmw \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_z_rmw.sv
	@echo "=== run tb_gs_lpddr_z_rmw ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_z_rmw.vvp

# Ch357 — Z-then-color integration wrapper (request FIFO + Z RMW + color writer + scene drain) unit test.
tb_gs_lpddr_zc_emit: dirs
	@echo "=== build tb_gs_lpddr_zc_emit ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_zc_emit.vvp \
	    -s tb_gs_lpddr_zc_emit \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_zc_emit.sv
	@echo "=== run tb_gs_lpddr_zc_emit ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_zc_emit.vvp

tb_gs_axi_w_regbuf: dirs
	@echo "=== build tb_gs_axi_w_regbuf ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_axi_w_regbuf.vvp \
	    -s tb_gs_axi_w_regbuf \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_axi_w_regbuf.sv
	@echo "=== run tb_gs_axi_w_regbuf ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_axi_w_regbuf.vvp

tb_gs_axi_aw_regbuf: dirs
	@echo "=== build tb_gs_axi_aw_regbuf ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_axi_aw_regbuf.vvp \
	    -s tb_gs_axi_aw_regbuf \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_axi_aw_regbuf.sv
	@echo "=== run tb_gs_axi_aw_regbuf ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_axi_aw_regbuf.vvp

tb_gs_axi_r_regbuf: dirs
	@echo "=== build tb_gs_axi_r_regbuf ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_axi_r_regbuf.vvp \
	    -s tb_gs_axi_r_regbuf \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_axi_r_regbuf.sv
	@echo "=== run tb_gs_axi_r_regbuf ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_axi_r_regbuf.vvp

tb_gs_grad_divider: dirs
	@echo "=== build tb_gs_grad_divider ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_grad_divider.vvp \
	    -s tb_gs_grad_divider \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_grad_divider.sv
	@echo "=== run tb_gs_grad_divider ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_grad_divider.vvp

tb_gs_grad_num_equiv: dirs
	@echo "=== build tb_gs_grad_num_equiv ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_grad_num_equiv.vvp \
	    -s tb_gs_grad_num_equiv \
	    $(TB_ROOT)/gif_gs/tb_gs_grad_num_equiv.sv
	@echo "=== run tb_gs_grad_num_equiv ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_grad_num_equiv.vvp

tb_gs_lpddr_scanout_fb: dirs
	@echo "=== build tb_gs_lpddr_scanout_fb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_fb.vvp \
	    -s tb_gs_lpddr_scanout_fb \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_fb.sv
	@echo "=== run tb_gs_lpddr_scanout_fb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_fb.vvp

tb_gs_lpddr_rd_probe: dirs
	@echo "=== build tb_gs_lpddr_rd_probe ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_rd_probe.vvp \
	    -s tb_gs_lpddr_rd_probe \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_rd_probe.sv
	@echo "=== run tb_gs_lpddr_rd_probe ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_rd_probe.vvp

tb_gs_lpddr_scanout: dirs
	@echo "=== build tb_gs_lpddr_scanout ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout.vvp \
	    -s tb_gs_lpddr_scanout \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout.sv
	@echo "=== run tb_gs_lpddr_scanout ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout.vvp

tb_gs_lpddr_scanout_lb_psm32_256: dirs
	@echo "=== build tb_gs_lpddr_scanout_lb_psm32_256 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32_256.vvp \
	    -s tb_gs_lpddr_scanout_lb_psm32_256 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb_psm32_256.sv
	@echo "=== run tb_gs_lpddr_scanout_lb_psm32_256 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32_256.vvp

tb_gs_lpddr_scanout_lb_psm32: dirs
	@echo "=== build tb_gs_lpddr_scanout_lb_psm32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32.vvp \
	    -s tb_gs_lpddr_scanout_lb_psm32 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb_psm32.sv
	@echo "=== run tb_gs_lpddr_scanout_lb_psm32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_psm32.vvp

tb_gs_lpddr_scanout_concurrency: dirs
	@echo "=== build tb_gs_lpddr_scanout_concurrency ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_concurrency.vvp \
	    -s tb_gs_lpddr_scanout_concurrency \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_concurrency.sv
	@echo "=== run tb_gs_lpddr_scanout_concurrency ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_concurrency.vvp

tb_gs_lpddr_scanout_psm32: dirs
	@echo "=== build tb_gs_lpddr_scanout_psm32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_psm32.vvp \
	    -s tb_gs_lpddr_scanout_psm32 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_psm32.sv
	@echo "=== run tb_gs_lpddr_scanout_psm32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_psm32.vvp

tb_gs_lpddr_rd_arb: dirs
	@echo "=== build tb_gs_lpddr_rd_arb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_rd_arb.vvp \
	    -s tb_gs_lpddr_rd_arb \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_rd_arb.sv
	@echo "=== run tb_gs_lpddr_rd_arb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_rd_arb.vvp

tb_gs_lpddr_scanout_lb: dirs
	@echo "=== build tb_gs_lpddr_scanout_lb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb.vvp \
	    -s tb_gs_lpddr_scanout_lb \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb.sv
	@echo "=== run tb_gs_lpddr_scanout_lb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb.vvp

tb_gs_lpddr_scanout_lb_hstretch: dirs
	@echo "=== build tb_gs_lpddr_scanout_lb_hstretch ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_hstretch.vvp \
	    -s tb_gs_lpddr_scanout_lb_hstretch \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb_hstretch.sv
	@echo "=== run tb_gs_lpddr_scanout_lb_hstretch ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_hstretch.vvp

tb_gs_lpddr_scanout_lb_binomial: dirs
	@echo "=== build tb_gs_lpddr_scanout_lb_binomial ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_binomial.vvp \
	    -s tb_gs_lpddr_scanout_lb_binomial \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_scanout_lb_binomial.sv
	@echo "=== run tb_gs_lpddr_scanout_lb_binomial ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_scanout_lb_binomial.vvp

tb_gs_scanout_binomial_lookahead: dirs
	@echo "=== build tb_gs_scanout_binomial_lookahead ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_binomial_lookahead.vvp \
	    -s tb_gs_scanout_binomial_lookahead \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_binomial_lookahead.sv
	@echo "=== run tb_gs_scanout_binomial_lookahead ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_binomial_lookahead.vvp

tb_gs_scanout_diag: dirs
	@echo "=== build tb_gs_scanout_diag ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_diag.vvp \
	    -s tb_gs_scanout_diag \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_diag.sv
	@echo "=== run tb_gs_scanout_diag ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_diag.vvp

tb_gs_scanout_cdc_qual: dirs
	@echo "=== build tb_gs_scanout_cdc_qual ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_cdc_qual.vvp \
	    -s tb_gs_scanout_cdc_qual \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_cdc_qual.sv
	@echo "=== run tb_gs_scanout_cdc_qual ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_cdc_qual.vvp

tb_gs_scanout_restart: dirs
	@echo "=== build tb_gs_scanout_restart ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_restart.vvp \
	    -s tb_gs_scanout_restart \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_restart.sv
	@echo "=== run tb_gs_scanout_restart ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_restart.vvp

tb_gs_texture_cache: dirs
	@echo "=== build tb_gs_texture_cache ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_texture_cache.vvp \
	    -s tb_gs_texture_cache \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_texture_cache.sv
	@echo "=== run tb_gs_texture_cache ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_texture_cache.vvp

tb_gs_lpddr_wr_probe: dirs
	@echo "=== build tb_gs_lpddr_wr_probe ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_wr_probe.vvp \
	    -s tb_gs_lpddr_wr_probe \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_wr_probe.sv
	@echo "=== run tb_gs_lpddr_wr_probe ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_wr_probe.vvp

tb_gs_lpddr_wr_arb: dirs
	@echo "=== build tb_gs_lpddr_wr_arb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_lpddr_wr_arb.vvp \
	    -s tb_gs_lpddr_wr_arb \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_lpddr_wr_arb.sv
	@echo "=== run tb_gs_lpddr_wr_arb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_lpddr_wr_arb.vvp

tb_gs_tile_reload: dirs
	@echo "=== build tb_gs_tile_reload ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_tile_reload.vvp \
	    -s tb_gs_tile_reload \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tile_reload.sv
	@echo "=== run tb_gs_tile_reload ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_reload.vvp

tb_gs_tile_reload_grid: dirs
	@echo "=== build tb_gs_tile_reload_grid ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_tile_reload_grid.vvp \
	    -s tb_gs_tile_reload_grid \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tile_reload_grid.sv
	@echo "=== run tb_gs_tile_reload_grid ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_reload_grid.vvp

tb_gs_z_flush_writer: dirs
	@echo "=== build tb_gs_z_flush_writer ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_z_flush_writer.vvp \
	    -s tb_gs_z_flush_writer \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_z_flush_writer.sv
	@echo "=== run tb_gs_z_flush_writer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_z_flush_writer.vvp

tb_gs_zbuffer: dirs
	@echo "=== build tb_gs_zbuffer ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_zbuffer.vvp \
	    -s tb_gs_zbuffer \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_zbuffer.sv
	@echo "=== run tb_gs_zbuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_zbuffer.vvp

tb_top_psmct32_zbuffer_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_zbuffer_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_zbuffer.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_zbuffer.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_zbuffer_demo.vvp \
	    -s tb_top_psmct32_zbuffer_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_zbuffer_demo.sv
	@echo "=== run tb_top_psmct32_zbuffer_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_zbuffer_demo.vvp

# Brick 3 — focused TRI affine interpolation (coverage + color + depth).
tb_gs_tri_interp: dirs
	@echo "=== build tb_gs_tri_interp ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_tri_interp.vvp \
	    -s tb_gs_tri_interp \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tri_interp.sv
	@echo "=== run tb_gs_tri_interp ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tri_interp.vvp

# GS per-vertex FOG — focused white-box fog blend + interpolation + FGE=0 gate.
tb_gs_fog: dirs
	@echo "=== build tb_gs_fog ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_fog.vvp \
	    -s tb_gs_fog \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_fog.sv
	@echo "=== run tb_gs_fog ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_fog.vvp

# GS per-vertex FOG on the PERSPECTIVE-textured emit (persp_emit5), PERSPECTIVE_CORRECT=1.
tb_gs_fog_persp: dirs
	@echo "=== build tb_gs_fog_persp ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_fog_persp.vvp \
	    -s tb_gs_fog_persp \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_fog_persp.sv
	@echo "=== run tb_gs_fog_persp ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_fog_persp.vvp

# GS per-vertex FOG end-to-end: staging PRIM.FGE -> feeder XYZF2 -> gs_stub fog.
tb_gs_feeder_fog_e2e: dirs
	@echo "=== build tb_gs_feeder_fog_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_feeder_fog_e2e.vvp \
	    -s tb_gs_feeder_fog_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_feeder_fog_e2e.sv
	@echo "=== run tb_gs_feeder_fog_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_feeder_fog_e2e.vvp

# GS per-vertex FOG compile-OUT: gs_stub #(.FOG_ENABLE(0)) prunes fog -> raw color.
tb_gs_fog_disabled: dirs
	@echo "=== build tb_gs_fog_disabled ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_fog_disabled.vvp \
	    -s tb_gs_fog_disabled \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_fog_disabled.sv
	@echo "=== run tb_gs_fog_disabled ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_fog_disabled.vvp

# Brick 3 — top-level non-axis-aligned triangle demo on the BRAM board path.
tb_top_psmct32_triangle_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_triangle_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_triangle.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_triangle.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_triangle_demo.vvp \
	    -s tb_top_psmct32_triangle_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_triangle_demo.sv
	@echo "=== run tb_top_psmct32_triangle_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_triangle_demo.vvp

tb_top_psmct32_alpha_blend_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_alpha_blend_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_alpha.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_alpha.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_alpha_blend_demo.vvp \
	    -s tb_top_psmct32_alpha_blend_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_alpha_blend_demo.sv
	@echo "=== run tb_top_psmct32_alpha_blend_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_alpha_blend_demo.vvp

# Ch344 — TEXTURED + source-over alpha SPRITE demo on the bram board variant (SPRITE_TEX_ALPHA=1),
# registered-read2 integration. 8x8 alpha-checker texture blended over a blue BG.
tb_top_psmct32_texalpha_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_texalpha_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_texalpha.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_texalpha.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_texalpha_demo.vvp \
	    -s tb_top_psmct32_texalpha_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_texalpha_demo.sv
	@echo "=== run tb_top_psmct32_texalpha_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_texalpha_demo.vvp

tb_gs_raster_psmt4: dirs
	@echo "=== build tb_gs_raster_psmt4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_psmt4.vvp \
	    -s tb_gs_raster_psmt4 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_psmt4.sv
	@echo "=== run tb_gs_raster_psmt4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_psmt4.vvp

tb_gs_demo_psmt4_e2e: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e.vvp \
	    -s tb_gs_demo_psmt4_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e.sv
	@echo "=== run tb_gs_demo_psmt4_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e.vvp

tb_gs_demo_psmt4_e2e_packed: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e_packed ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_packed.vvp \
	    -s tb_gs_demo_psmt4_e2e_packed \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_packed.sv
	@echo "=== run tb_gs_demo_psmt4_e2e_packed ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_packed.vvp

tb_gs_demo_psmt4_e2e_dmac: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e_dmac ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_dmac.vvp \
	    -s tb_gs_demo_psmt4_e2e_dmac \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_dmac.sv
	@echo "=== run tb_gs_demo_psmt4_e2e_dmac ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_dmac.vvp

tb_gs_demo_psmt4_e2e_trxdir: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e_trxdir ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_trxdir.vvp \
	    -s tb_gs_demo_psmt4_e2e_trxdir \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_trxdir.sv
	@echo "=== run tb_gs_demo_psmt4_e2e_trxdir ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_trxdir.vvp

tb_gs_demo_psmt4_e2e_eemmio: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e_eemmio ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemmio.vvp \
	    -s tb_gs_demo_psmt4_e2e_eemmio \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_eemmio.sv
	@echo "=== run tb_gs_demo_psmt4_e2e_eemmio ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemmio.vvp

tb_gs_demo_psmt4_e2e_eemap: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e_eemap ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemap.vvp \
	    -s tb_gs_demo_psmt4_e2e_eemap \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_eemap.sv
	@echo "=== run tb_gs_demo_psmt4_e2e_eemap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_eemap.vvp

tb_gs_demo_psmt4_e2e_ee_program: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e_ee_program ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_program.vvp \
	    -s tb_gs_demo_psmt4_e2e_ee_program \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_ee_program.sv
	@echo "=== run tb_gs_demo_psmt4_e2e_ee_program ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_program.vvp

tb_gs_demo_psmt4_e2e_ee_full_bootlet: dirs
	@echo "=== build tb_gs_demo_psmt4_e2e_ee_full_bootlet ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_full_bootlet.vvp \
	    -s tb_gs_demo_psmt4_e2e_ee_full_bootlet \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_e2e_ee_full_bootlet.sv
	@echo "=== run tb_gs_demo_psmt4_e2e_ee_full_bootlet ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_e2e_ee_full_bootlet.vvp

tb_ee_ram_cpu_dmac_contention: dirs
	@echo "=== build tb_ee_ram_cpu_dmac_contention ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_ram_cpu_dmac_contention.vvp \
	    -s tb_ee_ram_cpu_dmac_contention \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_ram_cpu_dmac_contention.sv
	@echo "=== run tb_ee_ram_cpu_dmac_contention ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_ram_cpu_dmac_contention.vvp

tb_gs_image_xfer_psmct16: dirs
	@echo "=== build tb_gs_image_xfer_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_image_xfer_psmct16.vvp \
	    -s tb_gs_image_xfer_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_psmct16.sv
	@echo "=== run tb_gs_image_xfer_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_psmct16.vvp

tb_gs_image_xfer_psmt8: dirs
	@echo "=== build tb_gs_image_xfer_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_image_xfer_psmt8.vvp \
	    -s tb_gs_image_xfer_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_psmt8.sv
	@echo "=== run tb_gs_image_xfer_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_psmt8.vvp

tb_gs_image_xfer_psmt4: dirs
	@echo "=== build tb_gs_image_xfer_psmt4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_image_xfer_psmt4.vvp \
	    -s tb_gs_image_xfer_psmt4 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_psmt4.sv
	@echo "=== run tb_gs_image_xfer_psmt4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_psmt4.vvp

tb_gs_swizzle_psmct32: dirs
	@echo "=== build tb_gs_swizzle_psmct32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_swizzle_psmct32.vvp \
	    -s tb_gs_swizzle_psmct32 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmct32.sv
	@echo "=== run tb_gs_swizzle_psmct32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmct32.vvp

tb_gs_swizzle_psmct16: dirs
	@echo "=== build tb_gs_swizzle_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_swizzle_psmct16.vvp \
	    -s tb_gs_swizzle_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmct16.sv
	@echo "=== run tb_gs_swizzle_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmct16.vvp

tb_gs_swizzle_psmt8: dirs
	@echo "=== build tb_gs_swizzle_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_swizzle_psmt8.vvp \
	    -s tb_gs_swizzle_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmt8.sv
	@echo "=== run tb_gs_swizzle_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmt8.vvp

tb_gs_swizzle_psmt4: dirs
	@echo "=== build tb_gs_swizzle_psmt4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_swizzle_psmt4.vvp \
	    -s tb_gs_swizzle_psmt4 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_swizzle_psmt4.sv
	@echo "=== run tb_gs_swizzle_psmt4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_swizzle_psmt4.vvp

tb_gs_scanout_swizzle_psmt4: dirs
	@echo "=== build tb_gs_scanout_swizzle_psmt4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt4.vvp \
	    -s tb_gs_scanout_swizzle_psmt4 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmt4.sv
	@echo "=== run tb_gs_scanout_swizzle_psmt4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt4.vvp

tb_gs_image_xfer_swizzle_psmt4: dirs
	@echo "=== build tb_gs_image_xfer_swizzle_psmt4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt4.vvp \
	    -s tb_gs_image_xfer_swizzle_psmt4 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmt4.sv
	@echo "=== run tb_gs_image_xfer_swizzle_psmt4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt4.vvp

tb_gs_raster_swizzle_psmt4: dirs
	@echo "=== build tb_gs_raster_swizzle_psmt4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_swizzle_psmt4.vvp \
	    -s tb_gs_raster_swizzle_psmt4 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmt4.sv
	@echo "=== run tb_gs_raster_swizzle_psmt4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmt4.vvp

tb_gs_demo_psmt4_swizzle_e2e: dirs
	@echo "=== build tb_gs_demo_psmt4_swizzle_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_e2e.vvp \
	    -s tb_gs_demo_psmt4_swizzle_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_swizzle_e2e.sv
	@echo "=== run tb_gs_demo_psmt4_swizzle_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_e2e.vvp

tb_gs_demo_psmt4_swizzle_trxdir_e2e: dirs
	@echo "=== build tb_gs_demo_psmt4_swizzle_trxdir_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_trxdir_e2e.vvp \
	    -s tb_gs_demo_psmt4_swizzle_trxdir_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt4_swizzle_trxdir_e2e.sv
	@echo "=== run tb_gs_demo_psmt4_swizzle_trxdir_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt4_swizzle_trxdir_e2e.vvp

tb_top_psmct32_raster_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_ch146.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_ch146.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo.vvp \
	    -s tb_top_psmct32_raster_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo.sv
	@echo "=== run tb_top_psmct32_raster_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo.vvp

# Brick 1 — TOP-LEVEL textured-sprite demo. Drives top_psmct32_raster_demo
# (PSMCT32_SWIZZLE=0) with the textured fixture (BITBLT texture upload +
# textured SPRITE + flat control sprite) and verifies the texture renders
# in the PCRTC scanout — i.e. a board load would SHOW a texture.
tb_top_psmct32_textured_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_textured_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_textured.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_textured.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_textured_demo.vvp \
	    -s tb_top_psmct32_textured_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_textured_demo.sv
	@echo "=== run tb_top_psmct32_textured_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_textured_demo.vvp

# Ch171 — this TB exercises the legacy 16x8 Ch146 fixture (the
# pre-Ch171 pattern) because it does per-pixel VRAM + scanout
# assertions that don't survive scaling to 320x240. Synth/board
# uses bios.mem/payload.mem (the Ch171 320x240 pattern) via the
# QSF macro.
tb_top_psmct32_raster_demo_bram: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_ch146.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_ch146.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram.vvp \
	    -s tb_top_psmct32_raster_demo_bram \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram.vvp

# Ch295 — TEXTURED-sprite demo on the BRAM BOARD VARIANT
# (top_psmct32_raster_demo_bram). Companion to tb_top_psmct32_textured_demo
# (vram_stub variant); proves the textured SPRITE path renders through the
# BRAM VRAM the de25_nano board top actually instantiates, despite
# vram_bram_stub.read2's 1-cycle registered read latency (gs_stub
# TEX_RD_REGISTERED=1). Built with the textured fixture + PSMCT32_SWIZZLE=0.
tb_top_psmct32_raster_demo_bram_textured: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_textured ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_textured.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_textured.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_textured.vvp \
	    -s tb_top_psmct32_raster_demo_bram_textured \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_textured.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_textured ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_textured.vvp

# Ch296 — PSMT8 INDEXED-TEXTURE + CLUT demo on the BRAM board variant.
# Proves the palettized texture path (texel index fetch -> clut_stub
# lookup -> PSMCT32 color) renders through the BRAM VRAM + the CLUT
# loader the board top instantiates. Uses the clut fixture
# (bios_clut.mem / payload_clut.mem) + PSMCT32_SWIZZLE=0.
tb_top_psmct32_raster_demo_bram_clut: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_clut.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_clut.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut.vvp \
	    -s tb_top_psmct32_raster_demo_bram_clut \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_clut.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut.vvp

# Ch347 — AUTHENTIC SH3 64x64-crop PSMT8+CLUT board integration (LOCAL assets; NOT in the regression).
# Fixtures from tools/gs_extract_sh3_clut.py + tools/gs_make_sh3_fixture.py (needs the local SH3 dump).
tb_top_psmct32_sh3_clut_demo: dirs
	@echo "=== build tb_top_psmct32_sh3_clut_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_clut.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_clut.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_clut_demo.vvp \
	    -s tb_top_psmct32_sh3_clut_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_clut_demo.sv
	@echo "=== run tb_top_psmct32_sh3_clut_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_clut_demo.vvp

# Ch297 — PSMT4 INDEXED-TEXTURE + CLUT demo on the BRAM board variant.
# Proves the 4-bit palettized texture path (nibble-select index fetch ->
# clut_stub lookup -> PSMCT32 color) renders through the BRAM VRAM + CLUT
# loader the board top instantiates. Uses the clut4 fixture
# (bios_clut4.mem / payload_clut4.mem) + PSMCT32_SWIZZLE=0.
tb_top_psmct32_raster_demo_bram_clut4: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_clut4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_clut4.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_clut4.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut4.vvp \
	    -s tb_top_psmct32_raster_demo_bram_clut4 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_clut4.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_clut4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_clut4.vvp

# Ch298 — SWIZZLED PSMT4 INDEXED-TEXTURE + CLUT demo on the BRAM board variant.
# Built with PSMT4_SWIZZLE=1 so BOTH the gif_image_xfer texture UPLOAD and the
# gs_texture_unit SAMPLE use the real PS2 PSMT4 block layout. The 64x32 texture
# / 16x32 sampled sprite crosses the 16-px block-ROW boundary, so the same VRAM
# bytes read linearly would scramble. Uses the swz4 fixture (bios_swz4.mem /
# payload_swz4.mem).
tb_top_psmct32_raster_demo_bram_swz4: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_swz4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_swz4.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_swz4.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz4.vvp \
	    -s tb_top_psmct32_raster_demo_bram_swz4 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_swz4.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_swz4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz4.vvp

tb_top_psmct32_raster_demo_bram_swz8: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_swz8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_swz8.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_swz8.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz8.vvp \
	    -s tb_top_psmct32_raster_demo_bram_swz8 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_swz8.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_swz8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz8.vvp

tb_top_psmct32_raster_demo_bram_swz32: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_swz32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_swz32.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_swz32.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz32.vvp \
	    -s tb_top_psmct32_raster_demo_bram_swz32 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_swz32.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_swz32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_swz32.vvp

tb_top_psmct32_perspective_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_perspective_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_persp.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_persp.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_perspective_demo.vvp \
	    -s tb_top_psmct32_perspective_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_perspective_demo.sv
	@echo "=== run tb_top_psmct32_perspective_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_perspective_demo.vvp

tb_top_psmct32_persp_floor_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_persp_floor_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_persp_floor.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_persp_floor.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_persp_floor_demo.vvp \
	    -s tb_top_psmct32_persp_floor_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_persp_floor_demo.sv
	@echo "=== run tb_top_psmct32_persp_floor_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_persp_floor_demo.vvp

tb_top_psmct32_combined_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_combined_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_combined.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_combined.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_combined_demo.vvp \
	    -s tb_top_psmct32_combined_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_combined_demo.sv
	@echo "=== run tb_top_psmct32_combined_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_combined_demo.vvp

tb_top_psmct32_tile_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_demo.vvp \
	    -s tb_top_psmct32_tile_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_demo.sv
	@echo "=== run tb_top_psmct32_tile_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_demo.vvp

tb_gs_tile_zflush: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_gs_tile_zflush ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile.mem"' \
	    -o $(BUILD_DIR)/tb_gs_tile_zflush.vvp \
	    -s tb_gs_tile_zflush \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_zflush.sv
	@echo "=== run tb_gs_tile_zflush ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_zflush.vvp

tb_gs_tile_spill_reload: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_gs_tile_spill_reload ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill.mem"' \
	    -o $(BUILD_DIR)/tb_gs_tile_spill_reload.vvp \
	    -s tb_gs_tile_spill_reload \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_reload.sv
	@echo "=== run tb_gs_tile_spill_reload ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_reload.vvp

tb_gs_tile_spill_lpddr: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_gs_tile_spill_lpddr ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill.mem"' \
	    -o $(BUILD_DIR)/tb_gs_tile_spill_lpddr.vvp \
	    -s tb_gs_tile_spill_lpddr \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_lpddr.sv
	@echo "=== run tb_gs_tile_spill_lpddr ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_lpddr.vvp

tb_gs_tile_spill_grid_lpddr: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_gs_tile_spill_grid_lpddr ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill4x4.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill4x4.mem"' \
	    -o $(BUILD_DIR)/tb_gs_tile_spill_grid_lpddr.vvp \
	    -s tb_gs_tile_spill_grid_lpddr \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_grid_lpddr.sv
	@echo "=== run tb_gs_tile_spill_grid_lpddr ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_grid_lpddr.vvp

tb_gs_tile_spill_grid8x8_lpddr: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_gs_tile_spill_grid8x8_lpddr ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill8x8.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill8x8.mem"' \
	    -o $(BUILD_DIR)/tb_gs_tile_spill_grid8x8_lpddr.vvp \
	    -s tb_gs_tile_spill_grid8x8_lpddr \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_grid8x8_lpddr.sv
	@echo "=== run tb_gs_tile_spill_grid8x8_lpddr ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_grid8x8_lpddr.vvp

tb_gs_tile_spill_lpddr_neg: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_gs_tile_spill_lpddr_neg ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_spill.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_spill.mem"' \
	    -o $(BUILD_DIR)/tb_gs_tile_spill_lpddr_neg.vvp \
	    -s tb_gs_tile_spill_lpddr_neg \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_gs_tile_spill_lpddr_neg.sv
	@echo "=== run tb_gs_tile_spill_lpddr_neg ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tile_spill_lpddr_neg.vvp

tb_top_psmct32_tile2x2_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile2x2_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile2x2.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile2x2.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile2x2_demo.vvp \
	    -s tb_top_psmct32_tile2x2_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile2x2_demo.sv
	@echo "=== run tb_top_psmct32_tile2x2_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile2x2_demo.vvp

tb_top_psmct32_tile_multiprim_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_multiprim_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_multiprim.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_multiprim.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_multiprim_demo.vvp \
	    -s tb_top_psmct32_tile_multiprim_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_multiprim_demo.sv
	@echo "=== run tb_top_psmct32_tile_multiprim_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_multiprim_demo.vvp

tb_top_psmct32_tile_scissor_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_scissor_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_scissor.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_scissor.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_scissor_demo.vvp \
	    -s tb_top_psmct32_tile_scissor_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_scissor_demo.sv
	@echo "=== run tb_top_psmct32_tile_scissor_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_scissor_demo.vvp

tb_top_psmct32_tile_wrap_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_wrap_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_wrap.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_wrap.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_wrap_demo.vvp \
	    -s tb_top_psmct32_tile_wrap_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_wrap_demo.sv
	@echo "=== run tb_top_psmct32_tile_wrap_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_wrap_demo.vvp

tb_top_psmct32_tile_psmct16_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_psmct16_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_psmct16.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_psmct16.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_psmct16_demo.vvp \
	    -s tb_top_psmct32_tile_psmct16_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_psmct16_demo.sv
	@echo "=== run tb_top_psmct32_tile_psmct16_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_psmct16_demo.vvp

tb_top_psmct32_tile_alpha_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_alpha_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_alpha.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_alpha.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_alpha_demo.vvp \
	    -s tb_top_psmct32_tile_alpha_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_alpha_demo.sv
	@echo "=== run tb_top_psmct32_tile_alpha_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_alpha_demo.vvp

tb_top_psmct32_tile_bilinear_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_bilinear_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_bilinear.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_bilinear.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_bilinear_demo.vvp \
	    -s tb_top_psmct32_tile_bilinear_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_bilinear_demo.sv
	@echo "=== run tb_top_psmct32_tile_bilinear_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_bilinear_demo.vvp

tb_top_psmct32_tile_palbilinear_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_palbilinear_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_palbilinear.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_palbilinear.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_palbilinear_demo.vvp \
	    -s tb_top_psmct32_tile_palbilinear_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_palbilinear_demo.sv
	@echo "=== run tb_top_psmct32_tile_palbilinear_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_palbilinear_demo.vvp

tb_top_psmct32_feeder_equiv_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_equiv_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_STG_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_equiv_demo.vvp \
	    -s tb_top_psmct32_feeder_equiv_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_equiv_demo.sv
	@echo "=== run tb_top_psmct32_feeder_equiv_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_equiv_demo.vvp

tb_top_psmct32_feeder_runtime_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_runtime_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_STG_A_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
	    -DFEEDER_STG_B_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4_B.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_runtime_demo.vvp \
	    -s tb_top_psmct32_feeder_runtime_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_runtime_demo.sv
	@echo "=== run tb_top_psmct32_feeder_runtime_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_runtime_demo.vvp

tb_top_psmct32_feeder_bridge_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_bridge_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_STG_A_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
	    -DFEEDER_STG_B_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4_B.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_bridge_demo.vvp \
	    -s tb_top_psmct32_feeder_bridge_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_bridge_demo.sv
	@echo "=== run tb_top_psmct32_feeder_bridge_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_bridge_demo.vvp

tb_top_psmct32_feeder_scenes_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_scenes_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_SCENE_C1_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_c1.mem"' \
	    -DFEEDER_SCENE_C2_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_c2.mem"' \
	    -DFEEDER_SCENE_C3_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_c3.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_scenes_demo.vvp \
	    -s tb_top_psmct32_feeder_scenes_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_scenes_demo.sv
	@echo "=== run tb_top_psmct32_feeder_scenes_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_scenes_demo.vvp

tb_top_psmct32_feeder_shapes_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_shapes_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_SHAPE_TRI_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_shape_tri.mem"' \
	    -DFEEDER_SHAPE_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_shape_rect.mem"' \
	    -DFEEDER_SHAPE_MIXED_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_shape_mixed.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_shapes_demo.vvp \
	    -s tb_top_psmct32_feeder_shapes_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_shapes_demo.sv
	@echo "=== run tb_top_psmct32_feeder_shapes_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_shapes_demo.vvp

tb_top_psmct32_feeder_colors_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_colors_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_COLOR_TRI_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_color_tri.mem"' \
	    -DFEEDER_COLOR_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_color_rect.mem"' \
	    -DFEEDER_COLOR_MIX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_color_mix.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_colors_demo.vvp \
	    -s tb_top_psmct32_feeder_colors_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_colors_demo.sv
	@echo "=== run tb_top_psmct32_feeder_colors_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_colors_demo.vvp

tb_top_psmct32_feeder_native_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_native_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_NATIVE_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_native_rect.mem"' \
	    -DFEEDER_NATIVE_MIX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_native_mix.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_native_demo.vvp \
	    -s tb_top_psmct32_feeder_native_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_native_demo.sv
	@echo "=== run tb_top_psmct32_feeder_native_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_native_demo.vvp

tb_top_psmct32_feeder_gouraud_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_gouraud_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_GOURAUD_TRI_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_gouraud_tri.mem"' \
	    -DFEEDER_GOURAUD_RECT_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_gouraud_rect.mem"' \
	    -DFEEDER_GOURAUD_MIX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_gouraud_mix.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_gouraud_demo.vvp \
	    -s tb_top_psmct32_feeder_gouraud_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_gouraud_demo.sv
	@echo "=== run tb_top_psmct32_feeder_gouraud_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_gouraud_demo.vvp

tb_top_psmct32_feeder_accum_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_accum_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_ACCUM_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_accum.mem"' \
	    -DFEEDER_LISTA_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_stg_cap4.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_accum_demo.vvp \
	    -s tb_top_psmct32_feeder_accum_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_accum_demo.sv
	@echo "=== run tb_top_psmct32_feeder_accum_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_accum_demo.vvp

tb_top_psmct32_feeder_scene_retrigger_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_scene_retrigger_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_SCENE_A_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_a.mem"' \
	    -DFEEDER_SCENE_B_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_scene_b.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_scene_retrigger_demo.vvp \
	    -s tb_top_psmct32_feeder_scene_retrigger_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_scene_retrigger_demo.sv
	@echo "=== run tb_top_psmct32_feeder_scene_retrigger_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_scene_retrigger_demo.vvp

tb_top_psmct32_feeder_zpersist_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_zpersist_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_ZPN_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_zpersist_near_first.mem"' \
	    -DFEEDER_ZPF_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_zpersist_far_first.mem"' \
	    -DFEEDER_ZPG_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_zpersist_grad.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_zpersist_demo.vvp \
	    -s tb_top_psmct32_feeder_zpersist_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_zpersist_demo.sv
	@echo "=== run tb_top_psmct32_feeder_zpersist_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_zpersist_demo.vvp

tb_top_psmct32_feeder_persp_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_persp_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_PERSP_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_persp.mem"' \
	    -DFEEDER_PERSP_TEX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_persp_tex.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_persp_demo.vvp \
	    -s tb_top_psmct32_feeder_persp_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_persp_demo.sv
	@echo "=== run tb_top_psmct32_feeder_persp_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_persp_demo.vvp

# Ch357 — BOARD gradient-path equivalence: same perspective scene + exact per-pixel oracle, but the bram-top runs the
# BOARD config (GRAD_SEQ_DIVIDER=0, GRAD_DIV_CYCLES=5 -> the registered-numerator-select + 5-cycle-settle FSM). Passing
# the SAME interior_ok==interior_total exact match proves the new FSM renders the 20-step perspective gradients
# bit-identically to the default combinational path (the numerator-register fix is value-transparent, +1 cycle/step).
tb_top_psmct32_feeder_persp_boardpath: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_persp_boardpath (GRAD_SEQ_DIVIDER=0/CYCLES=5) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DGRAD_BOARDPATH \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_feeder_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_feeder_setup.mem"' \
	    -DFEEDER_PERSP_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_persp.mem"' \
	    -DFEEDER_PERSP_TEX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_persp_tex.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_persp_boardpath.vvp \
	    -s tb_top_psmct32_feeder_persp_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_persp_demo.sv
	@echo "=== run tb_top_psmct32_feeder_persp_boardpath ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_persp_boardpath.vvp

# Ch348 — AUTHENTIC SH3 PSMT8+CLUT through the perspective feeder path (LOCAL assets; NOT in the regression).
# Fixtures: tools/gs_extract_sh3_clut.py + tools/gs_make_sh3_persp_fixture.py (needs the local SH3 dump).
tb_top_psmct32_sh3_persp_demo: dirs
	@echo "=== build tb_top_psmct32_sh3_persp_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_persp.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_persp.mem"' \
	    -DFEEDER_SH3_PERSP_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sh3_persp.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_persp_demo.vvp \
	    -s tb_top_psmct32_sh3_persp_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_persp_demo.sv
	@echo "=== run tb_top_psmct32_sh3_persp_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_persp_demo.vvp

tb_top_psmct32_sh3_real_draw_demo: dirs
	@echo "=== build tb_top_psmct32_sh3_real_draw_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_real.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_real.mem"' \
	    -DFEEDER_SH3_REAL_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sh3_real.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_real_draw_demo.vvp \
	    -s tb_top_psmct32_sh3_real_draw_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_real_draw_demo.sv
	@echo "=== run tb_top_psmct32_sh3_real_draw_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_real_draw_demo.vvp
	@echo "=== emit current RTL framebuffer PNG (Ch352 closeout) ==="
	@python3 $(SIM_DIR)/../tools/gs_fb_to_png.py \
	    $(SIM_DIR)/data/top_psmct32_raster_demo/sh3_real_fb_out.mem \
	    $(SIM_DIR)/data/top_psmct32_raster_demo/sh3_real_fb_rtl.png 256 120 3 || true

# Ch353 Brick 1c — LPDDR-only direct PSMCT32 framebuffer proof (FB_LPDDR_ONLY + widened writer).
tb_top_psmct32_sh3_lpddr_fb: dirs
	@echo "=== build tb_top_psmct32_sh3_lpddr_fb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_real.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_real.mem"' \
	    -DFEEDER_SH3_REAL_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sh3_real.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_lpddr_fb.vvp \
	    -s tb_top_psmct32_sh3_lpddr_fb \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_lpddr_fb.sv
	@echo "=== run tb_top_psmct32_sh3_lpddr_fb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_lpddr_fb.vvp

# Ch353 Brick 1b — same proof at the FULL 256x334 frame (--full-frame fixture: sh3_full_* + bios/payload/feeder _full).
tb_top_psmct32_sh3_lpddr_fb_full: dirs
	@echo "=== build tb_top_psmct32_sh3_lpddr_fb_full (FULL FRAME 256x334) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DSH3_FULL_FRAME \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_full.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_full.mem"' \
	    -DFEEDER_SH3_REAL_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sh3_full.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_lpddr_fb_full.vvp \
	    -s tb_top_psmct32_sh3_lpddr_fb \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_lpddr_fb.sv
	@echo "=== run tb_top_psmct32_sh3_lpddr_fb_full ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_lpddr_fb_full.vvp

# Ch353 Brick 3 — LPDDR-only FB HOST-START SEQUENCE proof (FEEDER_AUTOSTART=0 + render-epoch EOF + frame_drained
# hard gate + full write->scanout loop). The fit gate: no board fit until this passes. Full-frame fixtures.
tb_top_psmct32_sh3_lpddr_fb_seq: dirs
	@echo "=== build tb_top_psmct32_sh3_lpddr_fb_seq (Brick 3 SEQUENCE, FULL FRAME 256x334) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_full.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_full.mem"' \
	    -DFEEDER_SH3_REAL_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sh3_full.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_lpddr_fb_seq.vvp \
	    -s tb_top_psmct32_sh3_lpddr_fb_seq \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_lpddr_fb_seq.sv
	@echo "=== run tb_top_psmct32_sh3_lpddr_fb_seq ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_lpddr_fb_seq.vvp

# Ch354 Brick 1 — MULTI-DRAW accumulation into the LPDDR framebuffer (3 SH3 draws sharing one texture -> one FB).
# FEEDER_STG_WORDS=2048; proves records_emitted==NTRIS, one frame_drained after all batches, overlap oracle. LOCAL fixtures.
tb_top_psmct32_sh3_multidraw: dirs
	@echo "=== build tb_top_psmct32_sh3_multidraw (Ch354 multi-draw, FB 256x338, STG 2048) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_multi.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_multi.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_multidraw.vvp \
	    -s tb_top_psmct32_sh3_multidraw \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_multidraw.sv
	@echo "=== run tb_top_psmct32_sh3_multidraw ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_multidraw.vvp

# Ch355 Brick 1 — MULTI-TEXTURE composition: 2 SH3 draws w/ DIFFERENT TEX0/CLUT accumulate into one 320x381 LPDDR FB
# via scene-level texture rebind (2 cache fills/CRCs) + staged-list retriggering, no stale-drain race. LOCAL fixtures.
tb_top_psmct32_sh3_multitex: dirs
	@echo "=== build tb_top_psmct32_sh3_multitex (Ch355 multi-texture, FB 320x381) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_mt.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_mt.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_multitex.vvp \
	    -s tb_top_psmct32_sh3_multitex \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_multitex.sv
	@echo "=== run tb_top_psmct32_sh3_multitex ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_multitex.vvp

# Ch356 — N-TEXTURE SCHEDULER (data-driven epoch descriptors, FB 384x381). LOCAL fixtures via
# gs_make_sh3_scheduler_fixture.py --emit; bootlet preloads all N relocated CLUTs; lists streamed via the write port.
tb_top_psmct32_sh3_sched: dirs
	@echo "=== build tb_top_psmct32_sh3_sched (Ch356 N-texture scheduler, FB 384x381) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_sched.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_sched.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_sched.vvp \
	    -s tb_top_psmct32_sh3_sched \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_sched.sv
	@echo "=== run tb_top_psmct32_sh3_sched ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched.vvp

# Ch357 — scheduler with AUTHENTIC-Z fixtures (sh3_zsched primary [8634,12757,145742]); captures the raster fragment
# stream {epoch,x,y,persp_z,color} -> zsched_frags.txt for external persp_z5 verification vs the clamp16 oracle.
tb_top_psmct32_sh3_zsched: dirs sh3_zsched_fixture
	@echo "=== build tb_top_psmct32_sh3_zsched (Ch357 authentic-Z capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsched.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsched.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zsched.vvp \
	    -s tb_top_psmct32_sh3_zsched \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zsched.sv
	@echo "=== run tb_top_psmct32_sh3_zsched ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zsched.vvp

# Ch357 — persistent-Z ROP acceptance gate (option A): replay the captured raster fragment trace (zsched_frags.txt, produced
# by tb_top_psmct32_sh3_zsched) through gs_lpddr_zc_emit + an independent clamp16 scoreboard. Run the capture first.
tb_top_psmct32_sh3_zrop: tb_top_psmct32_sh3_zsched
	@echo "=== build tb_top_psmct32_sh3_zrop (Ch357 ROP scoreboard) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zrop.vvp \
	    -s tb_top_psmct32_sh3_zrop \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zrop.sv
	@echo "=== run tb_top_psmct32_sh3_zrop ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zrop.vvp

# Ch357 — REAL-RASTER persistent-Z board integration (Codex pre-fit gate): drive the REAL demo (feeder+raster,
# authz sh3_zsched scene) -> gs_lpddr_zc_emit -> REAL de25 arbiters (wr s0=color/s2=Z, rd s3=Z) -> one shared LPDDR
# with random backpressure. Catches request-FIFO fragment DROPS the handshake-fed zarb trace could not.
tb_top_psmct32_sh3_zint: dirs sh3_zsched_fixture
	@echo "=== build tb_top_psmct32_sh3_zint (Ch357 real-raster Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsched.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsched.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint.vvp \
	    -s tb_top_psmct32_sh3_zint \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint.sv
	@echo "=== run tb_top_psmct32_sh3_zint ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint.vvp

sh3_zsched_board_compare: tb_top_psmct32_sh3_zsched tb_top_psmct32_sh3_zint
	@test -f $(SH3_ZSCHED_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSCHED_BOARD_FB)"; \
	     echo "Run the board with --dump-fb and copy sh3_zsched_board_fb.mem here first."; exit 1)
	@echo "=== dump zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint.vvp +FBDUMP=$(SH3_ZSCHED_ZINT_FB)
	@echo "=== compare board framebuffer vs zint sim framebuffer ==="
	@sha256sum $(SH3_ZSCHED_BOARD_FB) $(SH3_ZSCHED_ZINT_FB)
	@cmp -s $(SH3_ZSCHED_BOARD_FB) $(SH3_ZSCHED_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to zint sim" || \
	    (echo "FAIL: board framebuffer differs from zint sim"; cmp -l $(SH3_ZSCHED_BOARD_FB) $(SH3_ZSCHED_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSCHED_BOARD_FB) \
	    --owner replay-color --frags $(TRACE_DIR)/zsched_frags.txt

# Ch358 — NATIVE 640x480 persistent-Z capture: the strong-reject scene at authentic screen coords through the REAL
# raster; captures the fragment stream {epoch,x,y,persp_z,color} -> zs640_frags.txt (replay-color board check input).
tb_top_psmct32_sh3_zs640_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640_cap (Ch358 native-640 authentic-Z capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640_cap.vvp

# Ch358 — real-raster persistent-Z integration at NATIVE 640x480 (the de25 GS_SH3_LPDDR_FB_Z+_640 path): REAL demo ->
# gs_lpddr_zc_emit -> REAL de25 arbiters -> one shared LPDDR w/ random backpressure + clamp16 scoreboard. Drop gate.
tb_top_psmct32_sh3_zint640: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640 (Ch358 native-640 real-raster Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640.vvp \
	    -s tb_top_psmct32_sh3_zint640 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640.sv
	@echo "=== run tb_top_psmct32_sh3_zint640 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640.vvp

# Ch358 — board proof (same pattern as sh3_zsched_board_compare): board --dump-fb must be byte-for-byte identical to
# the zint640 sim FB, and 100% exact against the replayed fragment colors.
sh3_zs640_board_compare: tb_top_psmct32_sh3_zs640_cap tb_top_psmct32_sh3_zint640
	@test -f $(SH3_ZS640_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZS640_BOARD_FB)"; \
	     echo "Run the board with --dump-fb and copy sh3_zs640_board_fb.mem here first."; exit 1)
	@echo "=== dump zint640 sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640.vvp +FBDUMP=$(SH3_ZS640_ZINT_FB)
	@echo "=== compare board framebuffer vs zint640 sim framebuffer ==="
	@sha256sum $(SH3_ZS640_BOARD_FB) $(SH3_ZS640_ZINT_FB)
	@cmp -s $(SH3_ZS640_BOARD_FB) $(SH3_ZS640_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to zint640 sim" || \
	    (echo "FAIL: board framebuffer differs from zint640 sim"; cmp -l $(SH3_ZS640_BOARD_FB) $(SH3_ZS640_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZS640_BOARD_FB) \
	    --tag zs640 --owner replay-color --frags $(TRACE_DIR)/zs640_frags.txt

# Ch359 — zs640c6 capture: TWO 204-tri shared-texture epochs through the REAL raster (ONE fill, epoch 1 reuses the
# resident cache); captures the fragment stream -> zs640c6_frags.txt (replay-color board check input).
tb_top_psmct32_sh3_zs640c6_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640c6_cap (Ch359 shared-texture residency capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c6.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c6.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c6_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640c6_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640c6_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640c6_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c6_cap.vvp

# Ch359 — real-raster persistent-Z integration for the shared-texture pair (drop gate + residency + scoreboard).
tb_top_psmct32_sh3_zint640c6: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640c6 (Ch359 real-raster residency Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c6.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c6.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c6.vvp \
	    -s tb_top_psmct32_sh3_zint640c6 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640c6.sv
	@echo "=== run tb_top_psmct32_sh3_zint640c6 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c6.vvp

# Ch359 — board proof (same contract): board --dump-fb byte-for-byte == zint640c6 sim FB + 100% replay-color.
sh3_zs640c6_board_compare: tb_top_psmct32_sh3_zs640c6_cap tb_top_psmct32_sh3_zint640c6
	@test -f $(SH3_ZS640C6_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZS640C6_BOARD_FB)"; \
	     echo "Run the board with --dump-fb and copy sh3_zs640c6_board_fb.mem here first."; exit 1)
	@echo "=== dump zint640c6 sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c6.vvp +FBDUMP=$(SH3_ZS640C6_ZINT_FB)
	@echo "=== compare board framebuffer vs zint640c6 sim framebuffer ==="
	@sha256sum $(SH3_ZS640C6_BOARD_FB) $(SH3_ZS640C6_ZINT_FB)
	@cmp -s $(SH3_ZS640C6_BOARD_FB) $(SH3_ZS640C6_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to zint640c6 sim" || \
	    (echo "FAIL: board framebuffer differs from zint640c6 sim"; cmp -l $(SH3_ZS640C6_BOARD_FB) $(SH3_ZS640C6_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZS640C6_BOARD_FB) \
	    --tag zs640c6 --owner replay-color --frags $(TRACE_DIR)/zs640c6_frags.txt

# Ch367 — runtime-CLUT proof: same real-raster Z path, but each epoch receives its palette through
# the core-side runtime writer. The board dump must match the integration framebuffer byte-for-byte.
tb_top_psmct32_sh3_zint640rt3: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rt3 (runtime-CLUT real-raster Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt3.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt3.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt3.vvp \
	    -s tb_top_psmct32_sh3_zint640rt3 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640rt3.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rt3 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt3.vvp

sh3_zsrt3_board_compare: tb_top_psmct32_sh3_zint640rt3
	@test -f $(SH3_ZSRT3_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRT3_BOARD_FB)"; \
	     echo "Run the runtime-CLUT board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump runtime-CLUT zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt3.vvp +FBDUMP=$(SH3_ZSRT3_ZINT_FB)
	@echo "=== compare board framebuffer vs runtime-CLUT zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRT3_BOARD_FB) $(SH3_ZSRT3_ZINT_FB)
	@cmp -s $(SH3_ZSRT3_BOARD_FB) $(SH3_ZSRT3_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to runtime-CLUT zint sim" || \
	    (echo "FAIL: board framebuffer differs from runtime-CLUT zint sim"; cmp -l $(SH3_ZSRT3_BOARD_FB) $(SH3_ZSRT3_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed runtime-CLUT fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRT3_BOARD_FB) \
	    --tag zsrt3 --owner replay-color --frags $(TRACE_DIR)/zsrt3_frags.txt

# Ch367 -- the established 24-draw texture-residency cluster with the runtime
# palette transport enabled on every epoch. This is fixture/host proof only;
# the signed core and its timing provenance are unchanged.
tb_top_psmct32_sh3_zint640rt24: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rt24 (24-draw runtime-CLUT Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt24_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT24_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    $(if $(filter 1,$(SH3_ZSRT24_TRACE)),-DSH3_SHARED_TRACE) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rt24 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt24.vvp

tb_top_psmct32_sh3_zint640rt24_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rt24 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt24_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT24_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrt24_board_compare: tb_top_psmct32_sh3_zint640rt24_trace
	@test -f $(SH3_ZSRT24_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRT24_BOARD_FB)"; \
	     echo "Run the runtime-CLUT 24-draw board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump runtime-CLUT 24-draw zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt24.vvp +FBDUMP=$(SH3_ZSRT24_ZINT_FB)
	@echo "=== compare board framebuffer vs runtime-CLUT 24-draw zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRT24_BOARD_FB) $(SH3_ZSRT24_ZINT_FB)
	@cmp -s $(SH3_ZSRT24_BOARD_FB) $(SH3_ZSRT24_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to runtime-CLUT 24-draw zint sim" || \
	    (echo "FAIL: board framebuffer differs from runtime-CLUT 24-draw zint sim"; cmp -l $(SH3_ZSRT24_BOARD_FB) $(SH3_ZSRT24_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed runtime-CLUT 24-draw fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRT24_BOARD_FB) \
	    --tag zsrt24 --owner replay-color --frags $(TRACE_DIR)/zsrt24_frags.txt

# Ch368 -- frame B of the runtime-CLUT motion pair. It uses the production
# 4096-entry request FIFO measured against its eight-epoch cold-Z bursts.
tb_top_psmct32_sh3_zint640rtb24: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rtb24 (frame-B runtime-CLUT Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtb24_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrtb24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtb24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTB24_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtb24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtb24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtb24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rtb24 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtb24.vvp $(if $(SH3_ZSRTB24_START_EPOCH),+START_EPOCH=$(SH3_ZSRTB24_START_EPOCH))

tb_top_psmct32_sh3_zint640rtb24_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rtb24 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtb24_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrtb24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtb24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTB24_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtb24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtb24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtb24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrtb24_board_compare: tb_top_psmct32_sh3_zint640rtb24_trace
	@test -f $(SH3_ZSRTB24_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTB24_BOARD_FB)"; \
	     echo "Run the runtime-CLUT Frame B board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump runtime-CLUT Frame B zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtb24.vvp +FBDUMP=$(SH3_ZSRTB24_ZINT_FB)
	@echo "=== compare board framebuffer vs runtime-CLUT Frame B zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTB24_BOARD_FB) $(SH3_ZSRTB24_ZINT_FB)
	@cmp -s $(SH3_ZSRTB24_BOARD_FB) $(SH3_ZSRTB24_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to runtime-CLUT Frame B zint sim" || \
	    (echo "FAIL: board framebuffer differs from runtime-CLUT Frame B zint sim"; cmp -l $(SH3_ZSRTB24_BOARD_FB) $(SH3_ZSRTB24_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed runtime-CLUT Frame B fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTB24_BOARD_FB) \
	    --tag zsrtb24 --owner replay-color --frags $(TRACE_DIR)/zsrtb24_frags.txt

# Ch369 -- runtime-CLUT version of the proven 28-draw mixed-residency frame:
# four texture rebinds followed by the eight-epoch shared-texture cluster.
tb_top_psmct32_sh3_zint640rtm28: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rtm28 (28-draw runtime-CLUT Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtm28_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrtm28"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtm28_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTM28_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtm28.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtm28.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtm28.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rtm28 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtm28.vvp

tb_top_psmct32_sh3_zint640rtm28_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rtm28 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtm28_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrtm28"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtm28_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTM28_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtm28.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtm28.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtm28.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrtm28_board_compare: tb_top_psmct32_sh3_zint640rtm28_trace
	@test -f $(SH3_ZSRTM28_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTM28_BOARD_FB)"; \
	     echo "Run the runtime-CLUT mixed-residency board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump runtime-CLUT mixed-residency zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtm28.vvp +FBDUMP=$(SH3_ZSRTM28_ZINT_FB)
	@echo "=== compare board framebuffer vs runtime-CLUT mixed-residency zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTM28_BOARD_FB) $(SH3_ZSRTM28_ZINT_FB)
	@cmp -s $(SH3_ZSRTM28_BOARD_FB) $(SH3_ZSRTM28_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to runtime-CLUT mixed-residency zint sim" || \
	    (echo "FAIL: board framebuffer differs from runtime-CLUT mixed-residency zint sim"; cmp -l $(SH3_ZSRTM28_BOARD_FB) $(SH3_ZSRTM28_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed runtime-CLUT mixed-residency fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTM28_BOARD_FB) \
	    --tag zsrtm28 --owner replay-color --frags $(TRACE_DIR)/zsrtm28_frags.txt

# Ch370 -- runtime-CLUT conversion of Frame C's 24-draw shared-texture cluster.
# It keeps the C palette relocated at CBP 504 and proves the same host-owned CLUT
# path as A/B/M28 without changing the fitted core.
tb_top_psmct32_sh3_zint640rtc24: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rtc24 (frame-C runtime-CLUT Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtc24_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrtc24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtc24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTC24_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtc24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtc24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtc24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rtc24 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtc24.vvp

tb_top_psmct32_sh3_zint640rtc24_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rtc24 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtc24_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrtc24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtc24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTC24_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtc24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtc24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtc24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrtc24_board_compare: tb_top_psmct32_sh3_zint640rtc24_trace
	@test -f $(SH3_ZSRTC24_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTC24_BOARD_FB)"; \
	     echo "Run the runtime-CLUT Frame C board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump runtime-CLUT Frame C zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtc24.vvp +FBDUMP=$(SH3_ZSRTC24_ZINT_FB)
	@echo "=== compare board framebuffer vs runtime-CLUT Frame C zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTC24_BOARD_FB) $(SH3_ZSRTC24_ZINT_FB)
	@cmp -s $(SH3_ZSRTC24_BOARD_FB) $(SH3_ZSRTC24_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to runtime-CLUT Frame C zint sim" || \
	    (echo "FAIL: board framebuffer differs from runtime-CLUT Frame C zint sim"; cmp -l $(SH3_ZSRTC24_BOARD_FB) $(SH3_ZSRTC24_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed runtime-CLUT Frame C fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTC24_BOARD_FB) \
	    --tag zsrtc24 --owner replay-color --frags $(TRACE_DIR)/zsrtc24_frags.txt

# Ch371 -- first runtime-CLUT probe from the earlier SH3 capture. Two ordered
# epochs share its PSMT8 texture, exercising a fill and verified resident reuse.
tb_top_psmct32_sh3_zint640rte3: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte3 (earlier-capture runtime-CLUT Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte3_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrte3"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte3_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE3_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte3.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte3.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte3.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte3 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte3.vvp

tb_top_psmct32_sh3_zint640rte3_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte3 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte3_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrte3"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte3_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE3_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte3.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte3.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte3.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrte3_board_compare: tb_top_psmct32_sh3_zint640rte3_trace
	@test -f $(SH3_ZSRTE3_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTE3_BOARD_FB)"; \
	     echo "Run the earlier-capture runtime-CLUT probe with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump earlier-capture runtime-CLUT zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte3.vvp +FBDUMP=$(SH3_ZSRTE3_ZINT_FB)
	@echo "=== compare board framebuffer vs earlier-capture runtime-CLUT zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTE3_BOARD_FB) $(SH3_ZSRTE3_ZINT_FB)
	@cmp -s $(SH3_ZSRTE3_BOARD_FB) $(SH3_ZSRTE3_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to earlier-capture runtime-CLUT zint sim" || \
	    (echo "FAIL: board framebuffer differs from earlier-capture runtime-CLUT zint sim"; cmp -l $(SH3_ZSRTE3_BOARD_FB) $(SH3_ZSRTE3_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed earlier-capture runtime-CLUT fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTE3_BOARD_FB) \
	    --tag zsrte3 --owner replay-color --frags $(TRACE_DIR)/zsrte3_frags.txt

# Ch372 -- two full 204-triangle epochs from the newly qualified earlier-capture texture cluster.
tb_top_psmct32_sh3_zint640rte6: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte6 (earlier-capture 6-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte6_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrte6"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte6_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE6_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte6.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte6.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte6.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte6 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte6.vvp

tb_top_psmct32_sh3_zint640rte6_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte6 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte6_params.vh"' -DSH3_SHARED_TAG='"zsrte6"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte6_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE6_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte6.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte6.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte6.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch373 -- eight chronological earlier-capture draws in three bounded runtime-CLUT epochs.
tb_top_psmct32_sh3_zint640rte8: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte8 (earlier-capture 8-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte8_params.vh"' -DSH3_SHARED_TAG='"zsrte8"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte8_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE8_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte8.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte8.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte8.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte8.vvp

tb_top_psmct32_sh3_zint640rte8_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte8 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte8_params.vh"' -DSH3_SHARED_TAG='"zsrte8"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte8_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE8_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte8.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte8.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte8.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrte8_board_compare: tb_top_psmct32_sh3_zint640rte8_trace
	@test -f $(SH3_ZSRTE8_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTE8_BOARD_FB)"; \
	     echo "Run the earlier-capture 8-draw board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump earlier-capture 8-draw zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte8.vvp +FBDUMP=$(SH3_ZSRTE8_ZINT_FB)
	@echo "=== compare board framebuffer vs earlier-capture 8-draw zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTE8_BOARD_FB) $(SH3_ZSRTE8_ZINT_FB)
	@cmp -s $(SH3_ZSRTE8_BOARD_FB) $(SH3_ZSRTE8_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to earlier-capture 8-draw zint sim" || \
	    (echo "FAIL: board framebuffer differs from earlier-capture 8-draw zint sim"; cmp -l $(SH3_ZSRTE8_BOARD_FB) $(SH3_ZSRTE8_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed earlier-capture 8-draw fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTE8_BOARD_FB) \
	    --tag zsrte8 --owner replay-color --frags $(TRACE_DIR)/zsrte8_frags.txt

# Ch374 -- Ch373's eight-draw resident sequence followed by a second runtime palette/texture binding.
tb_top_psmct32_sh3_zint640rte11: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte11 (earlier-capture 11-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte11_params.vh"' -DSH3_SHARED_TAG='"zsrte11"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte11_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE11_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte11.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte11.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte11.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte11 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte11.vvp

tb_top_psmct32_sh3_zint640rte11_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte11 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte11_params.vh"' -DSH3_SHARED_TAG='"zsrte11"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte11_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE11_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte11.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte11.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte11.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrte11_board_compare: tb_top_psmct32_sh3_zint640rte11_trace
	@test -f $(SH3_ZSRTE11_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTE11_BOARD_FB)"; \
	     echo "Run the earlier-capture 11-draw board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump earlier-capture 11-draw zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte11.vvp +FBDUMP=$(SH3_ZSRTE11_ZINT_FB)
	@echo "=== compare board framebuffer vs earlier-capture 11-draw zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTE11_BOARD_FB) $(SH3_ZSRTE11_ZINT_FB)
	@cmp -s $(SH3_ZSRTE11_BOARD_FB) $(SH3_ZSRTE11_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to earlier-capture 11-draw zint sim" || \
	    (echo "FAIL: board framebuffer differs from earlier-capture 11-draw zint sim"; cmp -l $(SH3_ZSRTE11_BOARD_FB) $(SH3_ZSRTE11_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed earlier-capture 11-draw fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTE11_BOARD_FB) \
	    --tag zsrte11 --owner replay-color --frags $(TRACE_DIR)/zsrte11_frags.txt

# Ch376 -- six-epoch, 17-draw extension of the second runtime palette residency chain.
tb_top_psmct32_sh3_zint640rte17: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte17 (17-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte17_params.vh"' -DSH3_SHARED_TAG='"zsrte17"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte17_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE17_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte17.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte17.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte17.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte17 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte17.vvp

tb_top_psmct32_sh3_zint640rte17_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte17 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte17_params.vh"' -DSH3_SHARED_TAG='"zsrte17"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte17_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE17_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte17.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte17.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte17.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrte17_board_compare: tb_top_psmct32_sh3_zint640rte17_trace
	@test -f $(SH3_ZSRTE17_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTE17_BOARD_FB)"; \
	     echo "Run the 17-draw board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump 17-draw zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte17.vvp +FBDUMP=$(SH3_ZSRTE17_ZINT_FB)
	@echo "=== compare board framebuffer vs 17-draw zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTE17_BOARD_FB) $(SH3_ZSRTE17_ZINT_FB)
	@cmp -s $(SH3_ZSRTE17_BOARD_FB) $(SH3_ZSRTE17_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to 17-draw zint sim" || \
	    (echo "FAIL: board framebuffer differs from 17-draw zint sim"; cmp -l $(SH3_ZSRTE17_BOARD_FB) $(SH3_ZSRTE17_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed 17-draw fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTE17_BOARD_FB) \
	    --tag zsrte17 --owner replay-color --frags $(TRACE_DIR)/zsrte17_frags.txt

# Ch377 -- seven-epoch, 18-draw final extension of the second runtime palette residency chain.
tb_top_psmct32_sh3_zint640rte18: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte18 (18-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte18_params.vh"' -DSH3_SHARED_TAG='"zsrte18"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte18_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE18_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte18.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte18.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte18 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte18.vvp

tb_top_psmct32_sh3_zint640rte18_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte18 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte18_params.vh"' -DSH3_SHARED_TAG='"zsrte18"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte18_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE18_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte18.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte18.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrte18_board_compare: tb_top_psmct32_sh3_zint640rte18_trace
	@test -f $(SH3_ZSRTE18_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTE18_BOARD_FB)"; \
	     echo "Run the 18-draw board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump 18-draw zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte18.vvp +FBDUMP=$(SH3_ZSRTE18_ZINT_FB)
	@echo "=== compare board framebuffer vs 18-draw zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTE18_BOARD_FB) $(SH3_ZSRTE18_ZINT_FB)
	@cmp -s $(SH3_ZSRTE18_BOARD_FB) $(SH3_ZSRTE18_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to 18-draw zint sim" || \
	    (echo "FAIL: board framebuffer differs from 18-draw zint sim"; cmp -l $(SH3_ZSRTE18_BOARD_FB) $(SH3_ZSRTE18_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed 18-draw fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTE18_BOARD_FB) \
	    --tag zsrte18 --owner replay-color --frags $(TRACE_DIR)/zsrte18_frags.txt

# Ch378 -- third runtime texture/CLUT binding, retained as a frame-pure fixture.
tb_top_psmct32_sh3_zint640rte19: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte19 (19-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte19_params.vh"' -DSH3_SHARED_TAG='"zsrte19"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte19_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE19_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte19.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte19.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte19.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte19 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte19.vvp

tb_top_psmct32_sh3_zint640rte19_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte19 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte19_params.vh"' -DSH3_SHARED_TAG='"zsrte19"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte19_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE19_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte19.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte19.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte19.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

sh3_zsrte19_board_compare: tb_top_psmct32_sh3_zint640rte19_trace
	@test -f $(SH3_ZSRTE19_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZSRTE19_BOARD_FB)"; \
	     echo "Run the 19-draw board scene with --dump-fb and copy it here first."; exit 1)
	@echo "=== dump 19-draw zint sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte19.vvp +FBDUMP=$(SH3_ZSRTE19_ZINT_FB)
	@echo "=== compare board framebuffer vs 19-draw zint sim framebuffer ==="
	@sha256sum $(SH3_ZSRTE19_BOARD_FB) $(SH3_ZSRTE19_ZINT_FB)
	@cmp -s $(SH3_ZSRTE19_BOARD_FB) $(SH3_ZSRTE19_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to 19-draw zint sim" || \
	    (echo "FAIL: board framebuffer differs from 19-draw zint sim"; cmp -l $(SH3_ZSRTE19_BOARD_FB) $(SH3_ZSRTE19_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed 19-draw fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZSRTE19_BOARD_FB) \
	    --tag zsrte19 --owner replay-color --frags $(TRACE_DIR)/zsrte19_frags.txt

# Ch379 -- deepen the third runtime texture/CLUT binding with the next frame-pure draw cluster.
tb_top_psmct32_sh3_zint640rte22: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte22 (22-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte22_params.vh"' -DSH3_SHARED_TAG='"zsrte22"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte22_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE22_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte22.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte22.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte22.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640rte22 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte22.vvp

tb_top_psmct32_sh3_zint640rte22_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte22 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte22_params.vh"' -DSH3_SHARED_TAG='"zsrte22"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte22_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE22_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte22.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte22.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte22.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rte25: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte25 (25-draw runtime-CLUT integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte25_params.vh"' -DSH3_SHARED_TAG='"zsrte25"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte25_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE25_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte25.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte25.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte25.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte25.vvp

tb_top_psmct32_sh3_zint640rte25_trace: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640rte25 trace variant ==="
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte25_params.vh"' -DSH3_SHARED_TAG='"zsrte25"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte25_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE25_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte25.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte25.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte25.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rte28: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte28_params.vh"' -DSH3_SHARED_TAG='"zsrte28"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte28_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE28_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte28.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte28.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte28.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte28.vvp

tb_top_psmct32_sh3_zint640rte28_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte28_params.vh"' -DSH3_SHARED_TAG='"zsrte28"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte28_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE28_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte28.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte28.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte28.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rte31: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte31_params.vh"' -DSH3_SHARED_TAG='"zsrte31"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte31_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE31_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte31.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte31.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte31.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte31.vvp

tb_top_psmct32_sh3_zint640rte31_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte31_params.vh"' -DSH3_SHARED_TAG='"zsrte31"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte31_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE31_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte31.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte31.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte31.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rte34: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte34_params.vh"' -DSH3_SHARED_TAG='"zsrte34"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte34_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE34_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte34.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte34.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte34.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte34.vvp

tb_top_psmct32_sh3_zint640rte34_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte34_params.vh"' -DSH3_SHARED_TAG='"zsrte34"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte34_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE34_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte34.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte34.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte34.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rte43: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte43_params.vh"' -DSH3_SHARED_TAG='"zsrte43"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte43_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE43_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte43.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte43.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte43.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte43.vvp

tb_top_psmct32_sh3_zint640rte43_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte43_params.vh"' -DSH3_SHARED_TAG='"zsrte43"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte43_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE43_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte43.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte43.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte43.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rte45: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte45_params.vh"' -DSH3_SHARED_TAG='"zsrte45"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte45_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE45_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte45.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte45.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte45.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte45.vvp

tb_top_psmct32_sh3_zint640rte45_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrte45_params.vh"' -DSH3_SHARED_TAG='"zsrte45"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrte45_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTE45_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrte45.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrte45.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rte45.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3e18: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3e18_params.vh"' -DSH3_SHARED_TAG='"zsrtf3e18"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3e18_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3E18_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3e18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3e18.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3e18.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3e18.vvp

tb_top_psmct32_sh3_zint640rtf3e18_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3e18_params.vh"' -DSH3_SHARED_TAG='"zsrtf3e18"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3e18_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3E18_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3e18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3e18.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3e18.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3e30: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3e30_params.vh"' -DSH3_SHARED_TAG='"zsrtf3e30"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3e30_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3E30_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3e30.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3e30.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3e30.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3e30.vvp

tb_top_psmct32_sh3_zint640rtf3e30_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3e30_params.vh"' -DSH3_SHARED_TAG='"zsrtf3e30"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3e30_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3E30_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3e30.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3e30.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3e30.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3c30: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c30_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c30"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c30_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C30_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c30.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c30.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c30.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c30.vvp

tb_top_psmct32_sh3_zint640rtf3c30_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c30_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c30"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c30_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C30_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c30.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c30.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c30.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3c34: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c34_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c34"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c34_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C34_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c34.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c34.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c34.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c34.vvp

tb_top_psmct32_sh3_zint640rtf3c34_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c34_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c34"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c34_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C34_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c34.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c34.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c34.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3c41: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c41_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c41"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c41_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C41_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c41.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c41.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c41.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c41.vvp

tb_top_psmct32_sh3_zint640rtf3c41_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c41_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c41"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c41_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C41_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c41.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c41.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c41.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3c49: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c49_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c49"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c49_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C49_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c49.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c49.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c49.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c49.vvp

tb_top_psmct32_sh3_zint640rtf3c49_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrtf3c49_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c49"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c49_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C49_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c49.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c49.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c49.vvp -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3c57: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrtf3c57_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c57"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c57_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C57_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c57.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c57.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c57.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c57.vvp

tb_top_psmct32_sh3_zint640rtf3c57_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrtf3c57_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c57"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c57_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C57_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c57.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c57.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c57.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rtf3c57x: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrtf3c57x_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c57x"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c57x_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C57X_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c57x.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c57x.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c57x.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c57x.vvp

tb_top_psmct32_sh3_zint640rtf3c57x_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrtf3c57x_params.vh"' -DSH3_SHARED_TAG='"zsrtf3c57x"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrtf3c57x_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRTF3C57X_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrtf3c57x.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrtf3c57x.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rtf3c57x.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch394 — 224139 (the PCSX2 rabbit/bench capture) aligned baseline.  This is
# deliberately an opaque/state-coverage rung: it establishes comparable image A
# before the separately-scoped blended pass.
tb_top_psmct32_sh3_zint640rt139o6: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139o6_params.vh"' -DSH3_SHARED_TAG='"zsrt139o6"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139o6_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139O6_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139o6.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139o6.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139o6.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139o6.vvp

tb_top_psmct32_sh3_zint640rt139o6_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139o6_params.vh"' -DSH3_SHARED_TAG='"zsrt139o6"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139o6_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139O6_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139o6.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139o6.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139o6.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rt139a1: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a1_params.vh"' -DSH3_SHARED_TAG='"zsrt139a1"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a1_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A1_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a1.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a1.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a1.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a1.vvp

tb_top_psmct32_sh3_zint640rt139a1_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a1_params.vh"' -DSH3_SHARED_TAG='"zsrt139a1"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a1_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A1_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a1.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a1.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a1.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

tb_top_psmct32_sh3_zint640rt139a2: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a2_params.vh"' -DSH3_SHARED_TAG='"zsrt139a2"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a2_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A2_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a2.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a2.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a2.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a2.vvp

tb_top_psmct32_sh3_zint640rt139a2_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a2_params.vh"' -DSH3_SHARED_TAG='"zsrt139a2"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a2_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A2_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a2.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a2.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a2.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch397 — authentic ABE=1 PSMT8 triangle epoch through LPDDR destination blending.
SH3_ZSRT139A3_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139a3: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a3_params.vh"' -DSH3_SHARED_TAG='"zsrt139a3"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a3_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A3_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a3.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a3.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a3.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a3.vvp

tb_top_psmct32_sh3_zint640rt139a3_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a3_params.vh"' -DSH3_SHARED_TAG='"zsrt139a3"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a3_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A3_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a3.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a3.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a3_trace.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch398 — six authentic ABE draws split into three staging-safe ordered epochs.
SH3_ZSRT139A4_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139a4: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a4_params.vh"' -DSH3_SHARED_TAG='"zsrt139a4"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a4_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A4_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a4.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a4.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a4.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a4.vvp

tb_top_psmct32_sh3_zint640rt139a4_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a4_params.vh"' -DSH3_SHARED_TAG='"zsrt139a4"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a4_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A4_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a4.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a4.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a4_trace.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch399 — full first in-bounds alpha family: 40 ABE draws in 14 ordered groups.
SH3_ZSRT139A5_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139a5: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a5_params.vh"' -DSH3_SHARED_TAG='"zsrt139a5"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a5_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A5_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a5.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a5.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a5.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a5.vvp

tb_top_psmct32_sh3_zint640rt139a5_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a5_params.vh"' -DSH3_SHARED_TAG='"zsrt139a5"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a5_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A5_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a5.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a5.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a5_trace.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch400 — chronological in-bounds base geometry followed by a bounded ABE tail.
SH3_ZSRT139A6_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139a6: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a6_params.vh"' -DSH3_SHARED_TAG='"zsrt139a6"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a6_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A6_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a6.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a6.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a6.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a6.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139a6_sim_fb.mem

tb_top_psmct32_sh3_zint640rt139a6_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a6_params.vh"' -DSH3_SHARED_TAG='"zsrt139a6"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a6_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A6_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a6.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a6.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a6_trace.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch401 — a6 chronological base plus high-coverage later-scene anchors and the
# proven 24-draw central cluster: 56 authentic draws in 28 bounded epochs.
SH3_ZSRT139A7_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139a7: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a7_params.vh"' -DSH3_SHARED_TAG='"zsrt139a7"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a7_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A7_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a7.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a7.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a7.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a7.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139a7_sim_fb.mem

tb_top_psmct32_sh3_zint640rt139a7_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a7_params.vh"' -DSH3_SHARED_TAG='"zsrt139a7"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a7_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A7_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a7.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a7.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a7_trace.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch402 — Ch401 plus twelve authentic single-draw character epochs. The
# optional CLAMP header carries normalized full-texture region-clamp state;
# splitting the character family retains the accepted 2048-word staging RAM.
SH3_ZSRT139A8_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139a8: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a8_params.vh"' -DSH3_SHARED_TAG='"zsrt139a8"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a8_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A8_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a8.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a8.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a8.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a8.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139a8_sim_fb.mem

tb_top_psmct32_sh3_zint640rt139a8_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a8_params.vh"' -DSH3_SHARED_TAG='"zsrt139a8"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a8_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A8_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a8.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a8.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a8_trace.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch403 — Ch402 geometry with authentic vertex RGB and TEX0.TFX=MODULATE.
SH3_ZSRT139A9_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139a9: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a9_params.vh"' -DSH3_SHARED_TAG='"zsrt139a9"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a9_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A9_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a9.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a9.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a9.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a9.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139a9_sim_fb.mem

tb_top_psmct32_sh3_zint640rt139a9_trace: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139a9_params.vh"' -DSH3_SHARED_TAG='"zsrt139a9"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139a9_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139A9_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SHARED_TRACE -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139a9.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139a9.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139a9_trace.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv

# Ch404 — accepted Ch403 40-epoch base plus 35 chronological character-detail epochs.
SH3_ZSRT139B2_REQ_DEPTH ?= 4096
tb_top_psmct32_sh3_zint640rt139b2: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139b2_params.vh"' -DSH3_SHARED_TAG='"zsrt139b2"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139b2_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139B2_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139b2.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139b2.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139b2.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139b2.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139b2_sim_fb.mem

# Ch405 — Ch404 opaque base plus three authentic Z-read-only alpha-fan epochs.
SH3_ZSRT139C2_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139c2: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139c2_params.vh"' -DSH3_SHARED_TAG='"zsrt139c2"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139c2_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139C2_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139c2.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139c2.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139c2.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139c2.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139c2_sim_fb.mem

# Ch405 bounded-burst production fixture: 75 accepted opaque epochs plus 212
# one-triangle alpha epochs. 16K covers the measured 14,752-pixel worst case.
SH3_ZSRT139C4_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139c4: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139c4_params.vh"' -DSH3_SHARED_TAG='"zsrt139c4"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139c4_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139C4_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139c4.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139c4.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139c4.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139c4.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139c4_sim_fb.mem

# Ch407 chronological continuation: accepted 287-epoch Ch405 scene plus the
# remaining 35 supported PSMT8 alpha fans, clipped from the authentic GS guard
# band into 167 one-triangle epochs. Existing Ch406 core; no RTL change.
SH3_ZSRT139D2_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139d2: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139d2_params.vh"' -DSH3_SHARED_TAG='"zsrt139d2"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139d2_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139D2_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139d2.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139d2.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139d2.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139d2.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139d2_sim_fb.mem

# Ch407 capacity-safe continuation: the 287-epoch accepted base plus 35
# chronological PSMT8 alpha fans, guard-band clipped and ordered into 187
# epochs capped at 14,500 packed fragments (474 total). Existing Ch406 core.
SH3_ZSRT139D4_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139d4: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139d4_params.vh"' -DSH3_SHARED_TAG='"zsrt139d4"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139d4_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139D4_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139d4.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139d4.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139d4.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139d4.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139d4_sim_fb.mem

# Ch407 authentic-SCISSOR correction of D4: x[0..511], y[0..511]
# intersects the 640x480 target as 512x480 (434 total epochs).
SH3_ZSRT139D6_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139d6: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139d6_params.vh"' -DSH3_SHARED_TAG='"zsrt139d6"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139d6_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139D6_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139d6.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139d6.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139d6.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139d6.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139d6_sim_fb.mem

# Ch408 authentic 16-sprite PSMT4 darkening overlay appended to D6. The
# sprites are FST->triangle converted and capacity-packed into 18 epochs.
SH3_ZSRT139E2_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139e2: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139e2_params.vh"' -DSH3_SHARED_TAG='"zsrt139e2"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139e2_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139E2_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139e2.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139e2.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139e2.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139e2.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139e2_sim_fb.mem

# Ch415 authentic vertex-fog fold plus perspective palette-bilinear filtering.
# The shared harness enables the serialized four-tap sampler and dumps the
# resulting full 640x480 framebuffer for direct PCSX2 comparison.
SH3_ZSRT139F16_REQ_DEPTH ?= 16384
SH3_ZSRT139F16_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f16: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139f16_params.vh"' -DSH3_SHARED_TAG='"zsrt139f16"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f16_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F16_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f16.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f16.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139f16.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139f16.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f16_sim_fb.mem $(SH3_ZSRT139F16_VVP_ARGS)

# Ch416 native 12.4 smoke fixture: three authentic draws with fractional XYZ
# bits preserved, exercising the opt-in pixel-center coverage path end to end.
tb_top_psmct32_sh3_zint640zspxy3: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zspxy3_params.vh"' -DSH3_SHARED_TAG='"zspxy3"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zspxy3_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=16384 -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zspxy3.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zspxy3.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640zspxy3.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640zspxy3.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zspxy3_sim_fb.mem

# Ch416 full chronological scene with captured XYZ 12.4 fractions retained.
# Attribute gradients remain on the proven integer basis in this first cut;
# coverage uses the native vertices and GS pixel-center sampling.
SH3_ZSRT139F17_REQ_DEPTH ?= 16384
SH3_ZSRT139F17_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f17: dirs
	$(IVERILOG) $(IVERILOG_FLGS) -I$(SIM_DIR)/data/top_psmct32_raster_demo -DSH3_SHARED_PARAMS='"sh3_zsrt139f17_params.vh"' -DSH3_SHARED_TAG='"zsrt139f17"' -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f17_epoch_table.vh"' -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F17_REQ_DEPTH) -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_FAST_GRAD -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f17.mem"' -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f17.mem"' -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139f17.vvp -s tb_top_psmct32_sh3_zint640_shared $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640rt139f17.vvp +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f17_sim_fb.mem $(SH3_ZSRT139F17_VVP_ARGS)

# Ch417 pre-fit production-control gate.  Verilator keeps the 263-epoch run
# practical while SH3_BOARD_GRAD exercises the exact DE25 combinational divider
# selection and five-cycle settle FSM.  The resulting framebuffer must hash
# identically to the one-cycle arithmetic/reference run above.
tb_top_psmct32_sh3_zint640rt139f17_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f17_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f17"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f17_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F17_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f17.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f17.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch417_boardgrad -o ch417_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch417_boardgrad/ch417_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f17_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F17_VVP_ARGS)

# Ch419 convergence gate: the accepted 263-epoch Ch417 scene followed by the
# 20-epoch rabbit/bench completion tail.  This also exercises the production
# registered request-RAM read and registered read-arbiter release timing cuts.
SH3_ZSRT139F18_REQ_DEPTH ?= 16384
SH3_ZSRT139F18_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f18_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f18_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f18"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f18_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F18_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f18.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch419_boardgrad -o ch419_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch419_boardgrad/ch419_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f18_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F18_VVP_ARGS)

# Ch424 fidelity repair: retain the complete 766-draw Ch415 grouped scene
# while using native 12.4 coverage and the production registered gradient
# path.  Ch416 accidentally regenerated from only the 113 surviving group
# representatives; this target proves the repaired population end to end.
SH3_ZSRT139F19_REQ_DEPTH ?= 16384
SH3_ZSRT139F19_VVP_ARGS ?=
SH3_ZSRT139F19_FBDUMP ?= ../../data/top_psmct32_raster_demo/sh3_zsrt139f19_boardgrad_sim_fb.mem
tb_top_psmct32_sh3_zint640rt139f19_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f19_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f19"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f19_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F19_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f19.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f19.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch424_boardgrad -o ch424_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch424_boardgrad/ch424_boardgrad_vlt \
	    +FBDUMP=$(SH3_ZSRT139F19_FBDUMP) \
	    $(SH3_ZSRT139F19_VVP_ARGS)

# Ch433 precision recheck: now that Ch432 restores the missing perspective
# samples, remeasure the f19 scene with a 13-bit reciprocal table.  The earlier
# Ch427 A/B ran through the half-population sampler and could not establish the
# post-repair precision return.
tb_top_psmct32_sh3_zint640rt139f19_recip13_ch433_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f19_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f19"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f19_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F19_REQ_DEPTH) \
	    -DSH3_SHARED_RECIP_BITS=13 \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f19.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f19.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch433_f19_recip13_boardgrad -o ch433_f19_recip13_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch433_f19_recip13_boardgrad/ch433_f19_recip13_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f19_recip13_ch433_boardgrad_sim_fb.mem

# Ch433 filter isolation: unchanged post-Ch432 f19 geometry and reciprocal,
# but nearest indexed sampling.  This distinguishes UV/interpolation error
# from a four-tap sampler alignment error before any new RTL is proposed.
tb_top_psmct32_sh3_zint640rt139f19_nearest_ch433_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f19_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f19"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f19_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F19_REQ_DEPTH) \
	    -DSH3_SHARED_NO_BILINEAR \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f19.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f19.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch433_f19_nearest_boardgrad -o ch433_f19_nearest_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch433_f19_nearest_boardgrad/ch433_f19_nearest_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f19_nearest_ch433_boardgrad_sim_fb.mem

# Ch433 fixture-precision isolation: the exact f19 draw population, grouping,
# native 12.4 geometry, and feature set, with the generator's per-triangle UV
# error optimizer replacing --fast-fit-scale.  This changes staging STQ only;
# the production RTL remains identical to the accepted Ch432 board image.
SH3_ZSRT139F43_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139f43_uvopt_ch433_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f43_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f43"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f43_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F43_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f43.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f43.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch433_f43_uvopt_boardgrad -o ch433_f43_uvopt_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch433_f43_uvopt_boardgrad/ch433_f43_uvopt_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f43_uvopt_ch433_boardgrad_sim_fb.mem

# Ch425 fidelity candidate: the repaired full scene followed in capture order
# by the authentic CT32 darken, PSMT8 alpha-fan, and PSMT4 postprocess passes.
SH3_ZSRT139F20_REQ_DEPTH ?= 16384
SH3_ZSRT139F20_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f20_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f20_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f20"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f20_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F20_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f20.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f20.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch425_boardgrad -o ch425_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch425_boardgrad/ch425_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f20_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F20_VVP_ARGS)

# Ch425 postprocess isolation: retain the accepted Ch424 scene and append only
# the authentic PSMT4 tail.  The CT32 darken and PSMT8 alpha-fan candidates are
# deliberately absent after their independent fidelity gates regressed.
SH3_ZSRT139F21_REQ_DEPTH ?= 16384
SH3_ZSRT139F21_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f21_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f21_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f21"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f21_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F21_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f21.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f21.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch425_psmt4_boardgrad -o ch425_psmt4_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch425_psmt4_boardgrad/ch425_psmt4_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f21_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F21_VVP_ARGS)

# Ch426 fidelity repair: Ch424 scene + authentic CT32 darken + regenerated
# alpha fans whose captured RGBAQ.A is preserved (the legacy generator forced
# A=ff and made the additive fog catastrophically white).
SH3_ZSRT139F23_REQ_DEPTH ?= 16384
SH3_ZSRT139F23_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f23_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f23_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f23"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f23_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F23_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f23.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f23.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch426_boardgrad -o ch426_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch426_boardgrad/ch426_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f23_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F23_VVP_ARGS)

# Ch426 controlled A/B: repaired alpha directly after Ch424, omitting the
# reconstructed CT32 intermediate darken to measure that pass independently.
SH3_ZSRT139F24_REQ_DEPTH ?= 16384
SH3_ZSRT139F24_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f24_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f24_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F24_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f24.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch426_nodarken_boardgrad -o ch426_nodarken_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch426_nodarken_boardgrad/ch426_nodarken_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f24_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F24_VVP_ARGS)

# Ch427 diagnostic: identical accepted Ch426 fixture with a 13-bit reciprocal
# mantissa (11-bit production baseline) to measure the practical precision
# ceiling before spending a Quartus compile or scarce RAM blocks.
tb_top_psmct32_sh3_zint640rt139f23_recip13_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f23_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f23"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f23_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F23_REQ_DEPTH) \
	    -DSH3_SHARED_RECIP_BITS=13 \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f23.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f23.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch427_recip13_boardgrad -o ch427_recip13_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch427_recip13_boardgrad/ch427_recip13_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f23_recip13_boardgrad_sim_fb.mem

# Ch427 completeness candidate: Ch424 + CT32 + all 93 captured PSMT8 alpha
# fans (408 bounded triangle epochs), using the repaired authentic RGBAQ.A.
SH3_ZSRT139F26_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139f26_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f26_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f26"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f26_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F26_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f26.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f26.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch427_allalpha_boardgrad -o ch427_allalpha_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch427_allalpha_boardgrad/ch427_allalpha_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f26_boardgrad_sim_fb.mem

# Ch427 operational all-alpha candidate: same 93 captured fans as f26, packed
# into 129 ordered epochs under the proven 14,500-fragment burst ceiling.
SH3_ZSRT139F28_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139f28_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f28_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f28"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f28_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F28_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f28.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f28.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch427_allalpha_cap_boardgrad -o ch427_allalpha_cap_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch427_allalpha_cap_boardgrad/ch427_allalpha_cap_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f28_boardgrad_sim_fb.mem

# Ch428 fidelity candidate: the complete opaque PSMT8 strip scene with the 70
# captured ABE strip draws restored at their true chronological positions,
# followed by the accepted CT32 darken and complete authentic-alpha tail.
SH3_ZSRT139F30_REQ_DEPTH ?= 16384
SH3_ZSRT139F30_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f30_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f30_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f30"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f30_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F30_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f30.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f30.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch428_fullabe_boardgrad -o ch428_fullabe_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch428_fullabe_boardgrad/ch428_fullabe_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f30_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F30_VVP_ARGS)

# Ch428 controlled 256-logical-texture candidate: accepted Ch427 base with the
# 240 captured ABE triangle-list draws inserted before the final three opaque
# scene draws.  The rejected interleaved-strip A/B is deliberately absent.
SH3_ZSRT139F33_REQ_DEPTH ?= 16384
SH3_ZSRT139F33_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f33_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f33_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f33"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f33_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F33_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f33.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f33.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch428_tri256_boardgrad -o ch428_tri256_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch428_tri256_boardgrad/ch428_tri256_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f33_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F33_VVP_ARGS)

# Ch429 first chronology-correct PSMT4 post-process A/B: append the captured
# 16-sprite tiled overlay after the complete, accepted f33 scene/CT32/alpha
# chain.  Ch425's PSMT4-only isolation lacked those prerequisite passes.
SH3_ZSRT139F34_REQ_DEPTH ?= 16384
SH3_ZSRT139F34_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f34_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f34_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f34"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f34_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F34_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f34.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f34.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch429_psmt4_boardgrad -o ch429_psmt4_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch429_psmt4_boardgrad/ch429_psmt4_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f34_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F34_VVP_ARGS)

# Ch429 native PSMT4 character recovery: insert the 19 captured 512x1024
# opaque strips before the logical-256 triangle family and final opaque tail.
SH3_ZSRT139F36_REQ_DEPTH ?= 16384
SH3_ZSRT139F36_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f36_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f36_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f36"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f36_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F36_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f36.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f36.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch429_character4_boardgrad -o ch429_character4_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch429_character4_boardgrad/ch429_character4_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f36_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F36_VVP_ARGS)

# Ch430 late-frame sprite recovery: append the three authentic PSMT8 sprites
# at idx198700/198710/198720 after the complete alpha tail.  The 128x128
# logical tile remains in the proven physical 512-wide cache window.
SH3_ZSRT139F38_REQ_DEPTH ?= 16384
SH3_ZSRT139F38_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f38_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f38_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f38"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f38_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F38_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f38.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f38.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch430_sprite128_boardgrad -o ch430_sprite128_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch430_sprite128_boardgrad/ch430_sprite128_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f38_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F38_VVP_ARGS)

# Ch430 operational sprite candidate: identical captured sprites, but bounded
# to 6,000 estimated samples per epoch after the 14,500-sample candidate
# exceeded the production harness's fresh-drain deadline.
SH3_ZSRT139F40_REQ_DEPTH ?= 16384
SH3_ZSRT139F40_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f40_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f40_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f40"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f40_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F40_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f40.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f40.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch430_sprite128_cap_boardgrad -o ch430_sprite128_cap_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch430_sprite128_cap_boardgrad/ch430_sprite128_cap_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f40_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F40_VVP_ARGS)

# Ch431 direct-color character highlights: restore the two authentic 64x64
# PSMCT32 ABE strips at their exact positions around the PSMT4 body epochs.
SH3_ZSRT139F42_REQ_DEPTH ?= 16384
SH3_ZSRT139F42_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f42_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f42_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f42"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f42_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F42_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f42.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f42.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch431_ct32_highlights_boardgrad -o ch431_ct32_highlights_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch431_ct32_highlights_boardgrad/ch431_ct32_highlights_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f42_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F42_VVP_ARGS)

# Ch432 perspective-bilinear handshake repair: replay the unchanged accepted
# f42 composition through RTL that holds the raster walker on the sampler
# launch cycle.  A separate object directory and dump preserve the Ch431
# baseline for direct before/after scoring.
SH3_ZSRT139F42_CH432_REQ_DEPTH ?= 16384
SH3_ZSRT139F42_CH432_VVP_ARGS ?=
tb_top_psmct32_sh3_zint640rt139f42_ch432_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f42_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f42"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f42_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F42_CH432_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f42.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f42.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch432_persp_bili_hold_boardgrad -o ch432_persp_bili_hold_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch432_persp_bili_hold_boardgrad/ch432_persp_bili_hold_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f42_ch432_boardgrad_sim_fb.mem \
	    $(SH3_ZSRT139F42_CH432_VVP_ARGS)

# Ch433 complete composition: replace f42's fast-fit f19 base slices with the
# UV-error-optimized f43 slices while preserving every chronology-correct
# PSMT4/direct-color character and alpha/postprocess epoch.
SH3_ZSRT139F44_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139f44_uvopt_ch433_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f44_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f44"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f44_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F44_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f44.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f44.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch433_f44_uvopt_boardgrad -o ch433_f44_uvopt_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch433_f44_uvopt_boardgrad/ch433_f44_uvopt_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f44_uvopt_ch433_boardgrad_sim_fb.mem

# Ch439 production capacity/timing proof. The complete 311-epoch f52 scene
# measured a 6,115-entry request-FIFO high-water mark. Exercise the shipping
# 8K depth (2,077 entries / 34% measured headroom) through the complete replay.
SH3_ZSRT139F52_REQ_DEPTH ?= 8192
tb_top_psmct32_sh3_zint640rt139f52_ch439_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f52_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f52"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f52_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F52_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f52.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f52.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch439_zsrt139f52_boardgrad -o ch439_zsrt139f52_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch439_zsrt139f52_boardgrad/ch439_zsrt139f52_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f52_ch439_8k_sim_fb.mem

# Ch434 diagnostic: the previously omitted authentic TME=0 alpha-lit fan and
# triangle family.  It runs on the unchanged Ch432/433 raster fabric; the
# fixture alone exposes captured Gouraud color plus destination blending.
SH3_ZSRT139F45_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139f45_untextured_ch434_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f45_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f45"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f45_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F45_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f45.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f45.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch434_f45_untextured_boardgrad -o ch434_f45_untextured_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch434_f45_untextured_boardgrad/ch434_f45_untextured_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f45_untextured_ch434_boardgrad_sim_fb.mem

# Ch434 production candidate: insert f45's recovered untextured lighting
# geometry after the last pre-177k scene draw and before the existing CT32
# darken/postprocess and textured-alpha tail.
SH3_ZSRT139F46_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139f46_untextured_ch434_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139f46_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139f46"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139f46_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139F46_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139f46.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139f46.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch434_f46_untextured_boardgrad -o ch434_f46_untextured_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch434_f46_untextured_boardgrad/ch434_f46_untextured_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139f46_untextured_ch434_boardgrad_sim_fb.mem

# Ch434 offscreen-light reconstruction stage: build the accepted scene Z,
# clear a 256x256 neutral-gray color target, apply the Z-tested additive and
# subtractive light volumes, then remove the neutral bias.  The upper-left
# 256x256 result is the authentic PSMCT16 light-buffer source (represented in
# expanded CT32 lanes for staged static-frame reconstruction).
SH3_ZSRT139L2_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_zint640rt139l2_lightbuf_ch434_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zsrt139l2_params.vh"' \
	    -DSH3_SHARED_TAG='"zsrt139l2"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zsrt139l2_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(SH3_ZSRT139L2_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zsrt139l2.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zsrt139l2.mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch434_l2_lightbuf_boardgrad -o ch434_l2_lightbuf_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch434_l2_lightbuf_boardgrad/ch434_l2_lightbuf_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/sh3_zsrt139l2_lightbuf_ch434_boardgrad_sim_fb.mem

# Ch434 small offscreen reconstruction stages. Override CH434_STAGE_TAG and
# CH434_STAGE_OUT for each captured ping-pong sprite pass.
CH434_STAGE_TAG ?= zsrt139l3
CH434_STAGE_OUT ?= sh3_$(CH434_STAGE_TAG)_ch434_boardgrad_sim_fb.mem
CH434_STAGE_REQ_DEPTH ?= 16384
tb_top_psmct32_sh3_ch434_stage_boardgrad_vlt: dirs
	$(VERILATOR) --binary --timing --bbox-unsup -Wno-fatal \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_$(CH434_STAGE_TAG)_params.vh"' \
	    -DSH3_SHARED_TAG='"$(CH434_STAGE_TAG)"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_$(CH434_STAGE_TAG)_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=$(CH434_STAGE_REQ_DEPTH) \
	    -DSH3_SHARED_RUNTIME_CLUT -DSH3_SUBPIXEL_XY -DSH3_BOARD_GRAD \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_$(CH434_STAGE_TAG).mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_$(CH434_STAGE_TAG).mem"' \
	    --top-module tb_top_psmct32_sh3_zint640_shared \
	    --Mdir $(BUILD_DIR)/obj_ch434_$(CH434_STAGE_TAG)_boardgrad -o ch434_$(CH434_STAGE_TAG)_boardgrad_vlt \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@cd $(TRACE_DIR) && $(BUILD_DIR)/obj_ch434_$(CH434_STAGE_TAG)_boardgrad/ch434_$(CH434_STAGE_TAG)_boardgrad_vlt \
	    +FBDUMP=../../data/top_psmct32_raster_demo/$(CH434_STAGE_OUT)

# Ch360 — four-epoch shared-texture residency expansion. C12 uses the same bootlet words as C6; these are
# simulation gates first, to measure the request-FIFO high-water before any board run.
tb_top_psmct32_sh3_zs640c12_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640c12_cap (Ch360 4-epoch shared-texture capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c12.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c12.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c12_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640c12_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640c12_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640c12_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c12_cap.vvp

tb_top_psmct32_sh3_zint640c12: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640c12 (Ch360 4-epoch real-raster Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c12.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c12.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c12.vvp \
	    -s tb_top_psmct32_sh3_zint640c12 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640c12.sv
	@echo "=== run tb_top_psmct32_sh3_zint640c12 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c12.vvp

# Shared-epoch harness smoke gate. It must reproduce the already-closed C12 fixture before it is used to
# generate the next draw-count rung. The generated params header supplies N_EPOCHS and the descriptor lookup helpers.
tb_top_psmct32_sh3_zs640_shared_c12_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640_shared_c12_cap (shared-harness C12 equivalence) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c12_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c12"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c12_epoch_table.vh"' \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c12.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c12.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640_shared_c12_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_shared_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_shared_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640_shared_c12_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640_shared_c12_cap.vvp

tb_top_psmct32_sh3_zint640_shared_c12: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640_shared_c12 (shared-harness C12 Z equivalence) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c12_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c12"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c12_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=1024 \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c12.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c12.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640_shared_c12.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640_shared_c12 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640_shared_c12.vvp

tb_top_psmct32_sh3_zs640c18_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640c18_cap (Ch361 shared-harness capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c18_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c18"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c18_epoch_table.vh"' \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c18.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c18_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_shared_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_shared_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640c18_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c18_cap.vvp

tb_top_psmct32_sh3_zint640c18: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640c18 (Ch361 shared-harness Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c18_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c18"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c18_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=1024 \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c18.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c18.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640c18 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c18.vvp

tb_top_psmct32_sh3_zs640c24_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640c24_cap (Ch362 shared-harness capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c24_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c24_epoch_table.vh"' \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c24_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_shared_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_shared_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640c24_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c24_cap.vvp

tb_top_psmct32_sh3_zint640c24: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640c24 (Ch362 shared-harness Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c24_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=1024 \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640c24 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c24.vvp

tb_top_psmct32_sh3_zs640mt5_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640mt5_cap (Ch363 multi-texture capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640mt5_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640mt5"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640mt5_epoch_table.vh"' \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640mt5.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640mt5.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640mt5_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_shared_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_shared_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640mt5_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640mt5_cap.vvp

tb_top_psmct32_sh3_zint640mt5: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640mt5 (Ch363 multi-texture Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640mt5_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640mt5"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640mt5_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=1024 \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640mt5.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640mt5.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640mt5.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640mt5 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640mt5.vvp

tb_top_psmct32_sh3_zs640m28_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640m28_cap (Ch364 mixed-residency capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640m28_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640m28"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640m28_epoch_table.vh"' \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640m28.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640m28.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640m28_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_shared_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_shared_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640m28_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640m28_cap.vvp

tb_top_psmct32_sh3_zint640m28: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640m28 (Ch364 mixed-residency Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640m28_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640m28"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640m28_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=1024 \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640m28.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640m28.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640m28.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640m28 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640m28.vvp

tb_top_psmct32_sh3_zs640b24_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640b24_cap (Ch365 frame-B capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640b24_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640b24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640b24_epoch_table.vh"' \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640b24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640b24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640b24_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_shared_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_shared_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640b24_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640b24_cap.vvp

tb_top_psmct32_sh3_zint640b24: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640b24 (Ch365 frame-B Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640b24_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640b24"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640b24_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=1024 \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640b24.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640b24.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640b24.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640b24 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640b24.vvp

tb_top_psmct32_sh3_zs640c24c_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_zs640c24c_cap (Ch366 frame-C capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c24c_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c24c"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c24c_epoch_table.vh"' \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c24c.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c24c.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c24c_cap.vvp \
	    -s tb_top_psmct32_sh3_zs640_shared_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zs640_shared_cap.sv
	@echo "=== run tb_top_psmct32_sh3_zs640c24c_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zs640c24c_cap.vvp

tb_top_psmct32_sh3_zint640c24c: dirs
	@echo "=== build tb_top_psmct32_sh3_zint640c24c (Ch366 frame-C Z integration) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DSH3_SHARED_PARAMS='"sh3_zs640c24c_params.vh"' \
	    -DSH3_SHARED_TAG='"zs640c24c"' \
	    -DSH3_SHARED_EPOCH_TABLE='"sh3_zs640c24c_epoch_table.vh"' \
	    -DSH3_SHARED_REQ_DEPTH=1024 \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_zs640c24c.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_zs640c24c.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c24c.vvp \
	    -s tb_top_psmct32_sh3_zint640_shared \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_zint640_shared.sv
	@echo "=== run tb_top_psmct32_sh3_zint640c24c ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c24c.vvp

sh3_zs640b24_board_compare:
	@test -f $(SH3_ZS640B24_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZS640B24_BOARD_FB)"; \
	     echo "Run the motion board sequence with --dump-fb and copy its final B framebuffer here first."; exit 1)
	@test -x $(BUILD_DIR)/tb_top_psmct32_sh3_zint640b24.vvp || \
	    (echo "MISSING: $(BUILD_DIR)/tb_top_psmct32_sh3_zint640b24.vvp"; \
	     echo "Run: make -C sim tb_top_psmct32_sh3_zint640b24"; exit 1)
	@echo "=== dump zint640b24 sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640b24.vvp +FBDUMP=$(SH3_ZS640B24_ZINT_FB)
	@echo "=== compare board framebuffer vs zint640b24 sim framebuffer ==="
	@sha256sum $(SH3_ZS640B24_BOARD_FB) $(SH3_ZS640B24_ZINT_FB)
	@cmp -s $(SH3_ZS640B24_BOARD_FB) $(SH3_ZS640B24_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to zint640b24 sim" || \
	    (echo "FAIL: board framebuffer differs from zint640b24 sim"; cmp -l $(SH3_ZS640B24_BOARD_FB) $(SH3_ZS640B24_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZS640B24_BOARD_FB) \
	    --tag zs640b24 --owner replay-color --frags $(TRACE_DIR)/zs640b24_frags.txt

sh3_zs640m28_board_compare: tb_top_psmct32_sh3_zs640m28_cap tb_top_psmct32_sh3_zint640m28
	@test -f $(SH3_ZS640M28_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZS640M28_BOARD_FB)"; \
	     echo "Run the board with --dump-fb and copy sh3_zs640m28_board_fb.mem here first."; exit 1)
	@echo "=== dump zint640m28 sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640m28.vvp +FBDUMP=$(SH3_ZS640M28_ZINT_FB)
	@echo "=== compare board framebuffer vs zint640m28 sim framebuffer ==="
	@sha256sum $(SH3_ZS640M28_BOARD_FB) $(SH3_ZS640M28_ZINT_FB)
	@cmp -s $(SH3_ZS640M28_BOARD_FB) $(SH3_ZS640M28_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to zint640m28 sim" || \
	    (echo "FAIL: board framebuffer differs from zint640m28 sim"; cmp -l $(SH3_ZS640M28_BOARD_FB) $(SH3_ZS640M28_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZS640M28_BOARD_FB) \
	    --tag zs640m28 --owner replay-color --frags $(TRACE_DIR)/zs640m28_frags.txt

sh3_zs640mt5_board_compare: tb_top_psmct32_sh3_zs640mt5_cap tb_top_psmct32_sh3_zint640mt5
	@test -f $(SH3_ZS640MT5_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZS640MT5_BOARD_FB)"; \
	     echo "Run the board with --dump-fb and copy sh3_zs640mt5_board_fb.mem here first."; exit 1)
	@echo "=== dump zint640mt5 sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640mt5.vvp +FBDUMP=$(SH3_ZS640MT5_ZINT_FB)
	@echo "=== compare board framebuffer vs zint640mt5 sim framebuffer ==="
	@sha256sum $(SH3_ZS640MT5_BOARD_FB) $(SH3_ZS640MT5_ZINT_FB)
	@cmp -s $(SH3_ZS640MT5_BOARD_FB) $(SH3_ZS640MT5_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to zint640mt5 sim" || \
	    (echo "FAIL: board framebuffer differs from zint640mt5 sim"; cmp -l $(SH3_ZS640MT5_BOARD_FB) $(SH3_ZS640MT5_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZS640MT5_BOARD_FB) \
	    --tag zs640mt5 --owner replay-color --frags $(TRACE_DIR)/zs640mt5_frags.txt

sh3_zs640c12_board_compare: tb_top_psmct32_sh3_zs640c12_cap tb_top_psmct32_sh3_zint640c12
	@test -f $(SH3_ZS640C12_BOARD_FB) || \
	    (echo "MISSING: $(SH3_ZS640C12_BOARD_FB)"; \
	     echo "Run the board with --dump-fb and copy sh3_zs640c12_board_fb.mem here first."; exit 1)
	@echo "=== dump zint640c12 sim framebuffer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_zint640c12.vvp +FBDUMP=$(SH3_ZS640C12_ZINT_FB)
	@echo "=== compare board framebuffer vs zint640c12 sim framebuffer ==="
	@sha256sum $(SH3_ZS640C12_BOARD_FB) $(SH3_ZS640C12_ZINT_FB)
	@cmp -s $(SH3_ZS640C12_BOARD_FB) $(SH3_ZS640C12_ZINT_FB) && \
	    echo "PASS: board framebuffer is byte-for-byte identical to zint640c12 sim" || \
	    (echo "FAIL: board framebuffer differs from zint640c12 sim"; cmp -l $(SH3_ZS640C12_BOARD_FB) $(SH3_ZS640C12_ZINT_FB) | sed -n '1,12p'; exit 1)
	@echo "=== compare board framebuffer vs replayed fragment colors ==="
	@$(PYTHON) $(REPO_ROOT)/tools/analyze_zsched_fb.py $(SH3_ZS640C12_BOARD_FB) \
	    --tag zs640c12 --owner replay-color --frags $(TRACE_DIR)/zs640c12_frags.txt

# Ch357 — TRIO regression (weak-depth, 384x381): capture the trio's authentic-Z fragments then run the ROP scoreboard.
tb_top_psmct32_sh3_ztrio_cap: dirs
	@echo "=== build tb_top_psmct32_sh3_ztrio_cap (Ch357 trio authentic-Z capture) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_ztrio.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_ztrio.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_ztrio_cap.vvp \
	    -s tb_top_psmct32_sh3_ztrio_cap \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_ztrio_cap.sv
	@echo "=== run tb_top_psmct32_sh3_ztrio_cap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_ztrio_cap.vvp

tb_top_psmct32_sh3_ztrio: tb_top_psmct32_sh3_ztrio_cap
	@echo "=== build tb_top_psmct32_sh3_ztrio (Ch357 trio ROP scoreboard) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_ztrio.vvp \
	    -s tb_top_psmct32_sh3_ztrio \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_ztrio.sv
	@echo "=== run tb_top_psmct32_sh3_ztrio ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_ztrio.vvp

# Ch356 accumulation-correctness gate: render ALL + each epoch in isolation (+ONLY=k +FBDUMP), then assert the joint
# ALL render == the composited isolation dumps BIT-FOR-BIT (compose_sched.py). This is the decisive scheduler proof.
tb_top_psmct32_sh3_sched_compose: tb_top_psmct32_sh3_sched
	@echo "=== Ch356 composition==isolated bit-for-bit gate ==="
	@cd $(TRACE_DIR) && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched.vvp +ONLY=ALL +FBDUMP=$(BUILD_DIR)/sched_fb_ALL.hex >/dev/null && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched.vvp +ONLY=0   +FBDUMP=$(BUILD_DIR)/sched_fb_0.hex   >/dev/null && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched.vvp +ONLY=1   +FBDUMP=$(BUILD_DIR)/sched_fb_1.hex   >/dev/null && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched.vvp +ONLY=2   +FBDUMP=$(BUILD_DIR)/sched_fb_2.hex   >/dev/null
	@python3 $(SIM_DIR)/../tools/compose_sched.py \
	  $(BUILD_DIR)/sched_fb_ALL.hex $(BUILD_DIR)/sched_fb_0.hex $(BUILD_DIR)/sched_fb_1.hex $(BUILD_DIR)/sched_fb_2.hex

# Ch357 — NATIVE 640x480 LPDDR framebuffer (scheduler unchanged; authentic screen coords, no union translation).
# LOCAL fixtures via gs_make_sh3_scheduler_fixture.py --fb640 --emit.
tb_top_psmct32_sh3_sched640: dirs
	@echo "=== build tb_top_psmct32_sh3_sched640 (Ch357 native 640x480) ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -I$(SIM_DIR)/data/top_psmct32_raster_demo \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sh3_s640.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sh3_s640.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_sh3_sched640.vvp \
	    -s tb_top_psmct32_sh3_sched640 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_sh3_sched640.sv
	@echo "=== run tb_top_psmct32_sh3_sched640 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched640.vvp

# Ch357 accumulation-correctness gate (bit-for-bit, full 640x480 frame).
tb_top_psmct32_sh3_sched640_compose: tb_top_psmct32_sh3_sched640
	@echo "=== Ch357 composition==isolated bit-for-bit gate (640x480) ==="
	@cd $(TRACE_DIR) && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched640.vvp +ONLY=ALL +FBDUMP=$(BUILD_DIR)/s640_fb_ALL.hex >/dev/null && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched640.vvp +ONLY=0   +FBDUMP=$(BUILD_DIR)/s640_fb_0.hex   >/dev/null && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched640.vvp +ONLY=1   +FBDUMP=$(BUILD_DIR)/s640_fb_1.hex   >/dev/null && \
	  $(VVP) $(BUILD_DIR)/tb_top_psmct32_sh3_sched640.vvp +ONLY=2   +FBDUMP=$(BUILD_DIR)/s640_fb_2.hex   >/dev/null
	@python3 $(SIM_DIR)/../tools/compose_sched.py --width 640 \
	  $(BUILD_DIR)/s640_fb_ALL.hex $(BUILD_DIR)/s640_fb_0.hex $(BUILD_DIR)/s640_fb_1.hex $(BUILD_DIR)/s640_fb_2.hex

# Ch345a — RUNTIME FEEDER textured-alpha SPRITE demo (sprite_mode staging + SPRITE_TEX_ALPHA). Setup bootlet
# uploads an 8x8 alpha texture + blue BG; the feeder streams 3 textured-alpha sprites over it.
tb_top_psmct32_feeder_sprite_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_sprite_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_sprite_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_sprite_setup.mem"' \
	    -DFEEDER_SPRITE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_sprite.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_sprite_demo.vvp \
	    -s tb_top_psmct32_feeder_sprite_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_sprite_demo.sv
	@echo "=== run tb_top_psmct32_feeder_sprite_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_sprite_demo.vvp

# Ch343 — LOCAL authentic-cube smoke (NOT in `run:`; needs dump-derived cube fixtures from
# `python3 tools/gs_make_cube_fixture.py`). Full boot: 64x64 cube texture upload (QWC=1030, 32 KiB EE
# RAM) + 27 perspective triangles through the S1 feeder path. De-risks the feeder_cube fit.
tb_top_psmct32_feeder_cube_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_feeder_cube_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_cube_setup.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_cube_setup.mem"' \
	    -DFEEDER_CUBE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_cube_persp.mem"' \
	    -DFEEDER_CUBE_TEX_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/feeder_cube_tex.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_feeder_cube_demo.vvp \
	    -s tb_top_psmct32_feeder_cube_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_feeder_cube_demo.sv
	@echo "=== run tb_top_psmct32_feeder_cube_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_feeder_cube_demo.vvp

tb_top_psmct32_tile_sprite18_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_sprite18_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_sprite18.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_sprite18.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_sprite18_demo.vvp \
	    -s tb_top_psmct32_tile_sprite18_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_sprite18_demo.sv
	@echo "=== run tb_top_psmct32_tile_sprite18_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_sprite18_demo.vvp

tb_top_psmct32_tile_cap64_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_cap64_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_cap64.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_cap64.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_cap64_demo.vvp \
	    -s tb_top_psmct32_tile_cap64_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_cap64_demo.sv
	@echo "=== run tb_top_psmct32_tile_cap64_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_cap64_demo.vvp

tb_top_psmct32_tile_cap_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_cap_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_cap.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_cap.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_cap_demo.vvp \
	    -s tb_top_psmct32_tile_cap_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_cap_demo.sv
	@echo "=== run tb_top_psmct32_tile_cap_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_cap_demo.vvp

tb_top_psmct32_tile_cap_overflow_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_cap_overflow_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_cap.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_cap.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_cap_overflow_demo.vvp \
	    -s tb_top_psmct32_tile_cap_overflow_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_cap_overflow_demo.sv
	@echo "=== run tb_top_psmct32_tile_cap_overflow_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_cap_overflow_demo.vvp

tb_top_psmct32_tile_late_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_late_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_late.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_late.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_late_demo.vvp \
	    -s tb_top_psmct32_tile_late_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_late_demo.sv
	@echo "=== run tb_top_psmct32_tile_late_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_late_demo.vvp

tb_top_psmct32_tile_lpddrfb_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_lpddrfb_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_psmct16fb.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_psmct16fb.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_lpddrfb_demo.vvp \
	    -s tb_top_psmct32_tile_lpddrfb_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_lpddrfb_demo.sv
	@echo "=== run tb_top_psmct32_tile_lpddrfb_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_lpddrfb_demo.vvp

tb_top_psmct32_tile_bin_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_bin_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_bin.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_bin.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_bin_demo.vvp \
	    -s tb_top_psmct32_tile_bin_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_bin_demo.sv
	@echo "=== run tb_top_psmct32_tile_bin_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_bin_demo.vvp

tb_top_psmct32_tile_bin4x4_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_bin4x4_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_bin4x4.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_bin4x4.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_bin4x4_demo.vvp \
	    -s tb_top_psmct32_tile_bin4x4_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_bin4x4_demo.sv
	@echo "=== run tb_top_psmct32_tile_bin4x4_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_bin4x4_demo.vvp

tb_top_psmct32_tile_psmct16fb_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_psmct16fb_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_psmct16fb.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_psmct16fb.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_psmct16fb_demo.vvp \
	    -s tb_top_psmct32_tile_psmct16fb_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_psmct16fb_demo.sv
	@echo "=== run tb_top_psmct32_tile_psmct16fb_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_psmct16fb_demo.vvp

tb_top_psmct32_tile_lpddr128_demo: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_tile_lpddr128_demo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tile_lpddr128.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tile_lpddr128.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_tile_lpddr128_demo.vvp \
	    -s tb_top_psmct32_tile_lpddr128_demo \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_tile_lpddr128_demo.sv
	@echo "=== run tb_top_psmct32_tile_lpddr128_demo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_tile_lpddr128_demo.vvp

# Textured-TRIANGLE demo on the BRAM board variant. Proves the
# textured-triangle rung (affine U/V into the texel-fetch path) renders
# through the BRAM VRAM the board top instantiates. Uses the tritex
# fixture (bios_tritex.mem / payload_tritex.mem) + PSMCT32_SWIZZLE=0.
tb_top_psmct32_raster_demo_bram_tritex: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_tritex ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tritex.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tritex.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_tritex.vvp \
	    -s tb_top_psmct32_raster_demo_bram_tritex \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_tritex.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_tritex ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_tritex.vvp

tb_top_psmct32_raster_demo_bram_lpddrtex: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_lpddrtex ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios_tritex.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload_tritex.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_lpddrtex.vvp \
	    -s tb_top_psmct32_raster_demo_bram_lpddrtex \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_lpddrtex.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_lpddrtex ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_lpddrtex.vvp

# Ch171 — spot-check TB for the 320x240 four-quadrant test card. Uses the
# Ch171 production fixtures (bios.mem / payload.mem) so its expectations
# match the synth/board build exactly. Instantiates the inner bram wrapper
# with board overrides (640x480 raster, 512 KiB VRAM) and probes a small
# set of inside/boundary/outside coordinates rather than every pixel.
tb_top_psmct32_raster_demo_bram_ch171: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_top_psmct32_raster_demo_bram_ch171 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload.mem"' \
	    -o $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_ch171.vvp \
	    -s tb_top_psmct32_raster_demo_bram_ch171 \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_raster_demo_bram_ch171.sv
	@echo "=== run tb_top_psmct32_raster_demo_bram_ch171 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_raster_demo_bram_ch171.vvp

# Ch172 — backpressure stress TB. Procedurally builds an 8-sprite GIF
# payload directly into ee_ram + bios_rom backings (no $readmemh image
# load) so the fixture .mem files don't need to grow. Asserts that
# gif_packed_stub.in_ready goes LOW at least once under FIFO_DEPTH=2 and
# that all 8 sprites still land in VRAM with raster_overflow=0.
# Ch173 — focused unit-test TB for the HPS↔fabric status bridge.
# Drives AXI4 reads directly + verifies the Ch173 register map
# (identity, CORE_STATUS, FRAME_COUNT, DMA_DONE_COUNT,
# RASTER_OVERFLOW_COUNT) + writes are ACK'd-and-ignored.
tb_ps2_hps_bridge: dirs
	@echo "=== build tb_ps2_hps_bridge ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ps2_hps_bridge.vvp \
	    -s tb_ps2_hps_bridge \
	    $(RTL_ROOT)/platform/ps2_hps_bridge.sv \
	    $(TB_ROOT)/platform/tb_ps2_hps_bridge.sv
	@echo "=== run tb_ps2_hps_bridge ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ps2_hps_bridge.vvp

tb_clut_stage_cdc: dirs
	@echo "=== build tb_clut_stage_cdc ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_clut_stage_cdc.vvp \
	    -s tb_clut_stage_cdc \
	    $(RTL_ROOT)/platform/clut_stage_cdc.sv \
	    $(TB_ROOT)/platform/tb_clut_stage_cdc.sv
	@echo "=== run tb_clut_stage_cdc ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_clut_stage_cdc.vvp

tb_top_psmct32_runtime_clut: dirs
	@echo "=== build tb_top_psmct32_runtime_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_top_psmct32_runtime_clut.vvp \
	    -s tb_top_psmct32_runtime_clut \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_top_psmct32_runtime_clut.sv
	@echo "=== run tb_top_psmct32_runtime_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_top_psmct32_runtime_clut.vvp

# Ch245 — focused unit-test for the platform-OSD cell adapter. Mocks
# the 32-bit-word tile_ram_cdc shadow and verifies the 32→16
# low/high-half mux returns the right cell for several pack patterns
# (low, high, mid-row, corner, unwritten-neighbor). Pure
# combinational adapter + a single register; no platform overlay
# instantiated. Cross-checks the integration glue introduced in
# rtl/top/de25_nano_psmct32_raster_demo_top.sv.
tb_osd_platform_cell_adapter: dirs
	@echo "=== build tb_osd_platform_cell_adapter ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_osd_platform_cell_adapter.vvp \
	    -s tb_osd_platform_cell_adapter \
	    $(TB_ROOT)/platform/tb_osd_platform_cell_adapter.sv
	@echo "=== run tb_osd_platform_cell_adapter ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_osd_platform_cell_adapter.vvp

# Ch229 — toggle-based bridge-clock → design-clock tile RAM CDC.
# Drives synthetic bridge writes at 100 MHz; verifies the 33 MHz
# design-side shadow RAM receives writes correctly through the 2-FF
# synchronizer + edge detector. Includes a static-toggle check
# proving writes are edge-triggered, not level-triggered.
tb_tile_ram_cdc: dirs
	@echo "=== build tb_tile_ram_cdc ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_tile_ram_cdc.vvp \
	    -s tb_tile_ram_cdc \
	    $(RTL_ROOT)/platform/tile_ram_cdc.sv \
	    $(TB_ROOT)/platform/tb_tile_ram_cdc.sv
	@echo "=== run tb_tile_ram_cdc ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_tile_ram_cdc.vvp

tb_gs_raster_backpressure_stress: dirs
	@echo "=== build tb_gs_raster_backpressure_stress ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='""' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='""' \
	    -o $(BUILD_DIR)/tb_gs_raster_backpressure_stress.vvp \
	    -s tb_gs_raster_backpressure_stress \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_gs_raster_backpressure_stress.sv
	@echo "=== run tb_gs_raster_backpressure_stress ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_backpressure_stress.vvp

tb_de25_nano_psmct32_raster_demo_top: dirs top_psmct32_raster_demo_mem
	@echo "=== build tb_de25_nano_psmct32_raster_demo_top ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DTOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/bios.mem"' \
	    -DTOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE='"$(SIM_DIR)/data/top_psmct32_raster_demo/payload.mem"' \
	    -o $(BUILD_DIR)/tb_de25_nano_psmct32_raster_demo_top.vvp \
	    -s tb_de25_nano_psmct32_raster_demo_top \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_de25_nano_psmct32_raster_demo_top.sv
	@echo "=== run tb_de25_nano_psmct32_raster_demo_top ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_de25_nano_psmct32_raster_demo_top.vvp

tb_hdmi_i2c_wake_smoke: dirs
	@echo "=== build tb_hdmi_i2c_wake_smoke ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_hdmi_i2c_wake_smoke.vvp \
	    -s tb_hdmi_i2c_wake_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/top/tb_hdmi_i2c_wake_smoke.sv
	@echo "=== run tb_hdmi_i2c_wake_smoke ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_hdmi_i2c_wake_smoke.vvp

tb_gs_scanout_swizzle_psmt8: dirs
	@echo "=== build tb_gs_scanout_swizzle_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt8.vvp \
	    -s tb_gs_scanout_swizzle_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmt8.sv
	@echo "=== run tb_gs_scanout_swizzle_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmt8.vvp

tb_gs_image_xfer_swizzle_psmt8: dirs
	@echo "=== build tb_gs_image_xfer_swizzle_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt8.vvp \
	    -s tb_gs_image_xfer_swizzle_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmt8.sv
	@echo "=== run tb_gs_image_xfer_swizzle_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmt8.vvp

tb_gs_raster_swizzle_psmt8: dirs
	@echo "=== build tb_gs_raster_swizzle_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_swizzle_psmt8.vvp \
	    -s tb_gs_raster_swizzle_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmt8.sv
	@echo "=== run tb_gs_raster_swizzle_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmt8.vvp

tb_gs_demo_psmt8_swizzle_e2e: dirs
	@echo "=== build tb_gs_demo_psmt8_swizzle_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_e2e.vvp \
	    -s tb_gs_demo_psmt8_swizzle_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt8_swizzle_e2e.sv
	@echo "=== run tb_gs_demo_psmt8_swizzle_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_e2e.vvp

tb_gs_demo_psmt8_swizzle_trxdir_e2e: dirs
	@echo "=== build tb_gs_demo_psmt8_swizzle_trxdir_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_trxdir_e2e.vvp \
	    -s tb_gs_demo_psmt8_swizzle_trxdir_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmt8_swizzle_trxdir_e2e.sv
	@echo "=== run tb_gs_demo_psmt8_swizzle_trxdir_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmt8_swizzle_trxdir_e2e.vvp

tb_gs_scanout_swizzle_psmct16: dirs
	@echo "=== build tb_gs_scanout_swizzle_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct16.vvp \
	    -s tb_gs_scanout_swizzle_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmct16.sv
	@echo "=== run tb_gs_scanout_swizzle_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct16.vvp

tb_gs_image_xfer_swizzle_psmct16: dirs
	@echo "=== build tb_gs_image_xfer_swizzle_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct16.vvp \
	    -s tb_gs_image_xfer_swizzle_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmct16.sv
	@echo "=== run tb_gs_image_xfer_swizzle_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct16.vvp

tb_gs_scanout_swizzle_psmct32: dirs
	@echo "=== build tb_gs_scanout_swizzle_psmct32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct32.vvp \
	    -s tb_gs_scanout_swizzle_psmct32 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_swizzle_psmct32.sv
	@echo "=== run tb_gs_scanout_swizzle_psmct32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_swizzle_psmct32.vvp

tb_gs_image_xfer_swizzle_psmct32: dirs
	@echo "=== build tb_gs_image_xfer_swizzle_psmct32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct32.vvp \
	    -s tb_gs_image_xfer_swizzle_psmct32 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_image_xfer_swizzle_psmct32.sv
	@echo "=== run tb_gs_image_xfer_swizzle_psmct32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_image_xfer_swizzle_psmct32.vvp

tb_gs_raster_swizzle_psmct32: dirs
	@echo "=== build tb_gs_raster_swizzle_psmct32 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_swizzle_psmct32.vvp \
	    -s tb_gs_raster_swizzle_psmct32 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmct32.sv
	@echo "=== run tb_gs_raster_swizzle_psmct32 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmct32.vvp

tb_gs_raster_swizzle_psmct16: dirs
	@echo "=== build tb_gs_raster_swizzle_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_swizzle_psmct16.vvp \
	    -s tb_gs_raster_swizzle_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_swizzle_psmct16.sv
	@echo "=== run tb_gs_raster_swizzle_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_swizzle_psmct16.vvp

tb_gs_raster_bram_psmct16: dirs
	@echo "=== build tb_gs_raster_bram_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_bram_psmct16.vvp \
	    -s tb_gs_raster_bram_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_bram_psmct16.sv
	@echo "=== run tb_gs_raster_bram_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_bram_psmct16.vvp

tb_gs_raster_bram_psmt8: dirs
	@echo "=== build tb_gs_raster_bram_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_bram_psmt8.vvp \
	    -s tb_gs_raster_bram_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_bram_psmt8.sv
	@echo "=== run tb_gs_raster_bram_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_bram_psmt8.vvp

tb_gs_raster_bram_psmt4: dirs
	@echo "=== build tb_gs_raster_bram_psmt4 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_raster_bram_psmt4.vvp \
	    -s tb_gs_raster_bram_psmt4 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_raster_bram_psmt4.sv
	@echo "=== run tb_gs_raster_bram_psmt4 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_raster_bram_psmt4.vvp

tb_gs_scanout_bram_psmct16: dirs
	@echo "=== build tb_gs_scanout_bram_psmct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_bram_psmct16.vvp \
	    -s tb_gs_scanout_bram_psmct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_bram_psmct16.sv
	@echo "=== run tb_gs_scanout_bram_psmct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_bram_psmct16.vvp

tb_gs_scanout_bram_psmt8: dirs
	@echo "=== build tb_gs_scanout_bram_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_bram_psmt8.vvp \
	    -s tb_gs_scanout_bram_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_bram_psmt8.sv
	@echo "=== run tb_gs_scanout_bram_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_bram_psmt8.vvp

tb_gs_demo_psmct32_swizzle_e2e: dirs
	@echo "=== build tb_gs_demo_psmct32_swizzle_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_e2e.vvp \
	    -s tb_gs_demo_psmct32_swizzle_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct32_swizzle_e2e.sv
	@echo "=== run tb_gs_demo_psmct32_swizzle_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_e2e.vvp

tb_gs_demo_psmct16_swizzle_e2e: dirs
	@echo "=== build tb_gs_demo_psmct16_swizzle_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_e2e.vvp \
	    -s tb_gs_demo_psmct16_swizzle_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct16_swizzle_e2e.sv
	@echo "=== run tb_gs_demo_psmct16_swizzle_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_e2e.vvp

tb_gs_demo_psmct16_swizzle_trxdir_e2e: dirs
	@echo "=== build tb_gs_demo_psmct16_swizzle_trxdir_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_trxdir_e2e.vvp \
	    -s tb_gs_demo_psmct16_swizzle_trxdir_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct16_swizzle_trxdir_e2e.sv
	@echo "=== run tb_gs_demo_psmct16_swizzle_trxdir_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct16_swizzle_trxdir_e2e.vvp

tb_gs_demo_psmct32_swizzle_trxdir_e2e: dirs
	@echo "=== build tb_gs_demo_psmct32_swizzle_trxdir_e2e ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_trxdir_e2e.vvp \
	    -s tb_gs_demo_psmct32_swizzle_trxdir_e2e \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_demo_psmct32_swizzle_trxdir_e2e.sv
	@echo "=== run tb_gs_demo_psmct32_swizzle_trxdir_e2e ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_demo_psmct32_swizzle_trxdir_e2e.vvp

tb_gs_scanout_psmt8: dirs
	@echo "=== build tb_gs_scanout_psmt8 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_psmt8.vvp \
	    -s tb_gs_scanout_psmt8 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psmt8.sv
	@echo "=== run tb_gs_scanout_psmt8 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psmt8.vvp

tb_gs_scanout_psmt8_clut: dirs
	@echo "=== build tb_gs_scanout_psmt8_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_psmt8_clut.vvp \
	    -s tb_gs_scanout_psmt8_clut \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psmt8_clut.sv
	@echo "=== run tb_gs_scanout_psmt8_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psmt8_clut.vvp

tb_gs_tex0_clut: dirs
	@echo "=== build tb_gs_tex0_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_tex0_clut.vvp \
	    -s tb_gs_tex0_clut \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_tex0_clut.sv
	@echo "=== run tb_gs_tex0_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_tex0_clut.vvp

tb_gs_clut_load: dirs
	@echo "=== build tb_gs_clut_load ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_clut_load.vvp \
	    -s tb_gs_clut_load \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load.sv
	@echo "=== run tb_gs_clut_load ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load.vvp

tb_gs_clut_load_ct16: dirs
	@echo "=== build tb_gs_clut_load_ct16 ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_clut_load_ct16.vvp \
	    -s tb_gs_clut_load_ct16 \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load_ct16.sv
	@echo "=== run tb_gs_clut_load_ct16 ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load_ct16.vvp

tb_gs_clut_load_cld_modes: dirs
	@echo "=== build tb_gs_clut_load_cld_modes ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_clut_load_cld_modes.vvp \
	    -s tb_gs_clut_load_cld_modes \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load_cld_modes.sv
	@echo "=== run tb_gs_clut_load_cld_modes ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load_cld_modes.vvp

tb_gs_clut_load_csa_window: dirs
	@echo "=== build tb_gs_clut_load_csa_window ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_clut_load_csa_window.vvp \
	    -s tb_gs_clut_load_csa_window \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_clut_load_csa_window.sv
	@echo "=== run tb_gs_clut_load_csa_window ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_clut_load_csa_window.vvp

tb_gs_scanout_psmt4_clut: dirs
	@echo "=== build tb_gs_scanout_psmt4_clut ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_scanout_psmt4_clut.vvp \
	    -s tb_gs_scanout_psmt4_clut \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_psmt4_clut.sv
	@echo "=== run tb_gs_scanout_psmt4_clut ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_psmt4_clut.vvp

tb_gs_psmt4_round_trip: dirs
	@echo "=== build tb_gs_psmt4_round_trip ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_gs_psmt4_round_trip.vvp \
	    -s tb_gs_psmt4_round_trip \
	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_psmt4_round_trip.sv
	@echo "=== run tb_gs_psmt4_round_trip ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_psmt4_round_trip.vvp

tb_intc: dirs
	@echo "=== build tb_intc_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_intc_stub.vvp \
	    -s tb_intc_stub \
	    $(RTL_SRCS) $(TB_ROOT)/intc/tb_intc_stub.sv
	@echo "=== run tb_intc_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_intc_stub.vvp

tb_platform_video: dirs
	@echo "=== build tb_platform_video_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_platform_video_stub.vvp \
	    -s tb_platform_video_stub \
	    $(RTL_SRCS) $(TB_ROOT)/platform/tb_platform_video_stub.sv
	@echo "=== run tb_platform_video_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_platform_video_stub.vvp

tb_bgcolor_via_dma: dirs
	@echo "=== build tb_bgcolor_via_dma ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_bgcolor_via_dma.vvp \
	    -s tb_bgcolor_via_dma \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_bgcolor_via_dma.sv
	@echo "=== run tb_bgcolor_via_dma ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_bgcolor_via_dma.vvp

tb_sif_mailbox: dirs
	@echo "=== build tb_sif_mailbox_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_mailbox_stub.vvp \
	    -s tb_sif_mailbox_stub \
	    $(RTL_SRCS) $(TB_ROOT)/sif/tb_sif_mailbox_stub.sv
	@echo "=== run tb_sif_mailbox_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_mailbox_stub.vvp

tb_sif_command_echo: dirs
	@echo "=== build tb_sif_command_echo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_command_echo.vvp \
	    -s tb_sif_command_echo \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_command_echo.sv
	@echo "=== run tb_sif_command_echo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_command_echo.vvp

tb_sif_command_echo_rearm: dirs
	@echo "=== build tb_sif_command_echo_rearm ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_command_echo_rearm.vvp \
	    -s tb_sif_command_echo_rearm \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_command_echo_rearm.sv
	@echo "=== run tb_sif_command_echo_rearm ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_command_echo_rearm.vvp

tb_sif_negative_path: dirs
	@echo "=== build tb_sif_negative_path ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_negative_path.vvp \
	    -s tb_sif_negative_path \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_negative_path.sv
	@echo "=== run tb_sif_negative_path ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_negative_path.vvp

tb_sif_dma_smoke: dirs
	@echo "=== build tb_sif_dma_smoke ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_dma_smoke.vvp \
	    -s tb_sif_dma_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_dma_smoke.sv
	@echo "=== run tb_sif_dma_smoke ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_dma_smoke.vvp

tb_sif_dma_mid_stall: dirs
	@echo "=== build tb_sif_dma_mid_stall ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_dma_mid_stall.vvp \
	    -s tb_sif_dma_mid_stall \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_dma_mid_stall.sv
	@echo "=== run tb_sif_dma_mid_stall ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_dma_mid_stall.vvp

tb_sif_dma_overflow: dirs
	@echo "=== build tb_sif_dma_overflow ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_dma_overflow.vvp \
	    -s tb_sif_dma_overflow \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_dma_overflow.sv
	@echo "=== run tb_sif_dma_overflow ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_dma_overflow.vvp

tb_sif_combined_ctrl_data: dirs
	@echo "=== build tb_sif_combined_ctrl_data ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_combined_ctrl_data.vvp \
	    -s tb_sif_combined_ctrl_data \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_combined_ctrl_data.sv
	@echo "=== run tb_sif_combined_ctrl_data ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_combined_ctrl_data.vvp

tb_iop_ram: dirs
	@echo "=== build tb_iop_ram_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_ram_stub.vvp \
	    -s tb_iop_ram_stub \
	    $(RTL_SRCS) $(TB_ROOT)/iop/tb_iop_ram_stub.sv
	@echo "=== run tb_iop_ram_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_ram_stub.vvp

tb_iop_memory_map: dirs
	@echo "=== build tb_iop_memory_map_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_memory_map_stub.vvp \
	    -s tb_iop_memory_map_stub \
	    $(RTL_SRCS) $(TB_ROOT)/iop/tb_iop_memory_map_stub.sv
	@echo "=== run tb_iop_memory_map_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_memory_map_stub.vvp

# Ch261 — focused arbitration test for the deferred-CPU-RAM-read slot
# added to iop_memory_map_stub. Drives CPU and DMA reads to different
# addresses on the same cycle and asserts DMA wins immediately while
# CPU's read services one cycle later via the pending slot.
tb_iop_memory_map_collision: dirs
	@echo "=== build tb_iop_memory_map_collision ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_memory_map_collision.vvp \
	    -s tb_iop_memory_map_collision \
	    $(RTL_SRCS) $(TB_ROOT)/iop/tb_iop_memory_map_collision.sv
	@echo "=== run tb_iop_memory_map_collision ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_memory_map_collision.vvp

# Ch234 — focused unit-test TB for sio2_input_stub. Drives the stub
# directly (without the IOP map) and verifies the active-high→active-low
# Sony pad-word translation, P1/P2 independence, PAD_STATUS, and
# write-ignored contract.
tb_sio2_input_stub: dirs
	@echo "=== build tb_sio2_input_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sio2_input_stub.vvp \
	    -s tb_sio2_input_stub \
	    $(RTL_ROOT)/iop/sio2_input_stub.sv \
	    $(TB_ROOT)/iop/tb_sio2_input_stub.sv
	@echo "=== run tb_sio2_input_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sio2_input_stub.vvp

# Ch235 — bridge + IOP integration TB. Wires ps2_hps_bridge → iop_map
# across two distinct clocks (100 MHz bridge, 33 MHz IOP); TB drives
# AXI writes to INPUT_P1/P2 at 0x040/0x044 and reads PAD_P1/P2_STATE
# at 0x1F80_8500/0x1F80_8504. Verifies the full end-to-end input
# path including the bridge-clk → IOP-clk CDC inside sio2_input_stub.
tb_bridge_iop_pad_input: dirs
	@echo "=== build tb_bridge_iop_pad_input ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_bridge_iop_pad_input.vvp \
	    -s tb_bridge_iop_pad_input \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_bridge_iop_pad_input.sv
	@echo "=== run tb_bridge_iop_pad_input ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_bridge_iop_pad_input.vvp

tb_lpddr_tex_staging: dirs
	@echo "=== build tb_lpddr_tex_staging ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_lpddr_tex_staging.vvp \
	    -s tb_lpddr_tex_staging \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_lpddr_tex_staging.sv
	@echo "=== run tb_lpddr_tex_staging ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_lpddr_tex_staging.vvp

# Ch238 — pad-state via SIF DMA to EE RAM integration TB. Wires
# ps2_hps_bridge → iop_memory_map_stub (PAD_P1_STATE) +
# sif_dma_ee_ram_bridge_stub → ee_memory_map_stub → ee_ram_stub. TB
# drives AXI writes to INPUT_P1, reads the Sony pad word from the
# IOP map, packs a 16-byte libpad-compatible buffer into 4 SIF beats,
# and verifies the qword that lands in EE RAM at the agreed
# EE_PAD_BUFFER_BASE = 0x0008_0000. No new production RTL —
# composes existing primitives end-to-end.
tb_pad_state_via_sif_to_ee: dirs
	@echo "=== build tb_pad_state_via_sif_to_ee ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_pad_state_via_sif_to_ee.vvp \
	    -s tb_pad_state_via_sif_to_ee \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_pad_state_via_sif_to_ee.sv
	@echo "=== run tb_pad_state_via_sif_to_ee ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_pad_state_via_sif_to_ee.vvp

# Ch240 — EE-side pad-buffer consumer integration TB. Adds an ee_core_stub
# + bios_rom_stub to the Ch239 pad-transfer harness. EE program is loaded
# into BIOS at the reset vector; it loops reading byte 3 of the pad buffer
# at EE_PAD_BUFFER_BASE and branches to one of three markers (A/B/C) based
# on the controller state. TB drives 4 scenarios (no buttons / RIGHT only /
# RIGHT+SELECT / re-clear) and verifies the marker bytes the EE wrote.
tb_ee_pad_buffer_branch: dirs
	@echo "=== build tb_ee_pad_buffer_branch ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_pad_buffer_branch.vvp \
	    -s tb_ee_pad_buffer_branch \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_pad_buffer_branch.sv
	@echo "=== run tb_ee_pad_buffer_branch ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_pad_buffer_branch.vvp

tb_iop_fetch_through_map: dirs
	@echo "=== build tb_iop_fetch_through_map ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_fetch_through_map.vvp \
	    -s tb_iop_fetch_through_map \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_fetch_through_map.sv
	@echo "=== run tb_iop_fetch_through_map ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_fetch_through_map.vvp

tb_sif_iop_bridge_smoke: dirs
	@echo "=== build tb_sif_iop_bridge_smoke ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_iop_bridge_smoke.vvp \
	    -s tb_sif_iop_bridge_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_iop_bridge_smoke.sv
	@echo "=== run tb_sif_iop_bridge_smoke ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_iop_bridge_smoke.vvp

tb_sif_iop_bridge_exec: dirs
	@echo "=== build tb_sif_iop_bridge_exec ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_iop_bridge_exec.vvp \
	    -s tb_sif_iop_bridge_exec \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_iop_bridge_exec.sv
	@echo "=== run tb_sif_iop_bridge_exec ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_iop_bridge_exec.vvp

tb_iop_to_sif_via_map: dirs
	@echo "=== build tb_iop_to_sif_via_map ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_to_sif_via_map.vvp \
	    -s tb_iop_to_sif_via_map \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_to_sif_via_map.sv
	@echo "=== run tb_iop_to_sif_via_map ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_to_sif_via_map.vvp

tb_iop_dmac_via_map: dirs
	@echo "=== build tb_iop_dmac_via_map ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_dmac_via_map.vvp \
	    -s tb_iop_dmac_via_map \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_dmac_via_map.sv
	@echo "=== run tb_iop_dmac_via_map ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_dmac_via_map.vvp

tb_sif_ee_landing_via_dmac: dirs
	@echo "=== build tb_sif_ee_landing_via_dmac ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_ee_landing_via_dmac.vvp \
	    -s tb_sif_ee_landing_via_dmac \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_ee_landing_via_dmac.sv
	@echo "=== run tb_sif_ee_landing_via_dmac ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_ee_landing_via_dmac.vvp

tb_sif_iop_driven_combined: dirs
	@echo "=== build tb_sif_iop_driven_combined ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_sif_iop_driven_combined.vvp \
	    -s tb_sif_iop_driven_combined \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_sif_iop_driven_combined.sv
	@echo "=== run tb_sif_iop_driven_combined ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_sif_iop_driven_combined.vvp

tb_ee_dmac_intc: dirs
	@echo "=== build tb_ee_dmac_intc ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_dmac_intc.vvp \
	    -s tb_ee_dmac_intc \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_dmac_intc.sv
	@echo "=== run tb_ee_dmac_intc ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_dmac_intc.vvp

tb_iop_dmac_intc: dirs
	@echo "=== build tb_iop_dmac_intc ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_dmac_intc.vvp \
	    -s tb_iop_dmac_intc \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_dmac_intc.sv
	@echo "=== run tb_iop_dmac_intc ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_dmac_intc.vvp

tb_iop_self_driven: dirs
	@echo "=== build tb_iop_self_driven ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_self_driven.vvp \
	    -s tb_iop_self_driven \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_self_driven.sv
	@echo "=== run tb_iop_self_driven ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_self_driven.vvp

# Ch261 — IOP responder skeleton. Composes iop_exec_stub + iop map
# + iop_ram + iop_dmac (ch9) + sif_dma_ee_ram_bridge_stub + ee_ram_stub
# to prove the IOP can produce one EE-visible side effect autonomously
# from a single go_i pulse. Foundation for Ch262 (wire into BIOS-long).
tb_iop_responder_ee_ram_landing: dirs
	@echo "=== build tb_iop_responder_ee_ram_landing ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_responder_ee_ram_landing.vvp \
	    -s tb_iop_responder_ee_ram_landing \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_responder_ee_ram_landing.sv
	@echo "=== run tb_iop_responder_ee_ram_landing ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_responder_ee_ram_landing.vvp

tb_iop_autonomous_two_xfers: dirs
	@echo "=== build tb_iop_autonomous_two_xfers ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_autonomous_two_xfers.vvp \
	    -s tb_iop_autonomous_two_xfers \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_autonomous_two_xfers.sv
	@echo "=== run tb_iop_autonomous_two_xfers ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_autonomous_two_xfers.vvp

tb_iop_core_basic: dirs
	@echo "=== build tb_iop_core_basic ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_core_basic.vvp \
	    -s tb_iop_core_basic \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_basic.sv
	@echo "=== run tb_iop_core_basic ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_basic.vvp

tb_iop_core_interrupts: dirs
	@echo "=== build tb_iop_core_interrupts ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_core_interrupts.vvp \
	    -s tb_iop_core_interrupts \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_interrupts.sv
	@echo "=== run tb_iop_core_interrupts ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_interrupts.vvp

tb_iop_core_bootstrap: dirs
	@echo "=== build tb_iop_core_bootstrap ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_core_bootstrap.vvp \
	    -s tb_iop_core_bootstrap \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_bootstrap.sv
	@echo "=== run tb_iop_core_bootstrap ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_bootstrap.vvp

tb_iop_core_bootstrap_intc: dirs
	@echo "=== build tb_iop_core_bootstrap_intc ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_core_bootstrap_intc.vvp \
	    -s tb_iop_core_bootstrap_intc \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_bootstrap_intc.sv
	@echo "=== run tb_iop_core_bootstrap_intc ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_bootstrap_intc.vvp

# BIOS iteration: set BIOS=<path> on the command line to point the
# smoke harness at a real BIOS hex image (one 32-bit word per line, no
# 0x prefix — see sim/golden/bin_to_hex.py to convert a .bin dump).
# Relative paths are resolved against the repo root so the user can
# drop a dump anywhere and reference it consistently.
#   make tb_iop_core_bios_smoke                          # synthetic (CI)
#   make tb_iop_core_bios_smoke BIOS=/tmp/ps2_bios.hex   # real iteration
BIOS ?=
BIOS_ABS := $(if $(BIOS),$(abspath $(BIOS)))
BIOS_PLUSARG := $(if $(BIOS_ABS),+BIOS=$(BIOS_ABS))

# Ch40 diagnostic preload of a `JR $31; NOP` stub at useg 0xC0 (see
# tb_ee_core_bios_smoke.sv "Chapter 40" block). Opt-in so the
# baseline real-BIOS run still exhibits the pre-stub install-gap
# failure (trap at pc=0x200). Enable with CH40_STUB=1 on the make
# command line.
CH40_STUB ?=
CH40_STUB_PLUSARG := $(if $(CH40_STUB),+CH40_STUB)

# Ch49 alignment-exception mode: when set, tb_ee_core_bios_smoke
# compiles ee_core_stub with TRAP_ALIGN_ERROR=1'b0 so misaligned
# SW/LW/SH/LH/LHU vector to EXC_VECTOR through the standard MIPS
# exception path instead of halting. Debugging aid for real-BIOS
# iteration only — the per-TB focused benches (tb_ee_core_align,
# tb_ee_core_align_exc) set the parameter directly and ignore this
# flag.
CH49_ALIGN_EXC ?=
CH49_ALIGN_EXC_DEFINE := $(if $(CH49_ALIGN_EXC),-DCH49_ALIGN_EXC)

# Ch64 narrow useg->ee_ram CPU-write mirror. When set, the bios-smoke
# build compiles with `CH64_USEG_MIRROR defined, which causes the TB's
# u_ee_map instantiation to override CPU_USEG_TO_RAM_MIRROR_EN to 1
# for the phys window [0x00044000..0x00044700). Experimental; default
# off to keep the Ch33 de-aliased model intact for every other test.
CH64_USEG_MIRROR ?=
CH64_USEG_MIRROR_DEFINE := $(if $(CH64_USEG_MIRROR),-DCH64_USEG_MIRROR)

# Ch65 narrow kseg0->useg_shadow CPU-write mirror (symmetric to Ch64).
# When set, the bios-smoke build compiles with `CH65_KSEG_MIRROR
# defined, and the TB overrides u_ee_map's
# CPU_KSEG0_TO_USEG_SHADOW_MIRROR_EN to 1 for phys window
# [0x001A4000..0x001A5000). Default off.
CH65_KSEG_MIRROR ?=
CH65_KSEG_MIRROR_DEFINE := $(if $(CH65_KSEG_MIRROR),-DCH65_KSEG_MIRROR)

# Ch70 — single coherent RAM-alias mode covering [0..4MiB), bidirectional.
# Subsumes the legacy Ch64+Ch65 narrow knobs when set. Default off; same
# regression compatibility story.
#   make ... BIOS=... CH49_ALIGN_EXC=1 CH55_INSTALL=1 CH70_RAM_ALIAS=1
CH70_RAM_ALIAS ?=
CH70_RAM_ALIAS_DEFINE := $(if $(CH70_RAM_ALIAS),-DCH70_RAM_ALIAS)

# Ch71 — patient progress runner. Compiles the same bios-smoke TB
# with -DCH71_LONG_RUN, which bumps the timeout 10x and gates the
# heaviest observer (LOOP_RING per-retire writes + tail print).
# Default off; only set by the tb_ee_core_bios_long target below.
CH71_LONG_RUN ?=
CH71_LONG_RUN_DEFINE := $(if $(CH71_LONG_RUN),-DCH71_LONG_RUN)

# Ch52 diagnostic preload of a minimal AdES/AdEL exception handler
# stub at useg_shadow[0x80..0x8C] (see tb_ee_core_bios_smoke.sv
# "Chapter 52" block). 4-instruction handler skips the faulting
# instruction via EPC+=4 and RFEs back. Forwarded as +CH52_EXC_STUB
# plusarg. Requires CH40_STUB=1 CH49_ALIGN_EXC=1 to reach the fault
# point in the first place. Opt-in diagnostic only.
CH52_EXC_STUB ?=
CH52_EXC_STUB_PLUSARG := $(if $(CH52_EXC_STUB),+CH52_EXC_STUB)

# Ch53 intermediate-richness variant: saves EPC/BadVAddr/Cause into
# useg 0xA8/0xAC/0xB0 before EPC+=4 + RFE. Designed to answer "does
# the BIOS care about the handler bytes beyond mere presence?" —
# if CH53_EXC_STUB advances the BIOS meaningfully further than
# CH52_EXC_STUB, install-source modeling (SIF/IOP) is next; if not,
# handler semantics need work. If both are set, CH53 wins (both
# initial blocks fire on the same r31_to_target edge).
CH53_EXC_STUB ?=
CH53_EXC_STUB_PLUSARG := $(if $(CH53_EXC_STUB),+CH53_EXC_STUB)

# Ch54 atomic coordinated install for useg 0x80..0x1FF. Single
# coherent image: AdES handler at 0x80..0x8C, (JR $31; NOP) pairs
# filling 0x90..0x1FC. Tests whether the BIOS's RAM-handler
# install is primarily about coordinated coverage of the whole
# shared surface (exception entry + ch37 dispatch targets at
# 0xB0/0xC0 + runway slots). Opt-in CH54_BLOB=1 on make command
# line.  Supersedes CH40/CH52 content for overlapping slots.
CH54_BLOB ?=
CH54_BLOB_PLUSARG := $(if $(CH54_BLOB),+CH54_BLOB)

# Ch55 external install seam: instantiate the boot_install_agent_stub
# + sif_dma_ee_ram_bridge_stub inside tb_ee_core_bios_smoke, pulse the
# agent before core_go, and let it stream the Ch54-image payload into
# useg_shadow via the real SIF bridge-write port. No TB direct poke
# into useg_shadow_mem for the installed region. Opt-in CH55_INSTALL=1
# on make. Do not combine with CH54_BLOB (they would both populate
# the same image but via different seams; pick one).
CH55_INSTALL ?=
CH55_INSTALL_PLUSARG := $(if $(CH55_INSTALL),+CH55_INSTALL)

# Ch56 runtime image override for the boot_install_agent_stub payload
# in tb_ee_core_bios_smoke. Transport is unchanged; the TB's opt-in
# initial block uses $readmemh to overwrite u_install_agent.payload
# before the install agent is pulsed. Requires CH55_INSTALL=1.
#   make ... CH55_INSTALL=1 CH56_IMAGE=$(SIM_DIR)/data/ch56_ch54_equivalent.mem
CH56_IMAGE ?=
CH56_IMAGE_ABS := $(if $(CH56_IMAGE),$(abspath $(CH56_IMAGE)))
CH56_IMAGE_PLUSARG := $(if $(CH56_IMAGE_ABS),+CH56_IMAGE=$(CH56_IMAGE_ABS))

tb_iop_core_bios_smoke: dirs
	@echo "=== build tb_iop_core_bios_smoke ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_iop_core_bios_smoke.vvp \
	    -s tb_iop_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_iop_core_bios_smoke.sv
	@echo "=== run tb_iop_core_bios_smoke ==="
	@if [ -n "$(BIOS_ABS)" ]; then \
	    echo "    real BIOS: $(BIOS_ABS)"; \
	fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_iop_core_bios_smoke.vvp $(BIOS_PLUSARG)

tb_ee_core_basic: dirs
	@echo "=== build tb_ee_core_basic ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_basic.vvp \
	    -s tb_ee_core_basic \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_basic.sv
	@echo "=== run tb_ee_core_basic ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_basic.vvp

tb_ee_core_memops: dirs
	@echo "=== build tb_ee_core_memops ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_memops.vvp \
	    -s tb_ee_core_memops \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_memops.sv
	@echo "=== run tb_ee_core_memops ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_memops.vvp

tb_ee_core_dmac: dirs
	@echo "=== build tb_ee_core_dmac ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_dmac.vvp \
	    -s tb_ee_core_dmac \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dmac.sv
	@echo "=== run tb_ee_core_dmac ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dmac.vvp

tb_ee_core_dmac_poll: dirs
	@echo "=== build tb_ee_core_dmac_poll ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_dmac_poll.vvp \
	    -s tb_ee_core_dmac_poll \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dmac_poll.sv
	@echo "=== run tb_ee_core_dmac_poll ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dmac_poll.vvp

tb_ee_core_dmac_intc: dirs
	@echo "=== build tb_ee_core_dmac_intc ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_dmac_intc.vvp \
	    -s tb_ee_core_dmac_intc \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dmac_intc.sv
	@echo "=== run tb_ee_core_dmac_intc ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dmac_intc.vvp

# The same BIOS=/path/to/bios.hex plusarg convention used by the IOP-side
# smoke (see tb_iop_core_bios_smoke rule above) — BIOS_ABS and
# BIOS_PLUSARG already defined there. Leave this target in the same mode
# so `make tb_ee_core_bios_smoke BIOS=...` works the same way.
tb_ee_core_bios_smoke: dirs
	@echo "=== build tb_ee_core_bios_smoke ==="
	$(IVERILOG) $(IVERILOG_FLGS) $(CH49_ALIGN_EXC_DEFINE) $(CH64_USEG_MIRROR_DEFINE) $(CH65_KSEG_MIRROR_DEFINE) $(CH70_RAM_ALIAS_DEFINE) \
	    -o $(BUILD_DIR)/tb_ee_core_bios_smoke.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_smoke ==="
	@if [ -n "$(BIOS_ABS)" ]; then \
	    echo "    real BIOS: $(BIOS_ABS)"; \
	fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_smoke.vvp $(BIOS_PLUSARG) $(CH40_STUB_PLUSARG) $(CH52_EXC_STUB_PLUSARG) $(CH53_EXC_STUB_PLUSARG) $(CH54_BLOB_PLUSARG) $(CH55_INSTALL_PLUSARG) $(CH56_IMAGE_PLUSARG)

# Ch71 — patient progress runner. Reuses the same TB source compiled
# with the bring-up bring-up defines + CH71_LONG_RUN to bump timeout
# and trim the heaviest observer. Build artifact is separate so the
# main smoke build is undisturbed.
#   make tb_ee_core_bios_long BIOS=/path/to/bios.hex
tb_ee_core_bios_long: dirs
	@echo "=== build tb_ee_core_bios_long (=tb_ee_core_bios_smoke + CH49_ALIGN_EXC + CH70_RAM_ALIAS + CH71_LONG_RUN + CH215_JMPBUF_RESTORE) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long ==="
	@if [ -n "$(BIOS_ABS)" ]; then \
	    echo "    real BIOS: $(BIOS_ABS)"; \
	fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch260 — opt-in INTC diagnostic build. Same TB + same defines as
# tb_ee_core_bios_long, plus -DCH259_INTC_DIAG which unmutes the
# compact INTC transaction observer ([ch218] lines) gated off in the
# routine build. Closed-arc artefact: routine BIOS runs no longer
# need to wade through the observer output, but the compile-time
# knob is preserved for any future BIOS-mmio probe revival.
#   make tb_ee_core_bios_long_intc_diag BIOS=/path/to/bios.hex
#   ... or with synthetic source bit injection:
#   make tb_ee_core_bios_long_intc_diag BIOS=... IOP_INTC_BOOT_SRC=0001
.PHONY: tb_ee_core_bios_long_intc_diag
tb_ee_core_bios_long_intc_diag: dirs
	@echo "=== build tb_ee_core_bios_long_intc_diag (=tb_ee_core_bios_long + CH259_INTC_DIAG) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH259_INTC_DIAG \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_intc_diag.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_intc_diag ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@if [ -n "$(IOP_INTC_BOOT_SRC)" ]; then echo "    IOP_INTC_BOOT_SRC=$(IOP_INTC_BOOT_SRC)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_intc_diag.vvp $(BIOS_PLUSARG) +CH55_INSTALL \
	    $(if $(IOP_INTC_BOOT_SRC),+IOP_INTC_BOOT_SRC=$(IOP_INTC_BOOT_SRC))

# Ch262 — BIOS-long + Ch259 INTC observer + Ch262 synthetic IOP
# responder. The responder runs once mid-treadmill (~50 ms sim time)
# and emits a 1-cycle pulse on bridge.last_seen rising edge that ORs
# into the EE-side iop_intc_inject_src_i path. Designed to answer
# whether a timed, causally linked IOP-side event changes BIOS
# behaviour relative to the Ch260 baseline. Opt-in/diagnostic only —
# routine tb_ee_core_bios_long is unaffected.
.PHONY: tb_ee_core_bios_long_iop_responder
tb_ee_core_bios_long_iop_responder: dirs
	@echo "=== build tb_ee_core_bios_long_iop_responder (=tb_ee_core_bios_long + CH259_INTC_DIAG + CH262_IOP_RESPONDER) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH259_INTC_DIAG -DCH262_IOP_RESPONDER \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_iop_responder.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_iop_responder ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_iop_responder.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch263 — Ch262 + retarget the responder DMA into the BIOS-polled
# kernel-data scan range (EE virt 0x80030200 / phys 0x00030200). The
# Ch262 INTC pulse path is preserved; the responder now ALSO leaves a
# real EE-RAM mutation at a slot BIOS empirically scans every pass.
# Three-way verdict: kernel_mutation_unobserved / observed_no_flow /
# perturbed_flow. Cross-reference with Ch217 verdict for the flow
# change call.
.PHONY: tb_ee_core_bios_long_kernel_mutate
tb_ee_core_bios_long_kernel_mutate: dirs
	@echo "=== build tb_ee_core_bios_long_kernel_mutate (=tb_ee_core_bios_long_iop_responder + CH263_KERNEL_DATA_MUTATE) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH259_INTC_DIAG -DCH262_IOP_RESPONDER -DCH263_KERNEL_DATA_MUTATE \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_kernel_mutate.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_kernel_mutate ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_kernel_mutate.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch264 — narrow callee-read autopsy. Re-uses the BIOS-long flow with
# the Ch218-style observer scoped to the longjmp-return callee body at
# 0xBFC52984..0xBFC52A04 (Codex's candidate C). Captures every data
# read in that PC range (sampled directly from ee_rd_data, not the
# arg1-zeroed event), tags each with the region classifier (ev_arg3),
# and on exit emits the ordered stream + a dedup table that flags the
# stable polled address(es) the callee gates on. Off by default.
#   make tb_ee_core_bios_long_callee_autopsy BIOS=/path/to/bios.hex
.PHONY: tb_ee_core_bios_long_callee_autopsy
tb_ee_core_bios_long_callee_autopsy: dirs
	@echo "=== build tb_ee_core_bios_long_callee_autopsy (=tb_ee_core_bios_long + CH264_CALLEE_AUTOPSY) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH264_CALLEE_AUTOPSY \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_callee_autopsy.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_callee_autopsy ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_callee_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch265 — helper-body autopsy at 0xBFC4D370..0xBFC4D470 (one frame
# deeper than Ch264). Re-uses the Ch264 capture pattern with
# additions: control-flow tracking (J/JAL/JR/JALR retires inside
# helper, with statically-decoded J/JAL targets and "LEAVES helper"
# notes), per-invocation $a0-in / $v0-out / $v1-out snapshots,
# 5-way verdict (helper_static_{mmio,ram}_gate_found,
# helper_no_data_reads, helper_is_thunk, helper_reads_vary_but_flow_static).
# Off by default.
#   make tb_ee_core_bios_long_helper_autopsy BIOS=/path/to/bios.hex
.PHONY: tb_ee_core_bios_long_helper_autopsy
tb_ee_core_bios_long_helper_autopsy: dirs
	@echo "=== build tb_ee_core_bios_long_helper_autopsy (=tb_ee_core_bios_long + CH265_HELPER_AUTOPSY) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH265_HELPER_AUTOPSY \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_helper_autopsy.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_helper_autopsy ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_helper_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch266 — dispatcher autopsy at 0xBFC4F320..0xBFC4F520 (one frame
# deeper than Ch265; widened to 0x200 = 128 instructions because
# this is suspected to be the real dispatcher body, not a thunk).
# Upgrades over Ch265: captures WRITES as well as reads, snapshots
# $sp on entry, groups by $a0 selector, and applies a stack-frame
# filter (discount EAs in $sp..$sp+0x40 and values matching any
# captured $ra_in). New verdict label `dispatcher_selector_table_found`
# detects function-pointer-table lookups where read EAs scale as
# base + $a0 * K. Off by default.
#   make tb_ee_core_bios_long_dispatcher_autopsy BIOS=/path/to/bios.hex
.PHONY: tb_ee_core_bios_long_dispatcher_autopsy
tb_ee_core_bios_long_dispatcher_autopsy: dirs
	@echo "=== build tb_ee_core_bios_long_dispatcher_autopsy (=tb_ee_core_bios_long + CH266_DISPATCHER_AUTOPSY) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH266_DISPATCHER_AUTOPSY \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_dispatcher_autopsy.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_dispatcher_autopsy ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_dispatcher_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch267 Phase 1 — passive observer keyed on physical address
# 0x0000A8C8 (the gate STORAGE found by Ch266). Accepts all three
# kseg/kuseg aliases. Classifies each access as clearer (write 0,
# especially from the Ch266 dispatcher PC window), writer (non-zero
# write), or poller (read). Suppresses dispatcher clears beyond the
# first per Ch217 pass to keep the stream readable. Verdicts:
# gate_only_cleared_never_polled, gate_polled_zero_no_writer,
# gate_nonzero_writer_found, gate_alias_mismatch, gate_no_traffic.
# Off by default.
#   make tb_ee_core_bios_long_gate_observer BIOS=/path/to/bios.hex
.PHONY: tb_ee_core_bios_long_gate_observer
tb_ee_core_bios_long_gate_observer: dirs
	@echo "=== build tb_ee_core_bios_long_gate_observer (=tb_ee_core_bios_long + CH267_GATE_OBSERVER) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH267_GATE_OBSERVER \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_gate_observer.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_gate_observer ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_gate_observer.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch268 — widened read autopsy for the longjmp-return OUTER CALLER
# body (PC 0xBFC52340..0xBFC52400). After Ch267 ruled out
# 0xA000A8C8, this scans every non-fetch READ the outer caller
# emits across treadmill passes, buckets by alias-normalized phys
# EA, and reports per-bucket PCs, per-pass values, alias mask, and
# stack-filtered gate verdict. 5-way verdicts:
# outer_static_{mmio,ram}_gate_found, outer_only_stack_reads,
# outer_no_reads, outer_reads_vary_but_flow_static. Off by default.
#   make tb_ee_core_bios_long_outer_read_autopsy BIOS=/path/to/bios.hex
.PHONY: tb_ee_core_bios_long_outer_read_autopsy
tb_ee_core_bios_long_outer_read_autopsy: dirs
	@echo "=== build tb_ee_core_bios_long_outer_read_autopsy (=tb_ee_core_bios_long + CH268_OUTER_READ_AUTOPSY) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH268_OUTER_READ_AUTOPSY \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_outer_read_autopsy.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_outer_read_autopsy ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_outer_read_autopsy.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch269 — $v0 lineage check (Codex's hard-stop chapter). Taps
# u_core.regfile[2] every cycle, captures each change with the
# FSM state at the prior cycle (the state that drove the write).
# Verdict v0_set_by_ch215_restore confirms the BEQ-at-0xBFC52350
# treadmill is an artifact of our Ch215 jmp_buf restore shim, not
# a hidden BIOS load — closing the post-Ch215 thunk-chain search.
# Off by default.
#   make tb_ee_core_bios_long_v0_lineage BIOS=/path/to/bios.hex
.PHONY: tb_ee_core_bios_long_v0_lineage
tb_ee_core_bios_long_v0_lineage: dirs
	@echo "=== build tb_ee_core_bios_long_v0_lineage (=tb_ee_core_bios_long + CH269_V0_LINEAGE) ==="
	$(IVERILOG) $(IVERILOG_FLGS) -DCH49_ALIGN_EXC -DCH70_RAM_ALIAS -DCH71_LONG_RUN -DCH215_JMPBUF_RESTORE -DCH269_V0_LINEAGE \
	    -o $(BUILD_DIR)/tb_ee_core_bios_long_v0_lineage.vvp \
	    -s tb_ee_core_bios_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bios_smoke.sv
	@echo "=== run tb_ee_core_bios_long_v0_lineage ==="
	@if [ -n "$(BIOS_ABS)" ]; then echo "    real BIOS: $(BIOS_ABS)"; fi
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bios_long_v0_lineage.vvp $(BIOS_PLUSARG) +CH55_INSTALL

# Ch270 — BIOS-bypass EE ELF runner. Loads a PS2 EE ELF (or the
# tiny synthetic test image) into EE RAM, bootstraps the EE core
# via a LUI/ORI/JR trampoline at 0xBFC00000 pointing at the ELF
# entry, and runs with STRICT_UNSUPPORTED=1. Emits a 5-way verdict:
#   elf_first_unsupported_opcode  → next chapter implements the opcode
#   elf_first_unmapped_mmio       → next chapter adds the missing region
#   elf_halted                    → ELF self-halted
#   elf_timeout_with_hot_pc       → ELF ran; reports most-frequent PC
#   elf_entry_unreached / no_retires → bootstrap failure (fail fast)
#
# Two variants:
#   tb_ee_core_elf_runner          — synthetic loop-to-self ELF
#                                     (regression default; no env needed)
#   tb_ee_core_elf_runner_real     — user-supplied real PS2 ELF via
#                                     ELF=<path> on the command line
ELF_IMAGE_SYN     := $(BUILD_DIR)/ch270_synth.image.hex
ELF_MANIFEST_SYN  := $(BUILD_DIR)/ch270_synth.manifest.hex
ELF_TO_EERAM      := $(REPO_ROOT)/tools/elf_to_eeram.py
ELF_GEN_SYN       := $(REPO_ROOT)/tools/generate_synthetic_image.py

$(ELF_IMAGE_SYN) $(ELF_MANIFEST_SYN): $(ELF_GEN_SYN) | dirs
	@echo "=== generate Ch270 synthetic EE-RAM image ==="
	$(PYTHON) $(ELF_GEN_SYN) --out-prefix $(BUILD_DIR)/ch270_synth

.PHONY: tb_ee_core_elf_runner
tb_ee_core_elf_runner: dirs $(ELF_IMAGE_SYN) $(ELF_MANIFEST_SYN)
	@echo "=== build tb_ee_core_elf_runner ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
	    -s tb_ee_core_elf_runner \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_elf_runner.sv
	@echo "=== run tb_ee_core_elf_runner (synthetic) ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
	    +ELF_IMAGE=$(ELF_IMAGE_SYN) +ELF_MANIFEST=$(ELF_MANIFEST_SYN)

# User-supplied real ELF: invoke with `ELF=/path/to/game.elf`.
ELF ?=
ELF_REAL_IMAGE    := $(BUILD_DIR)/ch270_real.image.hex
ELF_REAL_MANIFEST := $(BUILD_DIR)/ch270_real.manifest.hex

.PHONY: tb_ee_core_elf_runner_real
tb_ee_core_elf_runner_real: dirs
	@if [ -z "$(ELF)" ]; then \
	    echo "ERROR: pass ELF=/path/to/game.elf"; exit 2; fi
	@echo "=== convert ELF to EE-RAM image ==="
	$(PYTHON) $(ELF_TO_EERAM) --in $(ELF) --out-prefix $(BUILD_DIR)/ch270_real
	@echo "=== build tb_ee_core_elf_runner ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
	    -s tb_ee_core_elf_runner \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_elf_runner.sv
	@echo "=== run tb_ee_core_elf_runner (real ELF: $(ELF)) ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_elf_runner.vvp \
	    +ELF_IMAGE=$(ELF_REAL_IMAGE) +ELF_MANIFEST=$(ELF_REAL_MANIFEST)

tb_ee_core_slti: dirs
	@echo "=== build tb_ee_core_slti ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_slti.vvp \
	    -s tb_ee_core_slti \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_slti.sv
	@echo "=== run tb_ee_core_slti ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_slti.vvp

tb_ee_core_addi: dirs
	@echo "=== build tb_ee_core_addi ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_addi.vvp \
	    -s tb_ee_core_addi \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_addi.sv
	@echo "=== run tb_ee_core_addi ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_addi.vvp

# Ch271 — R5900 EE Store Quadword. Implements SQ as a 4-beat 32-bit
# write FSM (sq_beat counter) through the existing map_wr 32-bit
# port. Focused TB sets $v0 = 0x80000400, pre-pokes the EE RAM
# target with non-zero junk, executes `sq $zero, 0($v0)`, then
# LW-and-BNE-FAILs each of the four words back to verify zeros.
tb_ee_core_sq: dirs
	@echo "=== build tb_ee_core_sq ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_sq.vvp \
	    -s tb_ee_core_sq \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sq.sv
	@echo "=== run tb_ee_core_sq ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sq.vvp

# Ch272 — R5900 EE DADDU. MIPS-III SPECIAL funct 0x2D. Treated
# as ADDU (low 32 bits) for our 32-bit-GPR model. Focused TB
# covers normal add, the exact qbert move-case (0x0080E02D),
# and unsigned wraparound (no overflow trap).
tb_ee_core_daddu: dirs
	@echo "=== build tb_ee_core_daddu ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_daddu.vvp \
	    -s tb_ee_core_daddu \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_daddu.sv
	@echo "=== run tb_ee_core_daddu ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_daddu.vvp

# Ch273 — minimal EE syscall HLE dispatcher. Three known $v1 values
# from the PS2 crt0 prolog get stub returns and resume at PC+4
# (EndOfHeap=0x3C, InitMainThread=0x3D, FlushCache=0x64); unknown
# $v1 still halts so the next blocker surfaces. Gated behind
# EE_SYSCALL_HLE_ENABLE parameter (default OFF for backwards
# compat with existing "syscall = halt-PASS" TBs).
tb_ee_core_syscall_hle: dirs
	@echo "=== build tb_ee_core_syscall_hle ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_syscall_hle.vvp \
	    -s tb_ee_core_syscall_hle \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_syscall_hle.sv
	@echo "=== run tb_ee_core_syscall_hle ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_syscall_hle.vvp

# Ch274 — MIPS-II BEQL (Branch on Equal Likely). Same compare as
# BEQ, but on the not-taken path the delay slot is SQUASHED
# (PC <- PC+8). qbert.elf needs this in its C++ ctor walker
# where the delay slot at PC+4 clobbers $a0.
tb_ee_core_beql: dirs
	@echo "=== build tb_ee_core_beql ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_beql.vvp \
	    -s tb_ee_core_beql \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_beql.sv
	@echo "=== run tb_ee_core_beql ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_beql.vvp

# Ch275 — MIPS-III SD (Store Doubleword), opcode 0x3F. Implemented
# as a 2-beat 32-bit-stripe write FSM (reusing the SQ sq_beat
# counter). qbert.elf needs this for `sd $ra, 0x20($sp)` in a
# function prologue.
tb_ee_core_sd: dirs
	@echo "=== build tb_ee_core_sd ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_sd.vvp \
	    -s tb_ee_core_sd \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sd.sv
	@echo "=== run tb_ee_core_sd ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sd.vvp

# Ch276 — MIPS-III DSLL (Doubleword Shift Left Logical), SPECIAL
# funct 0x38. Treated as SLL low-32-bit semantics for our 32-bit
# regfile model. Focused TB covers exact qbert encoding, low-bit
# shift, low-32 wrap (bit-31 falls off), and sa=0 identity.
tb_ee_core_dsll: dirs
	@echo "=== build tb_ee_core_dsll ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_dsll.vvp \
	    -s tb_ee_core_dsll \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dsll.sv
	@echo "=== run tb_ee_core_dsll ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dsll.vvp

# Ch277 — MIPS-II BNEL (Branch on Not Equal Likely), opcode 0x15.
# Mirror of Ch274 BEQL: taken when rs!=rt (delay fires), not-taken
# when rs==rt (delay SQUASHED). Reuses the generalized
# is_branch_likely_squash mechanism added in Ch274.
tb_ee_core_bnel: dirs
	@echo "=== build tb_ee_core_bnel ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_bnel.vvp \
	    -s tb_ee_core_bnel \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bnel.sv
	@echo "=== run tb_ee_core_bnel ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bnel.vvp

# Ch278 — R5900 EE MMI2/PCPYLD only (opcode 0x1C, funct 0x09,
# sa 0x0E). Architectural rd[127:64]=rs[63:0], rd[63:0]=rt[63:0]
# collapses in our 32-bit model to rd_low32 = rt_low32. Any
# other MMI sub-instruction still strict-traps so the runner
# surfaces the next concrete blocker (do NOT NOP the whole MMI
# group).
tb_ee_core_pcpyld: dirs
	@echo "=== build tb_ee_core_pcpyld ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_pcpyld.vvp \
	    -s tb_ee_core_pcpyld \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pcpyld.sv
	@echo "=== run tb_ee_core_pcpyld ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pcpyld.vvp

# Ch279 — R5900 EE LQ (Load Quadword), opcode 0x1E. 128-bit
# load symmetric to Ch271 SQ. Single 32-bit read at the
# 16-byte-aligned EA; upper 96 bits unrepresentable in our
# 32-bit-GPR model and discarded.
tb_ee_core_lq: dirs
	@echo "=== build tb_ee_core_lq ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_lq.vvp \
	    -s tb_ee_core_lq \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lq.sv
	@echo "=== run tb_ee_core_lq ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lq.vvp

# Ch280 — R5900 EE MMI0/PSUBB (Parallel Subtract Byte) only.
# opcode 0x1C, funct 0x08, sa 0x09. 4 parallel byte subtracts
# on the low 32 bits (architectural 16-way on 128 bits); no
# cross-byte borrow.
tb_ee_core_psubb: dirs
	@echo "=== build tb_ee_core_psubb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_psubb.vvp \
	    -s tb_ee_core_psubb \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_psubb.sv
	@echo "=== run tb_ee_core_psubb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_psubb.vvp

# Ch281 — R5900 EE MMI3/PNOR (Parallel Not-OR) only. opcode
# 0x1C, funct 0x29 (MMI3), sa 0x13. Bit-identical to standard
# NOR for the low 32 bits; reuses the NOR writeback arm.
# With rs=$zero this is the canonical MIPS "NOT" pseudo.
tb_ee_core_pnor: dirs
	@echo "=== build tb_ee_core_pnor ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_pnor.vvp \
	    -s tb_ee_core_pnor \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pnor.sv
	@echo "=== run tb_ee_core_pnor ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pnor.vvp

# Ch282 — R5900 EE MMI2/PAND (Parallel AND) only. opcode 0x1C,
# funct 0x09 (MMI2), sa 0x12. Bit-identical to standard AND for
# the low 32 bits; reuses the AND writeback arm.
tb_ee_core_pand: dirs
	@echo "=== build tb_ee_core_pand ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_pand.vvp \
	    -s tb_ee_core_pand \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pand.sv
	@echo "=== run tb_ee_core_pand ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pand.vvp

# Ch283 — R5900 EE MMI3/PCPYUD (Parallel Copy Upper Doubleword).
# opcode 0x1C, funct 0x29 (MMI3), sa 0x0E. First MMI op that reads
# from the upper 64 bits of source registers; introduces the gpr128
# shadow that LQ/SQ/SD/PCPYLD/PSUBB/PNOR/PAND now also flow through.
tb_ee_core_pcpyud: dirs
	@echo "=== build tb_ee_core_pcpyud ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_pcpyud.vvp \
	    -s tb_ee_core_pcpyud \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pcpyud.sv
	@echo "=== run tb_ee_core_pcpyud ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pcpyud.vvp

# Ch284 — MIPS-III LD (Load Doubleword), opcode 0x37. The read-side
# of SD; 2-beat 32-bit load FSM (terminal sq_beat = 1) writing two
# lanes of gpr128[rt] and mirroring low 32 to regfile[rt]. 8-byte
# alignment required.
tb_ee_core_ld: dirs
	@echo "=== build tb_ee_core_ld ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_ld.vvp \
	    -s tb_ee_core_ld \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_ld.sv
	@echo "=== run tb_ee_core_ld ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_ld.vvp

# Ch286 — R5900 EI (Enable Interrupts), narrow exact-32-bit decode
# of the canonical encoding 0x42000038. Side-effect-free accept;
# every other COP0/CO encoding still traps under strict mode.
tb_ee_core_ei: dirs
	@echo "=== build tb_ee_core_ei ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_ei.vvp \
	    -s tb_ee_core_ei \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_ei.sv
	@echo "=== run tb_ee_core_ei ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_ei.vvp

# Ch287 — EE DMAC global control/status stub (D_CTRL/D_STAT/D_PCR/
# D_SQWC/D_RBSR/D_RBOR at 0x1000_E000+). Instantiated INTERNALLY in
# ee_memory_map_stub so existing TBs don't need new ports.
tb_ee_dmac_ctrl_stub: dirs
	@echo "=== build tb_ee_dmac_ctrl_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_dmac_ctrl_stub.vvp \
	    -s tb_ee_dmac_ctrl_stub \
	    $(RTL_SRCS) $(TB_ROOT)/dmac/tb_ee_dmac_ctrl_stub.sv
	@echo "=== run tb_ee_dmac_ctrl_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_dmac_ctrl_stub.vvp

# Ch288 — EE DMAC passive per-channel surface (ch0/1/3/4/5). Covers
# the unmodeled channels qbert touches during init clear. Latched
# CHCR/MADR/QWC/TADR; no transfer FSM. Instantiated INTERNALLY in
# ee_memory_map_stub.
tb_ee_dmac_passive_chan_stub: dirs
	@echo "=== build tb_ee_dmac_passive_chan_stub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_dmac_passive_chan_stub.vvp \
	    -s tb_ee_dmac_passive_chan_stub \
	    $(RTL_SRCS) $(TB_ROOT)/dmac/tb_ee_dmac_passive_chan_stub.sv
	@echo "=== run tb_ee_dmac_passive_chan_stub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_dmac_passive_chan_stub.vvp

# Ch292 — MIPS SYNC (SPECIAL funct 0x0F). Narrow side-effect-free
# accept; neighbor SPECIAL funct 0x0E still traps under strict mode.
tb_ee_core_sync: dirs
	@echo "=== build tb_ee_core_sync ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_sync.vvp \
	    -s tb_ee_core_sync \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sync.sv
	@echo "=== run tb_ee_core_sync ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sync.vvp

# Ch300 — R5900 EE MMI3/PCPYH (Parallel Copy Halfword), opcode
# 0x1C, funct 0x29 (MMI3), sa 0x1B. Broadcasts low halfword of each
# $rt doubleword across the corresponding $rd doubleword. Full-128
# writeback via the gpr128 shadow.
tb_ee_core_pcpyh: dirs
	@echo "=== build tb_ee_core_pcpyh ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_pcpyh.vvp \
	    -s tb_ee_core_pcpyh \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_pcpyh.sv
	@echo "=== run tb_ee_core_pcpyh ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_pcpyh.vvp

# Ch305 — R5900 DSUBU (doubleword subtract unsigned), SPECIAL funct
# 0x2F. Modelled as SUBU low-32 (sibling of Ch272 DADDU); no
# overflow trap.
tb_ee_core_dsubu: dirs
	@echo "=== build tb_ee_core_dsubu ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_dsubu.vvp \
	    -s tb_ee_core_dsubu \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_dsubu.sv
	@echo "=== run tb_ee_core_dsubu ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_dsubu.vvp

tb_ee_core_andi: dirs
	@echo "=== build tb_ee_core_andi ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_andi.vvp \
	    -s tb_ee_core_andi \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_andi.sv
	@echo "=== run tb_ee_core_andi ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_andi.vvp

# Ch178 — focused TB pinning CACHE-as-NOP. Issues the exact BIOS
# encoding (CACHE op=0x05, 0x29B0($30) = 0xBFC529B0) that triggered
# the Ch177 strict trap plus a second sub-op to prove "whole class
# accepted". Then verifies $2 wasn't clobbered.
tb_ee_core_cache: dirs
	@echo "=== build tb_ee_core_cache ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_cache.vvp \
	    -s tb_ee_core_cache \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_cache.sv
	@echo "=== run tb_ee_core_cache ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_cache.vvp

tb_ee_core_rtype_logic: dirs
	@echo "=== build tb_ee_core_rtype_logic ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_rtype_logic.vvp \
	    -s tb_ee_core_rtype_logic \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_rtype_logic.sv
	@echo "=== run tb_ee_core_rtype_logic ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_rtype_logic.vvp

tb_ee_core_sb: dirs
	@echo "=== build tb_ee_core_sb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_sb.vvp \
	    -s tb_ee_core_sb \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sb.sv
	@echo "=== run tb_ee_core_sb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sb.vvp

tb_ee_core_lb: dirs
	@echo "=== build tb_ee_core_lb ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_lb.vvp \
	    -s tb_ee_core_lb \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lb.sv
	@echo "=== run tb_ee_core_lb ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lb.vvp

tb_ee_core_jal: dirs
	@echo "=== build tb_ee_core_jal ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_jal.vvp \
	    -s tb_ee_core_jal \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_jal.sv
	@echo "=== run tb_ee_core_jal ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_jal.vvp

tb_ee_core_rtype_addu: dirs
	@echo "=== build tb_ee_core_rtype_addu ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_rtype_addu.vvp \
	    -s tb_ee_core_rtype_addu \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_rtype_addu.sv
	@echo "=== run tb_ee_core_rtype_addu ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_rtype_addu.vvp

tb_ee_core_slt: dirs
	@echo "=== build tb_ee_core_slt ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_slt.vvp \
	    -s tb_ee_core_slt \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_slt.sv
	@echo "=== run tb_ee_core_slt ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_slt.vvp

tb_ee_core_lh: dirs
	@echo "=== build tb_ee_core_lh ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_lh.vvp \
	    -s tb_ee_core_lh \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lh.sv
	@echo "=== run tb_ee_core_lh ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lh.vvp

tb_ee_core_lhu: dirs
	@echo "=== build tb_ee_core_lhu ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_lhu.vvp \
	    -s tb_ee_core_lhu \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lhu.sv
	@echo "=== run tb_ee_core_lhu ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lhu.vvp

tb_ee_core_shift: dirs
	@echo "=== build tb_ee_core_shift ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_shift.vvp \
	    -s tb_ee_core_shift \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_shift.sv
	@echo "=== run tb_ee_core_shift ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_shift.vvp

tb_ee_core_sh: dirs
	@echo "=== build tb_ee_core_sh ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_sh.vvp \
	    -s tb_ee_core_sh \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_sh.sv
	@echo "=== run tb_ee_core_sh ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_sh.vvp

tb_ee_core_jalr: dirs
	@echo "=== build tb_ee_core_jalr ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_jalr.vvp \
	    -s tb_ee_core_jalr \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_jalr.sv
	@echo "=== run tb_ee_core_jalr ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_jalr.vvp

tb_ee_core_add_sub: dirs
	@echo "=== build tb_ee_core_add_sub ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_add_sub.vvp \
	    -s tb_ee_core_add_sub \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_add_sub.sv
	@echo "=== run tb_ee_core_add_sub ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_add_sub.vvp

tb_ee_core_branch_zero: dirs
	@echo "=== build tb_ee_core_branch_zero ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_branch_zero.vvp \
	    -s tb_ee_core_branch_zero \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_branch_zero.sv
	@echo "=== run tb_ee_core_branch_zero ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_branch_zero.vvp

tb_ee_core_lbu: dirs
	@echo "=== build tb_ee_core_lbu ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_lbu.vvp \
	    -s tb_ee_core_lbu \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_lbu.sv
	@echo "=== run tb_ee_core_lbu ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_lbu.vvp

tb_ee_core_divu_mflo: dirs
	@echo "=== build tb_ee_core_divu_mflo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_divu_mflo.vvp \
	    -s tb_ee_core_divu_mflo \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_divu_mflo.sv
	@echo "=== run tb_ee_core_divu_mflo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_divu_mflo.vvp

tb_ee_core_multu_mflo: dirs
	@echo "=== build tb_ee_core_multu_mflo ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_multu_mflo.vvp \
	    -s tb_ee_core_multu_mflo \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_multu_mflo.sv
	@echo "=== run tb_ee_core_multu_mflo ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_multu_mflo.vvp

tb_ee_core_align: dirs
	@echo "=== build tb_ee_core_align ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_align.vvp \
	    -s tb_ee_core_align \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_align.sv
	@echo "=== run tb_ee_core_align ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_align.vvp

tb_ee_core_align_exc: dirs
	@echo "=== build tb_ee_core_align_exc ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_align_exc.vvp \
	    -s tb_ee_core_align_exc \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_align_exc.sv
	@echo "=== run tb_ee_core_align_exc ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_align_exc.vvp

tb_ee_core_bev: dirs
	@echo "=== build tb_ee_core_bev ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_bev.vvp \
	    -s tb_ee_core_bev \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_bev.sv
	@echo "=== run tb_ee_core_bev ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_bev.vvp

tb_ee_core_cop0_count: dirs
	@echo "=== build tb_ee_core_cop0_count ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_cop0_count.vvp \
	    -s tb_ee_core_cop0_count \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_cop0_count.sv
	@echo "=== run tb_ee_core_cop0_count ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_cop0_count.vvp

tb_ee_bootstrap_mmio: dirs
	@echo "=== build tb_ee_bootstrap_mmio ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_bootstrap_mmio.vvp \
	    -s tb_ee_bootstrap_mmio \
	    $(RTL_SRCS) $(TB_ROOT)/ee/tb_ee_bootstrap_mmio.sv
	@echo "=== run tb_ee_bootstrap_mmio ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_bootstrap_mmio.vvp

tb_ee_biu_mmio: dirs
	@echo "=== build tb_ee_biu_mmio ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_biu_mmio.vvp \
	    -s tb_ee_biu_mmio \
	    $(RTL_SRCS) $(TB_ROOT)/ee/tb_ee_biu_mmio.sv
	@echo "=== run tb_ee_biu_mmio ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_biu_mmio.vvp

tb_ee_core_gif_packed: dirs
	@echo "=== build tb_ee_core_gif_packed ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_packed.vvp \
	    -s tb_ee_core_gif_packed \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_packed.sv
	@echo "=== run tb_ee_core_gif_packed ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_packed.vvp

tb_ee_core_gif_reglist: dirs
	@echo "=== build tb_ee_core_gif_reglist ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_reglist.vvp \
	    -s tb_ee_core_gif_reglist \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_reglist.sv
	@echo "=== run tb_ee_core_gif_reglist ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_reglist.vvp

tb_ee_core_gif_primitive: dirs
	@echo "=== build tb_ee_core_gif_primitive ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_primitive.vvp \
	    -s tb_ee_core_gif_primitive \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive.sv
	@echo "=== run tb_ee_core_gif_primitive ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive.vvp

tb_ee_core_gif_primitive_observer: dirs
	@echo "=== build tb_ee_core_gif_primitive_observer ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_primitive_observer.vvp \
	    -s tb_ee_core_gif_primitive_observer \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive_observer.sv
	@echo "=== run tb_ee_core_gif_primitive_observer ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive_observer.vvp

tb_ee_core_gif_primitive_strip: dirs
	@echo "=== build tb_ee_core_gif_primitive_strip ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_primitive_strip.vvp \
	    -s tb_ee_core_gif_primitive_strip \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive_strip.sv
	@echo "=== run tb_ee_core_gif_primitive_strip ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive_strip.vvp

tb_ee_core_gif_primitive_gouraud: dirs
	@echo "=== build tb_ee_core_gif_primitive_gouraud ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_primitive_gouraud.vvp \
	    -s tb_ee_core_gif_primitive_gouraud \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_primitive_gouraud.sv
	@echo "=== run tb_ee_core_gif_primitive_gouraud ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_primitive_gouraud.vvp

tb_ee_core_gif_pixel_emit: dirs
	@echo "=== build tb_ee_core_gif_pixel_emit ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_pixel_emit.vvp \
	    -s tb_ee_core_gif_pixel_emit \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_pixel_emit.sv
	@echo "=== run tb_ee_core_gif_pixel_emit ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_pixel_emit.vvp

tb_ee_core_gif_pixel_emit_psm: dirs
	@echo "=== build tb_ee_core_gif_pixel_emit_psm ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_pixel_emit_psm.vvp \
	    -s tb_ee_core_gif_pixel_emit_psm \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_pixel_emit_psm.sv
	@echo "=== run tb_ee_core_gif_pixel_emit_psm ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_pixel_emit_psm.vvp

tb_ee_core_gif_raster_basic: dirs
	@echo "=== build tb_ee_core_gif_raster_basic ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_raster_basic.vvp \
	    -s tb_ee_core_gif_raster_basic \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_basic.sv
	@echo "=== run tb_ee_core_gif_raster_basic ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_basic.vvp

tb_ee_core_gif_raster_topleft: dirs
	@echo "=== build tb_ee_core_gif_raster_topleft ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_raster_topleft.vvp \
	    -s tb_ee_core_gif_raster_topleft \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_topleft.sv
	@echo "=== run tb_ee_core_gif_raster_topleft ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_topleft.vvp

tb_ee_core_gif_raster_gouraud: dirs
	@echo "=== build tb_ee_core_gif_raster_gouraud ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_raster_gouraud.vvp \
	    -s tb_ee_core_gif_raster_gouraud \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_gouraud.sv
	@echo "=== run tb_ee_core_gif_raster_gouraud ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_gouraud.vvp

tb_ee_core_gif_raster_queue: dirs
	@echo "=== build tb_ee_core_gif_raster_queue ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_gif_raster_queue.vvp \
	    -s tb_ee_core_gif_raster_queue \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_gif_raster_queue.sv
	@echo "=== run tb_ee_core_gif_raster_queue ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_gif_raster_queue.vvp

tb_ee_core_varshift: dirs
	@echo "=== build tb_ee_core_varshift ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_core_varshift.vvp \
	    -s tb_ee_core_varshift \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_core_varshift.sv
	@echo "=== run tb_ee_core_varshift ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_core_varshift.vvp

tb_ee_install_agent_smoke: dirs
	@echo "=== build tb_ee_install_agent_smoke ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -o $(BUILD_DIR)/tb_ee_install_agent_smoke.vvp \
	    -s tb_ee_install_agent_smoke \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_install_agent_smoke.sv
	@echo "=== run tb_ee_install_agent_smoke ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_install_agent_smoke.vvp

tb_ee_install_agent_external_image: dirs
	@echo "=== build tb_ee_install_agent_external_image ==="
	$(IVERILOG) $(IVERILOG_FLGS) \
	    -DCH56_TB_IMAGE_PATH='"$(SIM_DIR)/data/ch56_test_image_4w.mem"' \
	    -o $(BUILD_DIR)/tb_ee_install_agent_external_image.vvp \
	    -s tb_ee_install_agent_external_image \
	    $(RTL_SRCS) $(TB_ROOT)/integration/tb_ee_install_agent_external_image.sv
	@echo "=== run tb_ee_install_agent_external_image ==="
	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_ee_install_agent_external_image.vvp

# Ch357 ZSCHED rejoins the default regression now that its signoff oracle uses the same integer XY
# geometry emitted to the RTL. zrop depends on zsched; zint exercises the real raster -> Z/color LPDDR path.
.PHONY: tb_top_psmct32_sh3_zsched tb_top_psmct32_sh3_zrop tb_top_psmct32_sh3_zint sh3_zsched_board_compare
run: tb_top_psmct32_sh3_zsched tb_top_psmct32_sh3_zrop tb_top_psmct32_sh3_zint

.PHONY: tb_top_psmct32_sh3_zs640_cap tb_top_psmct32_sh3_zint640 sh3_zs640_board_compare sh3_zs640_fixture
run: tb_top_psmct32_sh3_zs640_cap tb_top_psmct32_sh3_zint640

.PHONY: tb_top_psmct32_sh3_zs640c6_cap tb_top_psmct32_sh3_zint640c6 sh3_zs640c6_board_compare sh3_zs640c6_fixture
run: tb_top_psmct32_sh3_zs640c6_cap tb_top_psmct32_sh3_zint640c6

.PHONY: tb_top_psmct32_sh3_zint640rt3 sh3_zsrt3_board_compare
.PHONY: tb_top_psmct32_sh3_zint640rt24 tb_top_psmct32_sh3_zint640rt24_trace sh3_zsrt24_board_compare
.PHONY: tb_top_psmct32_sh3_zint640rtb24 tb_top_psmct32_sh3_zint640rtb24_trace sh3_zsrtb24_board_compare
.PHONY: tb_top_psmct32_sh3_zint640rtm28 tb_top_psmct32_sh3_zint640rtm28_trace sh3_zsrtm28_board_compare
.PHONY: tb_top_psmct32_sh3_zint640rtc24 tb_top_psmct32_sh3_zint640rtc24_trace sh3_zsrtc24_board_compare
.PHONY: tb_top_psmct32_sh3_zint640rte3 tb_top_psmct32_sh3_zint640rte3_trace sh3_zsrte3_board_compare
.PHONY: tb_top_psmct32_sh3_zint640rte6 tb_top_psmct32_sh3_zint640rte6_trace
.PHONY: tb_top_psmct32_sh3_zint640rte8 tb_top_psmct32_sh3_zint640rte8_trace sh3_zsrte8_board_compare
.PHONY: tb_top_psmct32_sh3_zint640rte11 tb_top_psmct32_sh3_zint640rte11_trace sh3_zsrte11_board_compare

.PHONY: tb_top_psmct32_sh3_zs640c12_cap tb_top_psmct32_sh3_zint640c12 sh3_zs640c12_board_compare sh3_zs640c12_fixture
run: tb_top_psmct32_sh3_zs640c12_cap tb_top_psmct32_sh3_zint640c12

.PHONY: tb_top_psmct32_sh3_zs640b24_cap tb_top_psmct32_sh3_zint640b24 sh3_zs640b24_board_compare sh3_zs640b24_fixture
run: tb_top_psmct32_sh3_zs640b24_cap tb_top_psmct32_sh3_zint640b24

.PHONY: tb_top_psmct32_sh3_zs640c24c_cap tb_top_psmct32_sh3_zint640c24c sh3_zs640c24c_fixture sh3_zs640motionabc_bootlet
run: tb_top_psmct32_sh3_zs640c24c_cap tb_top_psmct32_sh3_zint640c24c tb_gs_axi_w_regbuf tb_gs_axi_aw_regbuf tb_gs_axi_r_regbuf
run: tb_gs_lpddr_scanout_lb tb_gs_scanout_binomial_lookahead tb_gs_scanout_diag tb_gs_scanout_restart tb_gs_scanout_cdc_qual
run: tb_gs_grad_num_equiv

run: tb_ee_fetch tb_gs tb_intc tb_platform_video tb_bgcolor_via_dma tb_sif_mailbox \
     tb_sif_command_echo tb_sif_command_echo_rearm tb_sif_negative_path \
     tb_sif_dma_smoke tb_sif_dma_mid_stall tb_sif_dma_overflow tb_sif_combined_ctrl_data \
     tb_iop_ram tb_iop_memory_map tb_iop_memory_map_collision tb_iop_fetch_through_map tb_sif_iop_bridge_smoke \
     tb_sif_iop_bridge_exec tb_iop_to_sif_via_map tb_iop_dmac_via_map \
     tb_sif_ee_landing_via_dmac tb_sif_iop_driven_combined \
     tb_ee_dmac_intc tb_iop_dmac_intc tb_iop_self_driven \
     tb_iop_autonomous_two_xfers tb_iop_responder_ee_ram_landing \
     tb_iop_core_basic tb_iop_core_interrupts \
     tb_iop_core_bootstrap tb_iop_core_bootstrap_intc tb_iop_core_bios_smoke \
     tb_ee_core_basic tb_ee_core_memops tb_ee_core_dmac tb_ee_core_dmac_poll \
     tb_ee_core_dmac_intc tb_ee_core_bios_smoke tb_ee_core_slti \
     tb_ee_core_addi tb_ee_core_andi tb_ee_core_cache tb_ee_core_rtype_logic \
     tb_ee_core_sb tb_ee_core_lb tb_ee_core_jal tb_ee_core_rtype_addu \
     tb_ee_core_slt tb_ee_core_lh tb_ee_core_lhu tb_ee_core_shift \
     tb_ee_core_sh tb_ee_core_jalr tb_ee_core_add_sub \
     tb_ee_core_branch_zero tb_ee_core_lbu tb_ee_core_divu_mflo tb_ee_core_multu_mflo \
     tb_ee_core_align tb_ee_core_align_exc tb_ee_core_bev \
     tb_ee_core_cop0_count tb_ee_bootstrap_mmio tb_ee_biu_mmio \
     tb_ee_core_gif_packed tb_ee_core_gif_reglist tb_ee_core_gif_primitive tb_ee_core_gif_primitive_observer tb_ee_core_gif_primitive_strip tb_ee_core_gif_primitive_gouraud tb_ee_core_gif_pixel_emit tb_ee_core_gif_pixel_emit_psm tb_ee_core_gif_raster_basic tb_ee_core_gif_raster_topleft tb_ee_core_gif_raster_gouraud tb_ee_core_gif_raster_queue tb_gs_raster_queue_full_pop tb_gs_raster_pipeline tb_gs_prim_list_feeder tb_gs_vram_writeback tb_vram_stub tb_vram_bram_stub_equivalence tb_vram_normalize_write tb_gs_scanout_basic tb_gs_scanout_dbx_dby tb_gs_scanout_display_window tb_gs_scanout_magh_magv tb_gs_scanout_psm16 tb_gs_scanout_psmt8 tb_gs_scanout_psmt8_clut tb_gs_tex0_clut tb_gs_clut_load tb_gs_clut_load_ct16 tb_gs_clut_load_cld_modes tb_gs_clut_load_csa_window tb_gs_scanout_psmt4_clut tb_gs_psmt4_round_trip tb_gs_raster_psmct16 tb_gs_raster_psmt8 tb_gs_textured_sprite tb_gs_textured_alpha_sprite tb_gs_psmt8_alpha_sprite tb_gs_psmt8_clut_triangle tb_clut_loader_csm1 tb_gs_raster_psmt4 tb_gs_demo_psmt4_e2e tb_gs_demo_psmt4_e2e_packed tb_gs_demo_psmt4_e2e_dmac tb_gs_demo_psmt4_e2e_trxdir tb_gs_demo_psmt4_e2e_eemmio tb_gs_demo_psmt4_e2e_eemap tb_gs_demo_psmt4_e2e_ee_program tb_gs_demo_psmt4_e2e_ee_full_bootlet tb_ee_ram_cpu_dmac_contention tb_gs_image_xfer_psmct16 tb_gs_image_xfer_psmt8 tb_gs_image_xfer_psmt4 tb_gs_swizzle_psmct32 tb_gs_swizzle_psmct16 tb_gs_swizzle_psmt8 tb_gs_swizzle_psmt4 tb_gs_scanout_swizzle_psmt4 tb_gs_image_xfer_swizzle_psmt4 tb_gs_raster_swizzle_psmt4 tb_gs_demo_psmt4_swizzle_e2e tb_gs_demo_psmt4_swizzle_trxdir_e2e tb_top_psmct32_raster_demo tb_top_psmct32_textured_demo tb_top_psmct32_raster_demo_bram tb_top_psmct32_raster_demo_bram_textured tb_top_psmct32_raster_demo_bram_ch171 tb_gs_raster_backpressure_stress tb_ps2_hps_bridge tb_gs_raster_bram_psmct16 tb_gs_raster_bram_psmt8 tb_gs_raster_bram_psmt4 tb_gs_scanout_bram_psmct16 tb_gs_scanout_bram_psmt8 tb_de25_nano_psmct32_raster_demo_top tb_hdmi_i2c_wake_smoke tb_gs_scanout_swizzle_psmt8 tb_gs_image_xfer_swizzle_psmt8 tb_gs_raster_swizzle_psmt8 tb_gs_demo_psmt8_swizzle_e2e tb_gs_demo_psmt8_swizzle_trxdir_e2e tb_gs_scanout_swizzle_psmct16 tb_gs_image_xfer_swizzle_psmct16 tb_gs_scanout_swizzle_psmct32 tb_gs_image_xfer_swizzle_psmct32 tb_gs_raster_swizzle_psmct32 tb_gs_raster_swizzle_psmct16 tb_gs_demo_psmct32_swizzle_e2e tb_gs_demo_psmct32_swizzle_trxdir_e2e tb_gs_demo_psmct16_swizzle_e2e tb_gs_demo_psmct16_swizzle_trxdir_e2e tb_ee_core_varshift tb_ee_install_agent_smoke tb_ee_install_agent_external_image tb_tile_ram_cdc tb_sio2_input_stub tb_bridge_iop_pad_input tb_pad_state_via_sif_to_ee tb_ee_pad_buffer_branch tb_lpddr_tex_staging tb_osd_platform_cell_adapter tb_ee_core_elf_runner tb_ee_core_sq tb_ee_core_daddu tb_ee_core_syscall_hle tb_ee_core_beql tb_ee_core_sd tb_ee_core_dsll tb_ee_core_bnel tb_ee_core_pcpyld tb_ee_core_lq tb_ee_core_psubb tb_ee_core_pnor tb_ee_core_pand tb_ee_core_pcpyud tb_ee_core_ld tb_ee_core_ei tb_ee_dmac_ctrl_stub tb_ee_dmac_passive_chan_stub tb_ee_core_sync tb_ee_core_pcpyh tb_ee_core_dsubu tb_gs_async_fifo tb_gs_lpddr_fb_writer tb_gs_lpddr_axi_master tb_gs_lpddr_axi_master_elastic tb_gs_lpddr_scanout_fb tb_gs_lpddr_rd_probe tb_gs_lpddr_scanout tb_gs_lpddr_scanout_psm32 tb_gs_lpddr_scanout_concurrency tb_gs_lpddr_scanout_lb_psm32 tb_gs_lpddr_scanout_lb_psm32_256 tb_gs_lpddr_rd_arb tb_gs_lpddr_scanout_lb tb_gs_texture_cache tb_gs_lpddr_wr_probe tb_gs_lpddr_wr_arb tb_gs_tile_reload tb_gs_tile_reload_grid tb_gs_z_flush_writer tb_gs_alpha_blend tb_top_psmct32_alpha_blend_demo tb_top_psmct32_texalpha_demo tb_gs_zbuffer tb_top_psmct32_zbuffer_demo tb_gs_tri_interp tb_gs_fog tb_gs_fog_persp tb_gs_feeder_fog_e2e tb_gs_fog_disabled tb_top_psmct32_triangle_demo tb_gs_textured_triangle tb_top_psmct32_raster_demo_bram_tritex tb_top_psmct32_raster_demo_bram_lpddrtex tb_gs_texture_psmt8_clut tb_gs_texture_wrap tb_gs_texture_bilinear tb_top_psmct32_raster_demo_bram_clut tb_gs_texture_psmt4_clut tb_gs_texture_swizzle_psmt4_clut tb_top_psmct32_raster_demo_bram_clut4 tb_top_psmct32_raster_demo_bram_swz4 tb_gs_texture_swizzle_psmt8_clut tb_top_psmct32_raster_demo_bram_swz8 tb_gs_texture_swizzle_psmct32 tb_top_psmct32_raster_demo_bram_swz32 tb_gs_reciprocal tb_gs_persp_uv tb_gs_persp_uv_farw tb_gs_grad_divider tb_top_psmct32_perspective_demo tb_top_psmct32_persp_floor_demo tb_top_psmct32_combined_demo tb_gs_tile_ram tb_top_psmct32_tile_demo tb_gs_tile_zflush tb_gs_tile_spill_reload tb_gs_tile_spill_lpddr tb_gs_tile_spill_grid_lpddr tb_gs_tile_spill_grid8x8_lpddr tb_gs_tile_spill_lpddr_neg tb_top_psmct32_tile2x2_demo tb_top_psmct32_tile_multiprim_demo tb_top_psmct32_tile_scissor_demo tb_top_psmct32_tile_wrap_demo tb_top_psmct32_tile_psmct16_demo tb_top_psmct32_tile_alpha_demo tb_top_psmct32_tile_bilinear_demo tb_top_psmct32_tile_bin_demo tb_top_psmct32_tile_bin4x4_demo tb_top_psmct32_tile_psmct16fb_demo tb_top_psmct32_tile_lpddr128_demo tb_top_psmct32_tile_palbilinear_demo tb_top_psmct32_tile_cap_demo tb_top_psmct32_tile_cap_overflow_demo tb_top_psmct32_tile_sprite18_demo tb_top_psmct32_tile_cap64_demo tb_top_psmct32_feeder_equiv_demo tb_top_psmct32_feeder_runtime_demo tb_top_psmct32_feeder_bridge_demo tb_top_psmct32_feeder_scenes_demo tb_top_psmct32_feeder_shapes_demo tb_top_psmct32_feeder_colors_demo tb_top_psmct32_feeder_native_demo tb_top_psmct32_feeder_gouraud_demo tb_top_psmct32_feeder_accum_demo tb_top_psmct32_feeder_scene_retrigger_demo tb_top_psmct32_feeder_zpersist_demo tb_top_psmct32_feeder_persp_demo tb_top_psmct32_feeder_sprite_demo tb_top_psmct32_tile_late_demo tb_top_psmct32_tile_lpddrfb_demo
	@echo
	@echo "=== all testbenches complete ==="

# ---------------------------------------------------------------------
# Inspection + cleanup
# ---------------------------------------------------------------------

traces:
	@echo "traces in $(TRACE_DIR):"
	@ls -la $(TRACE_DIR) 2>/dev/null || echo "(none yet)"

clean:
	rm -rf $(BUILD_DIR) $(TRACE_DIR) $(GOLD_TRC_DIR)
	@echo "cleaned build, rtl trace, and golden trace directories"

# ---------------------------------------------------------------------
# Golden-reference harness (Milestone B track)
# ---------------------------------------------------------------------
#
# Spec: sim/golden/trace_compare_spec.md
# Tools:
#   sim/golden/make_nop_golden.py  — generates the NOP-sled golden trace
#   sim/golden/trace_compare.py    — filtered order-based diff

GOLDEN_NOP := $(GOLD_TRC_DIR)/nop_sled.trace
RTL_FETCH  := $(TRACE_DIR)/ee_fetch.trace

golden_nop: dirs
	@echo "=== generate NOP-sled golden ==="
	$(PYTHON) $(GOLDEN_DIR)/make_nop_golden.py --count 32 -o $(GOLDEN_NOP)

compare_ee_fetch: tb_ee_fetch golden_nop
	@echo "=== compare RTL ee_fetch.trace against NOP-sled golden ==="
	$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(GOLDEN_NOP)

# Meta-test that exercises the comparator against the three documented
# exit-code paths (acceptance criteria 4, 5, 6 in trace_compare_spec.md).
test_compare: tb_ee_fetch golden_nop
	@echo
	@echo "=== test_compare: clean run must exit 0 ==="
	$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(GOLDEN_NOP)
	@echo
	@echo "=== test_compare: corrupted golden must exit 1 ==="
	@cp $(GOLDEN_NOP) $(BUILD_DIR)/corrupt_golden.trace
	@sed -i '5s/0x0000000000000000 0x0000000000000000 0x0000000000000000 -/0x00000000deadbeef 0x0000000000000000 0x0000000000000000 -/' $(BUILD_DIR)/corrupt_golden.trace
	@$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(BUILD_DIR)/corrupt_golden.trace; \
	    rc=$$?; \
	    if [ $$rc -eq 1 ]; then echo "  (correctly reported mismatch with exit=1)"; else echo "  FAIL: expected exit=1, got $$rc"; exit 1; fi
	@echo
	@echo "=== test_compare: malformed trace must exit 3 ==="
	@cp $(GOLDEN_NOP) $(BUILD_DIR)/malformed_golden.trace
	@sed -i '5s/.*/this line has too few columns/' $(BUILD_DIR)/malformed_golden.trace
	@$(PYTHON) $(GOLDEN_DIR)/trace_compare.py $(RTL_FETCH) $(BUILD_DIR)/malformed_golden.trace; \
	    rc=$$?; \
	    if [ $$rc -eq 3 ]; then echo "  (correctly reported malformed input with exit=3)"; else echo "  FAIL: expected exit=3, got $$rc"; exit 1; fi
	@echo
	@echo "=== test_compare: all three exit-code paths verified ==="