Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
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// retroDE_ps2 — tb_iop_fetch_through_map
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//
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// First IOP-side execution-visible traffic. Wires:
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//
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// iop_fetch_stub → iop_memory_map_stub → iop_ram_stub
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//
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// TB preloads RAM with a distinctive pattern through the map's write
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// port, then enables the fetcher and verifies that the resulting PC
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// stream and data payloads match what was loaded.
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//
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// Pass criteria:
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// - sequential PC progression from RESET_VECTOR, step +4 per fetch
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// - returned data matches the preloaded pattern
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// - trace tagging correct: SUBSYS_IOP, IFETCH event, IOP_RAM region
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// at the map layer, IOP CPU master_id (2) propagated through
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// - at least N fetches observed (16 in this test)
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`timescale 1ns/1ps
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module tb_iop_fetch_through_map;
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localparam int RAM_BYTES = 4 * 1024;
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localparam int RAM_ADDR_W = $clog2(RAM_BYTES);
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localparam logic [31:0] RESET_VECTOR = 32'h0000_0000;
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localparam int N_FETCHES = 16;
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localparam int PRELOAD_CNT = 32; // cover fetch window plus slack
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ------------------------------------------------------------------
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// Fetcher
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// ------------------------------------------------------------------
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logic fetch_enable;
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logic fetch_rd_en;
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logic [31:0] fetch_rd_addr;
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logic [31:0] fetch_rd_data;
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logic fetch_rd_valid;
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logic fetch_ev_valid;
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trace_pkg::subsys_e fetch_ev_subsys;
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trace_pkg::event_e fetch_ev_event;
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logic [63:0] fetch_ev_arg0, fetch_ev_arg1, fetch_ev_arg2, fetch_ev_arg3;
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logic [31:0] fetch_ev_flags;
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iop_fetch_stub #(.RESET_VECTOR(RESET_VECTOR)) u_fetch (
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.clk(clk), .rst_n(rst_n), .enable(fetch_enable),
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.rd_en(fetch_rd_en), .rd_addr(fetch_rd_addr),
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.rd_data(fetch_rd_data), .rd_valid(fetch_rd_valid),
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.ev_valid(fetch_ev_valid), .ev_subsys(fetch_ev_subsys),
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.ev_event(fetch_ev_event),
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.ev_arg0(fetch_ev_arg0), .ev_arg1(fetch_ev_arg1),
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.ev_arg2(fetch_ev_arg2), .ev_arg3(fetch_ev_arg3),
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.ev_flags(fetch_ev_flags)
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);
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// ------------------------------------------------------------------
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// Map — shared by TB (preload writes) and fetcher (runtime reads)
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// ------------------------------------------------------------------
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// Preload-side write signals (driven by TB)
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logic tb_wr_en;
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logic [31:0] tb_wr_addr;
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logic [31:0] tb_wr_data;
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logic [3:0] tb_wr_be;
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// When the fetcher is enabled, master_id reflects IOP CPU (2). During
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// the preload window, the TB owns writes and tags them as TB_direct (0).
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logic [7:0] map_master_id;
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assign map_master_id = fetch_enable ? 8'd2 : 8'd0;
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logic map_ram_rd_en;
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logic [20:0] map_ram_rd_addr;
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logic [31:0] ram_rd_data;
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logic ram_rd_valid;
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logic map_ram_wr_en;
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logic [20:0] map_ram_wr_addr;
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logic [31:0] map_ram_wr_data;
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logic [3:0] map_ram_wr_be;
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logic [7:0] map_ram_master_id;
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logic map_ev_valid;
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trace_pkg::subsys_e map_ev_subsys;
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trace_pkg::event_e map_ev_event;
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logic [63:0] map_ev_arg0, map_ev_arg1, map_ev_arg2, map_ev_arg3;
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logic [31:0] map_ev_flags;
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iop_memory_map_stub u_map (
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.clk(clk), .rst_n(rst_n),
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// Read: from fetcher
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.iop_rd_en(fetch_rd_en), .iop_rd_addr(fetch_rd_addr),
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.iop_rd_data(fetch_rd_data), .iop_rd_valid(fetch_rd_valid),
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// Write: from TB preload
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.iop_wr_en(tb_wr_en), .iop_wr_addr(tb_wr_addr),
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.iop_wr_data(tb_wr_data), .iop_wr_be(tb_wr_be),
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.master_id(map_master_id),
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// Bridge port — unused by this TB
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.bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
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.bridge_wr_data(32'd0), .bridge_wr_be(4'd0),
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.bridge_master_id(8'd0),
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// DMA read-master port — unused by this TB
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.dma_rd_en(1'b0), .dma_rd_addr(32'd0),
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.dma_master_id(8'd0),
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.dma_rd_data(), .dma_rd_valid(),
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// SIF register-shell port — unused by this TB
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.sif_rd_en(), .sif_rd_addr(),
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.sif_rd_data(32'd0), .sif_rd_valid(1'b0),
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.sif_wr_en(), .sif_wr_addr(), .sif_wr_data(),
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// IOP DMAC port — unused by this TB
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.iop_dmac_rd_en(), .iop_dmac_rd_addr(),
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.iop_dmac_rd_data(32'd0), .iop_dmac_rd_valid(1'b0),
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.iop_dmac_wr_en(), .iop_dmac_wr_addr(), .iop_dmac_wr_data(),
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// IOP INTC port — unused by this TB
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.iop_intc_rd_en(), .iop_intc_rd_addr(),
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.iop_intc_rd_data(32'd0), .iop_intc_rd_valid(1'b0),
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.iop_intc_wr_en(), .iop_intc_wr_addr(), .iop_intc_wr_data(),
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.input_p1(32'd0), .input_p2(32'd0),
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// BIOS ROM port — unused by this TB
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.bios_rd_en(), .bios_rd_addr(),
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.bios_rd_data(32'd0), .bios_rd_valid(1'b0),
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.ram_rd_en(map_ram_rd_en), .ram_rd_addr(map_ram_rd_addr),
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.ram_rd_data(ram_rd_data), .ram_rd_valid(ram_rd_valid),
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.ram_wr_en(map_ram_wr_en), .ram_wr_addr(map_ram_wr_addr),
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.ram_wr_data(map_ram_wr_data), .ram_wr_be(map_ram_wr_be),
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.ram_master_id(map_ram_master_id),
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.ev_valid(map_ev_valid), .ev_subsys(map_ev_subsys),
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.ev_event(map_ev_event),
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.ev_arg0(map_ev_arg0), .ev_arg1(map_ev_arg1),
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.ev_arg2(map_ev_arg2), .ev_arg3(map_ev_arg3),
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.ev_flags(map_ev_flags)
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);
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// ------------------------------------------------------------------
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// IOP RAM backing
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// ------------------------------------------------------------------
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logic ram_ev_valid;
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trace_pkg::subsys_e ram_ev_subsys;
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trace_pkg::event_e ram_ev_event;
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logic [63:0] ram_ev_arg0, ram_ev_arg1, ram_ev_arg2, ram_ev_arg3;
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logic [31:0] ram_ev_flags;
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iop_ram_stub #(.SIZE_BYTES(RAM_BYTES)) u_ram (
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.clk(clk), .rst_n(rst_n),
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.rd_en(map_ram_rd_en), .rd_addr(map_ram_rd_addr[RAM_ADDR_W-1:0]),
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.rd_data(ram_rd_data), .rd_valid(ram_rd_valid),
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.wr_en(map_ram_wr_en), .wr_addr(map_ram_wr_addr[RAM_ADDR_W-1:0]),
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.wr_data(map_ram_wr_data), .wr_be(map_ram_wr_be),
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.master_id(map_ram_master_id),
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.ev_valid(ram_ev_valid), .ev_subsys(ram_ev_subsys),
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.ev_event(ram_ev_event),
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.ev_arg0(ram_ev_arg0), .ev_arg1(ram_ev_arg1),
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.ev_arg2(ram_ev_arg2), .ev_arg3(ram_ev_arg3),
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.ev_flags(ram_ev_flags)
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);
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// ------------------------------------------------------------------
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// Trace sinks
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// ------------------------------------------------------------------
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trace_sink_stub #(.FILENAME("iop_fetch_fetcher.trace"), .SINK_LABEL("iop_fetch"))
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u_trace_fetch (.clk(clk), .rst_n(rst_n),
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.ev_valid(fetch_ev_valid), .ev_subsys(fetch_ev_subsys),
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.ev_event(fetch_ev_event), .ev_arg0(fetch_ev_arg0),
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.ev_arg1(fetch_ev_arg1), .ev_arg2(fetch_ev_arg2),
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.ev_arg3(fetch_ev_arg3), .ev_flags(fetch_ev_flags));
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trace_sink_stub #(.FILENAME("iop_fetch_map.trace"), .SINK_LABEL("iop_map"))
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u_trace_map (.clk(clk), .rst_n(rst_n),
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.ev_valid(map_ev_valid), .ev_subsys(map_ev_subsys),
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.ev_event(map_ev_event), .ev_arg0(map_ev_arg0),
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.ev_arg1(map_ev_arg1), .ev_arg2(map_ev_arg2),
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.ev_arg3(map_ev_arg3), .ev_flags(map_ev_flags));
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trace_sink_stub #(.FILENAME("iop_fetch_ram.trace"), .SINK_LABEL("iop_ram"))
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u_trace_ram (.clk(clk), .rst_n(rst_n),
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.ev_valid(ram_ev_valid), .ev_subsys(ram_ev_subsys),
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.ev_event(ram_ev_event), .ev_arg0(ram_ev_arg0),
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.ev_arg1(ram_ev_arg1), .ev_arg2(ram_ev_arg2),
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.ev_arg3(ram_ev_arg3), .ev_flags(ram_ev_flags));
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// ------------------------------------------------------------------
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// Checkers
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// ------------------------------------------------------------------
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int ifetch_count;
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int map_ifetch_routed; // map-level IOP reads with region=IOP_RAM
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int map_master_iop_cpu_count; // map events tagged master_id=2
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int errors;
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wire [31:0] obs_addr = fetch_ev_arg0[31:0];
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wire [31:0] obs_data = fetch_ev_arg1[31:0];
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wire [31:0] obs_offset = obs_addr - RESET_VECTOR;
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wire [31:0] obs_wordidx = obs_offset >> 2;
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// Preloaded pattern: 0xABCD_0000 | word_idx
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wire [31:0] obs_expected = 32'hABCD_0000 | {16'd0, obs_wordidx[15:0]};
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initial begin
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ifetch_count = 0;
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map_ifetch_routed = 0;
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map_master_iop_cpu_count = 0;
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errors = 0;
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end
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always_ff @(posedge clk) begin
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if (rst_n && fetch_ev_valid && fetch_ev_event == trace_pkg::EV_IFETCH) begin
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ifetch_count <= ifetch_count + 1;
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if (obs_data !== obs_expected) begin
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$error("[tb_iop_fetch_through_map] IFETCH mismatch: addr=0x%08h data=0x%08h expected=0x%08h",
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obs_addr, obs_data, obs_expected);
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errors <= errors + 1;
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end
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end
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if (rst_n && map_ev_valid &&
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map_ev_subsys == trace_pkg::SUBSYS_IOP) begin
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if (map_ev_event == trace_pkg::EV_READ &&
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map_ev_arg3[7:0] == 8'd2) // region=IOP_RAM
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map_ifetch_routed <= map_ifetch_routed + 1;
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if (map_ev_arg2[7:0] == 8'd2) // master=IOP_CPU
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map_master_iop_cpu_count <= map_master_iop_cpu_count + 1;
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end
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end
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// ------------------------------------------------------------------
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// Helpers
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// ------------------------------------------------------------------
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task automatic preload_word(input logic [31:0] addr,
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input logic [31:0] data);
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@(negedge clk);
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tb_wr_en = 1'b1;
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tb_wr_addr = addr;
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tb_wr_data = data;
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tb_wr_be = 4'b1111;
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@(negedge clk);
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tb_wr_en = 1'b0;
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tb_wr_addr = 32'd0;
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tb_wr_data = 32'd0;
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tb_wr_be = 4'd0;
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endtask
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// ------------------------------------------------------------------
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// Stimulus
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// ------------------------------------------------------------------
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initial begin
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rst_n = 1'b0;
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fetch_enable = 1'b0;
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tb_wr_en = 1'b0;
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tb_wr_addr = 32'd0;
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tb_wr_data = 32'd0;
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tb_wr_be = 4'd0;
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repeat (4) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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// Preload a window wider than N_FETCHES so any overshoot in the
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// run loop still hits preloaded words. Pattern is consistent:
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// mem[word_idx] = 0xABCD_0000 | word_idx
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for (int i = 0; i < PRELOAD_CNT; i++) begin
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preload_word(RESET_VECTOR + (i * 32'd4),
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32'hABCD_0000 | {16'd0, 16'(i)});
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end
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// Enable the fetcher and let it run through the preloaded window.
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@(negedge clk);
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fetch_enable = 1'b1;
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repeat (N_FETCHES + 6) @(posedge clk);
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fetch_enable = 1'b0;
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repeat (4) @(posedge clk);
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// ------------------------------------------------------------------
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$display("[tb_iop_fetch_through_map] ifetches=%0d map_routed=%0d map_iop_cpu_tagged=%0d errors=%0d",
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ifetch_count, map_ifetch_routed, map_master_iop_cpu_count, errors);
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if (ifetch_count < N_FETCHES)
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$error("expected >= %0d IFETCHes, got %0d", N_FETCHES, ifetch_count);
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if (map_ifetch_routed < N_FETCHES)
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$error("expected >= %0d map-routed IOP reads (region=IOP_RAM), got %0d",
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N_FETCHES, map_ifetch_routed);
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if (map_master_iop_cpu_count < N_FETCHES)
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$error("expected >= %0d map events tagged master=IOP_CPU, got %0d",
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N_FETCHES, map_master_iop_cpu_count);
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if (errors == 0 && ifetch_count >= N_FETCHES &&
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map_ifetch_routed >= N_FETCHES &&
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map_master_iop_cpu_count >= N_FETCHES)
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$display("[tb_iop_fetch_through_map] PASS");
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else
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$display("[tb_iop_fetch_through_map] FAIL");
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$finish;
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end
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initial begin
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#200000;
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$error("[tb_iop_fetch_through_map] timeout");
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$finish;
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end
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endmodule : tb_iop_fetch_through_map
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