Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
@@ -0,0 +1,495 @@
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// retroDE_ps2 — tb_iop_dmac_via_map
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//
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// IOP-DMAC register lifecycle + data-path integration. Proves:
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// - IOP can program DMAC ch9 through the real 0x1F80_152x window.
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// - DMAC fetches real source words from IOP RAM via the map's new
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// dma_rd_* master port — MADR is a live pointer, stepping by 4.
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// - Transfer emits DMA_START, per-beat DMA_BEAT with correct
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// src_addr + remaining-count, and DMA_DONE on the final beat.
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// - Endpoint ready/valid backpressure stalls mid-stream without any
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// false completion: busy stays high, no DMA_DONE fires, no beat
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// events advance while ep_ready is low.
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//
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// Chain:
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// TB (preloads payload into IOP RAM via map CPU write)
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// TB (programs ch9 via map at 0x1F80_152x)
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// │
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// ▼
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// iop_memory_map_stub ← iop_dmac_reg_stub (ch9, reads via dma_rd_*)
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// │
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// ▼
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// iop_ram_stub
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//
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// TB consumes the DMAC endpoint with a manually-driven ep_ready; the
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// egress bridge is deliberately not wired here — that's the full-chain
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// TB's job (tb_sif_ee_landing_via_dmac). Keeping this TB minimal keeps
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// the lifecycle/stall coverage independent of the landing path.
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//
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// Scenarios:
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// 1. Architectural programming. IOP writes MADR + BCR via map; DMAC
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// emits EV_DMA_CFG; busy stays low; CHCR[0] stays 0.
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// 2. Normal run: ep_ready = 1, IOP writes CHCR start (bit 0). DMAC
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// emits START, then emits one BEAT per accepted word with correct
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// src_addr, finishes with DONE. CHCR[0] clears.
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// 3. Stall: start a second transfer with ep_ready = 0. Confirm busy
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// high, no new DONE, beat count unchanged across a wait window.
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// 4. Recovery: ep_ready back to 1. Transfer completes.
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// 5. Readback: MADR/BCR/CHCR read through the map.
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//
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// Key trace-visible assertions:
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// - Map emits events with region=IOP_DMAC (4) on ch9 register
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// accesses, region=IOP_RAM (2) on DMAC source fetches (master_id=4).
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// - DMAC trace has the CFG/START/BEAT/DONE sequence with BEAT count
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// equal to BCR, and src_addr stepping by 4 per beat.
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`timescale 1ns/1ps
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module tb_iop_dmac_via_map;
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localparam int RAM_BYTES = 4 * 1024;
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localparam int RAM_ADDR_W = $clog2(RAM_BYTES);
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localparam logic [31:0] DMAC_CH9_BASE = 32'h1F80_1520;
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localparam logic [31:0] DMAC_MADR_ADDR = DMAC_CH9_BASE | 32'h00;
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localparam logic [31:0] DMAC_BCR_ADDR = DMAC_CH9_BASE | 32'h04;
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localparam logic [31:0] DMAC_CHCR_ADDR = DMAC_CH9_BASE | 32'h08;
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// Source address in IOP RAM for the payload — bit-aligned to a
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// deterministic offset away from 0 so the TB can tell the right
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// bytes moved.
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localparam logic [31:0] SRC_BASE = 32'h0000_0200;
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localparam int BEATS = 4; // small BCR for TB speed
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ------------------------------------------------------------------
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// IOP map
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// ------------------------------------------------------------------
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logic iop_rd_en;
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logic [31:0] iop_rd_addr;
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logic [31:0] iop_rd_data;
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logic iop_rd_valid;
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logic iop_wr_en;
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logic [31:0] iop_wr_addr;
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logic [31:0] iop_wr_data;
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logic [3:0] iop_wr_be;
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logic ram_rd_en;
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logic [20:0] ram_rd_addr;
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logic [31:0] ram_rd_data;
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logic ram_rd_valid;
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logic ram_wr_en;
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logic [20:0] ram_wr_addr;
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logic [31:0] ram_wr_data;
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logic [3:0] ram_wr_be;
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logic [7:0] ram_master_id;
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logic map_dmac_rd_en;
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logic [3:0] map_dmac_rd_addr;
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logic [31:0] map_dmac_rd_data;
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logic map_dmac_rd_valid;
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logic map_dmac_wr_en;
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logic [3:0] map_dmac_wr_addr;
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logic [31:0] map_dmac_wr_data;
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// DMAC as read master through the map
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logic dma_rd_en;
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logic [31:0] dma_rd_addr;
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logic [7:0] dma_master_id;
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logic [31:0] dma_rd_data;
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logic dma_rd_valid;
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logic map_ev_valid;
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trace_pkg::subsys_e map_ev_subsys;
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trace_pkg::event_e map_ev_event;
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logic [63:0] map_ev_arg0, map_ev_arg1, map_ev_arg2, map_ev_arg3;
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logic [31:0] map_ev_flags;
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iop_memory_map_stub u_iop_map (
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.clk(clk), .rst_n(rst_n),
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.iop_rd_en(iop_rd_en), .iop_rd_addr(iop_rd_addr),
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.iop_rd_data(iop_rd_data), .iop_rd_valid(iop_rd_valid),
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.iop_wr_en(iop_wr_en), .iop_wr_addr(iop_wr_addr),
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.iop_wr_data(iop_wr_data), .iop_wr_be(iop_wr_be),
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.master_id(8'd2), // IOP_CPU
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// Bridge port — unused
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.bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
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.bridge_wr_data(32'd0), .bridge_wr_be(4'd0),
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.bridge_master_id(8'd0),
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// DMA read-master port — DMAC's fetches
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.dma_rd_en(dma_rd_en), .dma_rd_addr(dma_rd_addr),
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.dma_master_id(dma_master_id),
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.dma_rd_data(dma_rd_data), .dma_rd_valid(dma_rd_valid),
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// SIF register-shell port — unused by this TB
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.sif_rd_en(), .sif_rd_addr(),
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.sif_rd_data(32'd0), .sif_rd_valid(1'b0),
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.sif_wr_en(), .sif_wr_addr(), .sif_wr_data(),
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// DMAC register-shell port
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.iop_dmac_rd_en(map_dmac_rd_en), .iop_dmac_rd_addr(map_dmac_rd_addr),
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.iop_dmac_rd_data(map_dmac_rd_data), .iop_dmac_rd_valid(map_dmac_rd_valid),
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.iop_dmac_wr_en(map_dmac_wr_en), .iop_dmac_wr_addr(map_dmac_wr_addr),
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.iop_dmac_wr_data(map_dmac_wr_data),
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// IOP INTC port — unused by this TB
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.iop_intc_rd_en(), .iop_intc_rd_addr(),
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.iop_intc_rd_data(32'd0), .iop_intc_rd_valid(1'b0),
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.iop_intc_wr_en(), .iop_intc_wr_addr(), .iop_intc_wr_data(),
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.input_p1(32'd0), .input_p2(32'd0),
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// BIOS ROM port — unused by this TB
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.bios_rd_en(), .bios_rd_addr(),
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.bios_rd_data(32'd0), .bios_rd_valid(1'b0),
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// RAM downstream
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.ram_rd_en(ram_rd_en), .ram_rd_addr(ram_rd_addr),
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.ram_rd_data(ram_rd_data), .ram_rd_valid(ram_rd_valid),
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.ram_wr_en(ram_wr_en), .ram_wr_addr(ram_wr_addr),
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.ram_wr_data(ram_wr_data), .ram_wr_be(ram_wr_be),
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.ram_master_id(ram_master_id),
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.ev_valid(map_ev_valid), .ev_subsys(map_ev_subsys),
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.ev_event(map_ev_event),
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.ev_arg0(map_ev_arg0), .ev_arg1(map_ev_arg1),
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.ev_arg2(map_ev_arg2), .ev_arg3(map_ev_arg3),
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.ev_flags(map_ev_flags)
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);
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iop_ram_stub #(.SIZE_BYTES(RAM_BYTES)) u_iop_ram (
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.clk(clk), .rst_n(rst_n),
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.rd_en(ram_rd_en), .rd_addr(ram_rd_addr[RAM_ADDR_W-1:0]),
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.rd_data(ram_rd_data), .rd_valid(ram_rd_valid),
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.wr_en(ram_wr_en), .wr_addr(ram_wr_addr[RAM_ADDR_W-1:0]),
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.wr_data(ram_wr_data), .wr_be(ram_wr_be),
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.master_id(ram_master_id),
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.ev_valid(), .ev_subsys(), .ev_event(),
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.ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
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);
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// ------------------------------------------------------------------
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// IOP DMAC (ch9) — TB drives ep_ready directly
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// ------------------------------------------------------------------
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logic ep_valid;
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logic [31:0] ep_data;
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logic ep_last;
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logic ep_ready;
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logic dmac_busy;
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logic [31:0] dmac_done_count;
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logic dmac_ev_valid;
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trace_pkg::subsys_e dmac_ev_subsys;
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trace_pkg::event_e dmac_ev_event;
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logic [63:0] dmac_ev_arg0, dmac_ev_arg1, dmac_ev_arg2, dmac_ev_arg3;
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logic [31:0] dmac_ev_flags;
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iop_dmac_reg_stub u_dmac (
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.clk(clk), .rst_n(rst_n),
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.reg_wr_en(map_dmac_wr_en), .reg_rd_en(map_dmac_rd_en),
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.reg_offset(map_dmac_wr_en ? map_dmac_wr_addr : map_dmac_rd_addr),
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.reg_wr_data(map_dmac_wr_data),
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.reg_rd_data(map_dmac_rd_data), .reg_rd_valid(map_dmac_rd_valid),
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// DMAC → IOP map dma_rd_*
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.mem_rd_en(dma_rd_en), .mem_rd_addr(dma_rd_addr),
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.mem_master_id(dma_master_id),
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.mem_rd_data(dma_rd_data), .mem_rd_valid(dma_rd_valid),
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// Endpoint (TB drives ep_ready)
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.ep_valid(ep_valid), .ep_data(ep_data), .ep_last(ep_last),
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.ep_ready(ep_ready),
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.irq_completion_o(),
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.busy_o(dmac_busy), .done_count_o(dmac_done_count),
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.ev_valid(dmac_ev_valid), .ev_subsys(dmac_ev_subsys),
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.ev_event(dmac_ev_event),
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.ev_arg0(dmac_ev_arg0), .ev_arg1(dmac_ev_arg1),
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.ev_arg2(dmac_ev_arg2), .ev_arg3(dmac_ev_arg3),
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.ev_flags(dmac_ev_flags)
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);
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// ------------------------------------------------------------------
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// Trace sinks
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// ------------------------------------------------------------------
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trace_sink_stub #(.FILENAME("iop_dmac_via_map.trace"), .SINK_LABEL("iop_map"))
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u_trace_map (.clk(clk), .rst_n(rst_n),
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.ev_valid(map_ev_valid), .ev_subsys(map_ev_subsys),
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.ev_event(map_ev_event), .ev_arg0(map_ev_arg0),
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.ev_arg1(map_ev_arg1), .ev_arg2(map_ev_arg2),
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.ev_arg3(map_ev_arg3), .ev_flags(map_ev_flags));
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trace_sink_stub #(.FILENAME("iop_dmac_reg.trace"), .SINK_LABEL("iop_dmac"))
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u_trace_dmac (.clk(clk), .rst_n(rst_n),
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.ev_valid(dmac_ev_valid), .ev_subsys(dmac_ev_subsys),
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.ev_event(dmac_ev_event), .ev_arg0(dmac_ev_arg0),
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.ev_arg1(dmac_ev_arg1), .ev_arg2(dmac_ev_arg2),
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.ev_arg3(dmac_ev_arg3), .ev_flags(dmac_ev_flags));
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// ------------------------------------------------------------------
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// Counters + captured beats
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// ------------------------------------------------------------------
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int map_dmac_events; // map events region=IOP_DMAC (reg accesses)
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int map_ram_dma_events; // map events region=IOP_RAM + master_id=4
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int dmac_cfg_events;
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int dmac_start_events;
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int dmac_beat_events;
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int dmac_done_events;
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int stall_cycles;
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int errors;
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logic [31:0] captured_beats [0:31];
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int beat_capture_count;
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initial begin
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map_dmac_events = 0;
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map_ram_dma_events = 0;
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dmac_cfg_events = 0;
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dmac_start_events = 0;
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dmac_beat_events = 0;
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dmac_done_events = 0;
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stall_cycles = 0;
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beat_capture_count = 0;
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errors = 0;
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for (int i = 0; i < 32; i++) captured_beats[i] = 32'd0;
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end
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always_ff @(posedge clk) begin
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if (rst_n && map_ev_valid &&
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map_ev_subsys == trace_pkg::SUBSYS_IOP) begin
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if (map_ev_arg3[7:0] == 8'd4)
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map_dmac_events <= map_dmac_events + 1;
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if (map_ev_arg3[7:0] == 8'd2 && map_ev_arg2[7:0] == 8'd4)
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map_ram_dma_events <= map_ram_dma_events + 1;
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end
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if (rst_n && dmac_ev_valid &&
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dmac_ev_subsys == trace_pkg::SUBSYS_DMAC) begin
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case (dmac_ev_event)
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trace_pkg::EV_DMA_CFG: dmac_cfg_events <= dmac_cfg_events + 1;
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trace_pkg::EV_DMA_START: dmac_start_events <= dmac_start_events + 1;
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trace_pkg::EV_DMA_BEAT: dmac_beat_events <= dmac_beat_events + 1;
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trace_pkg::EV_DMA_DONE: dmac_done_events <= dmac_done_events + 1;
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default: ;
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endcase
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end
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if (rst_n && dmac_busy && !ep_ready)
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stall_cycles <= stall_cycles + 1;
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// Capture beats as they're accepted at the endpoint.
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if (rst_n && ep_valid && ep_ready && beat_capture_count < 32) begin
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captured_beats[beat_capture_count] <= ep_data;
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beat_capture_count <= beat_capture_count + 1;
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end
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end
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// ------------------------------------------------------------------
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// Helpers
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// ------------------------------------------------------------------
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task automatic iop_write(input logic [31:0] addr, input logic [31:0] data);
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@(negedge clk);
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iop_wr_en = 1'b1;
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iop_wr_addr = addr;
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iop_wr_data = data;
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iop_wr_be = 4'b1111;
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@(negedge clk);
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iop_wr_en = 1'b0;
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iop_wr_addr = 32'd0;
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iop_wr_data = 32'd0;
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iop_wr_be = 4'd0;
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endtask
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task automatic iop_read_expect(input logic [31:0] addr,
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input logic [31:0] expected,
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input string label);
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@(negedge clk);
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iop_rd_en = 1'b1;
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iop_rd_addr = addr;
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@(negedge clk);
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iop_rd_en = 1'b0;
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iop_rd_addr = 32'd0;
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if (iop_rd_data !== expected || iop_rd_valid !== 1'b1) begin
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$error("[tb_iop_dmac_via_map] IOP read %s at 0x%08h: got 0x%08h valid=%0b expected 0x%08h",
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label, addr, iop_rd_data, iop_rd_valid, expected);
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errors = errors + 1;
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end
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endtask
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// ------------------------------------------------------------------
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// Stimulus
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// ------------------------------------------------------------------
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logic [31:0] payload [0:BEATS-1];
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int prev_done_count;
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int prev_beat_count;
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int stall_observed;
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initial begin
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rst_n = 1'b0;
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iop_rd_en = 1'b0;
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iop_rd_addr = 32'd0;
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iop_wr_en = 1'b0;
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iop_wr_addr = 32'd0;
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iop_wr_data = 32'd0;
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iop_wr_be = 4'd0;
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ep_ready = 1'b1;
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prev_done_count = 0;
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prev_beat_count = 0;
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stall_observed = 0;
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// Four distinctive words so beat capture is unambiguous.
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payload[0] = 32'hA5A5_0000;
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payload[1] = 32'hDEAD_BEEF;
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payload[2] = 32'hCAFE_F00D;
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payload[3] = 32'h1234_5678;
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repeat (4) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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// --------------------------------------------------------------
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// Preload: TB writes the payload words into IOP RAM through the
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// CPU-side port of the map. Uses the RAM region (phys 0x00...),
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// 4-byte stride starting at SRC_BASE.
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// --------------------------------------------------------------
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for (int i = 0; i < BEATS; i++) begin
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iop_write(SRC_BASE + (i << 2), payload[i]);
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end
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// --------------------------------------------------------------
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// Scenario 1: architectural programming
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// --------------------------------------------------------------
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iop_write(DMAC_MADR_ADDR, SRC_BASE);
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iop_write(DMAC_BCR_ADDR, 32'(BEATS));
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if (dmac_busy !== 1'b0) begin
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$error("[tb_iop_dmac_via_map] unexpected busy after programming (no start)");
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errors = errors + 1;
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end
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if (dmac_done_count != 0) begin
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$error("[tb_iop_dmac_via_map] done_count nonzero before any start: %0d",
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dmac_done_count);
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errors = errors + 1;
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end
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// --------------------------------------------------------------
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// Scenario 2: normal flow with ep_ready high throughout
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// --------------------------------------------------------------
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ep_ready = 1'b1;
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iop_write(DMAC_CHCR_ADDR, 32'h0000_0001);
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// Allow enough cycles for the full transfer: each beat takes at
|
||||
// least 2 cycles (fetch + send), plus a few cycles of startup +
|
||||
// wind-down. 6*BEATS is generous.
|
||||
repeat (6 * BEATS) @(posedge clk);
|
||||
|
||||
if (dmac_done_count != 1) begin
|
||||
$error("[tb_iop_dmac_via_map] done_count expected 1 after normal flow, got %0d",
|
||||
dmac_done_count);
|
||||
errors = errors + 1;
|
||||
end
|
||||
if (beat_capture_count < BEATS) begin
|
||||
$error("[tb_iop_dmac_via_map] captured %0d beats, expected %0d",
|
||||
beat_capture_count, BEATS);
|
||||
errors = errors + 1;
|
||||
end
|
||||
// Payload order check
|
||||
for (int i = 0; i < BEATS; i++) begin
|
||||
if (captured_beats[i] !== payload[i]) begin
|
||||
$error("[tb_iop_dmac_via_map] beat[%0d] got 0x%08h expected 0x%08h",
|
||||
i, captured_beats[i], payload[i]);
|
||||
errors = errors + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// Scenario 3: mid-stream stall
|
||||
// --------------------------------------------------------------
|
||||
prev_done_count = dmac_done_count;
|
||||
prev_beat_count = dmac_beat_events;
|
||||
|
||||
// Re-program same source+length (transfer already cleared CHCR.0).
|
||||
iop_write(DMAC_MADR_ADDR, SRC_BASE);
|
||||
iop_write(DMAC_BCR_ADDR, 32'(BEATS));
|
||||
|
||||
// Start with ep_ready low from the beginning.
|
||||
ep_ready = 1'b0;
|
||||
iop_write(DMAC_CHCR_ADDR, 32'h0000_0001);
|
||||
|
||||
// Wait window with backpressure held. DMAC should reach
|
||||
// ACTIVE_SEND and wait there — busy high, no DONE.
|
||||
repeat (10) @(posedge clk);
|
||||
|
||||
if (dmac_busy !== 1'b1) begin
|
||||
$error("[tb_iop_dmac_via_map] busy should be high during mid-stream stall");
|
||||
errors = errors + 1;
|
||||
end
|
||||
if (dmac_done_count != prev_done_count) begin
|
||||
$error("[tb_iop_dmac_via_map] DMA_DONE fired during stall: %0d→%0d",
|
||||
prev_done_count, dmac_done_count);
|
||||
errors = errors + 1;
|
||||
end
|
||||
stall_observed = stall_cycles;
|
||||
if (stall_observed < 5) begin
|
||||
$error("[tb_iop_dmac_via_map] expected >=5 stall cycles, got %0d", stall_observed);
|
||||
errors = errors + 1;
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// Scenario 4: recovery
|
||||
// --------------------------------------------------------------
|
||||
ep_ready = 1'b1;
|
||||
repeat (6 * BEATS) @(posedge clk);
|
||||
|
||||
if (dmac_done_count != 2) begin
|
||||
$error("[tb_iop_dmac_via_map] done_count expected 2 after recovery, got %0d",
|
||||
dmac_done_count);
|
||||
errors = errors + 1;
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// Scenario 5: readback via map
|
||||
// --------------------------------------------------------------
|
||||
iop_read_expect(DMAC_MADR_ADDR, SRC_BASE, "MADR readback");
|
||||
iop_read_expect(DMAC_BCR_ADDR, 32'(BEATS), "BCR readback");
|
||||
iop_read_expect(DMAC_CHCR_ADDR, 32'h0000_0000, "CHCR readback (start cleared)");
|
||||
|
||||
repeat (4) @(posedge clk);
|
||||
|
||||
// --------------------------------------------------------------
|
||||
$display("[tb_iop_dmac_via_map] map_dmac=%0d map_ram_dma=%0d cfg=%0d start=%0d beat=%0d done=%0d stall_cy=%0d errors=%0d",
|
||||
map_dmac_events, map_ram_dma_events,
|
||||
dmac_cfg_events, dmac_start_events, dmac_beat_events,
|
||||
dmac_done_events, stall_observed, errors);
|
||||
|
||||
// Two transfers × BEATS beats each = 2*BEATS expected DMA_BEAT events
|
||||
if (dmac_beat_events != 2 * BEATS)
|
||||
$error("expected %0d EV_DMA_BEAT events, got %0d",
|
||||
2 * BEATS, dmac_beat_events);
|
||||
if (dmac_start_events != 2)
|
||||
$error("expected 2 EV_DMA_START, got %0d", dmac_start_events);
|
||||
if (dmac_done_events != 2)
|
||||
$error("expected 2 EV_DMA_DONE, got %0d", dmac_done_events);
|
||||
if (map_ram_dma_events < BEATS)
|
||||
$error("expected >=%0d map RAM reads by DMA master, got %0d",
|
||||
BEATS, map_ram_dma_events);
|
||||
|
||||
if (errors == 0 &&
|
||||
dmac_beat_events == 2 * BEATS &&
|
||||
dmac_start_events == 2 &&
|
||||
dmac_done_events == 2 &&
|
||||
map_ram_dma_events >= BEATS)
|
||||
$display("[tb_iop_dmac_via_map] PASS");
|
||||
else
|
||||
$display("[tb_iop_dmac_via_map] FAIL");
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#200000;
|
||||
$error("[tb_iop_dmac_via_map] timeout");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule : tb_iop_dmac_via_map
|
||||
Reference in New Issue
Block a user