Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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// ============================================================================
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// tb_gs_texture_cache.sv (Ch322 Brick 1)
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//
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// Proves the prefilled texture cache: fill an 8x8 PSMCT32 texture (256 B = 8
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// single-beat 256-bit reads) from a tiny EMIF-ish read model into the on-chip
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// RAM, then verify:
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// (1) fill_done asserts, fill_beats=8, fill_bytes=256, rd_errs=0
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// (2) every cached word == the source word (sampler-side 1-cycle reads)
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// (3) the read is 1-cycle REGISTERED (data lands the cycle AFTER tex_rd_en)
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// (4) a forced non-OKAY rresp increments rd_errs
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// ============================================================================
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`timescale 1ns/1ps
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module tb_gs_texture_cache;
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localparam int TEX_BYTES = 256;
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localparam int N_BEATS = 8;
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localparam int TEX_WORDS = TEX_BYTES/4; // 64
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localparam [29:0] LPDDR_TEX_BASE = 30'h0010_0000;
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localparam [31:0] TEX_VRAM_BASE = 32'd2048;
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logic axi_clk = 0, sample_clk = 0, axi_rst_n = 0;
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always #5 axi_clk = ~axi_clk; // 100 MHz-ish
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always #7 sample_clk = ~sample_clk; // asynchronous, slower
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// fill control
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logic fill_start;
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logic fill_done;
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logic [31:0] fill_beats, fill_bytes, rd_errs;
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// AXI read channel
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logic [29:0] araddr; logic [1:0] arburst; logic [6:0] arid;
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logic [7:0] arlen; logic [2:0] arsize; logic arvalid, arready;
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logic [255:0] rdata; logic [1:0] rresp; logic rlast, rvalid, rready;
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// sampler read port
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logic tex_rd_en;
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logic [31:0] tex_rd_addr, tex_rd_data;
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logic tex_ready;
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// golden source: 64 words. tex_word(i) = 0xC0DE_0000 | i (distinct per lane).
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function automatic [31:0] tex_word(input int i); tex_word = 32'hC0DE_0000 | i[31:0]; endfunction
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// force a bad rresp on a chosen beat to exercise rd_errs (set <0 to disable)
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int err_beat = -1;
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gs_texture_cache #(
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.LPDDR_TEX_BASE(LPDDR_TEX_BASE), .TEX_VRAM_BASE(TEX_VRAM_BASE),
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.TEX_BYTES(TEX_BYTES), .N_BEATS(N_BEATS)
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) dut (
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.axi_clk(axi_clk), .axi_rst_n(axi_rst_n),
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.fill_start(fill_start), .fill_done(fill_done),
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.fill_beats(fill_beats), .fill_bytes(fill_bytes), .rd_errs(rd_errs),
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.araddr(araddr), .arburst(arburst), .arid(arid), .arlen(arlen),
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.arsize(arsize), .arvalid(arvalid), .arready(arready),
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.rdata(rdata), .rresp(rresp), .rlast(rlast), .rvalid(rvalid), .rready(rready),
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.sample_clk(sample_clk), .tex_rd_en(tex_rd_en),
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.tex_rd_addr(tex_rd_addr), .tex_rd_data(tex_rd_data), .tex_ready(tex_ready)
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);
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// ---- single-beat EMIF read model (arlen=0 only), ~ a few cycles latency ----
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// returns 8 words per 256-bit beat from the golden source, indexed by araddr.
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typedef enum logic [1:0] { S_IDLE, S_WAIT, S_DATA } sstate_t;
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sstate_t sst;
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logic [29:0] beat_addr; logic [3:0] dly; int beat_idx;
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always_ff @(posedge axi_clk) begin
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if (!axi_rst_n) begin
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sst <= S_IDLE; arready <= 1'b0; rvalid <= 1'b0; rlast <= 1'b0;
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rresp <= 2'b00; rdata <= '0; dly <= '0;
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end else begin
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arready <= 1'b0; rvalid <= 1'b0; rlast <= 1'b0;
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case (sst)
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S_IDLE: if (arvalid) begin
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beat_addr <= araddr; arready <= 1'b1;
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beat_idx <= (araddr - LPDDR_TEX_BASE) >> 5; // 32 B/beat
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dly <= 4'd3; sst <= S_WAIT;
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end
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S_WAIT: if (dly==0) sst <= S_DATA; else dly <= dly - 1'b1;
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S_DATA: if (rready) begin
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for (int w=0; w<8; w++) rdata[w*32 +: 32] <= tex_word(beat_idx*8 + w);
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rresp <= (beat_idx == err_beat) ? 2'b10 : 2'b00; // SLVERR on chosen beat
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rvalid <= 1'b1; rlast <= 1'b1;
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sst <= S_IDLE;
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end
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endcase
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end
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end
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int errors = 0;
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task automatic check(input bit cond, input string msg);
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if (!cond) begin errors++; $display("[texcache] FAIL: %s", msg); end
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endtask
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// sampler 1-cycle read helper (sample_clk domain)
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task automatic read_word(input int widx, output logic [31:0] got);
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@(posedge sample_clk);
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tex_rd_addr <= TEX_VRAM_BASE + widx*4; tex_rd_en <= 1'b1;
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@(posedge sample_clk);
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tex_rd_en <= 1'b0; // data for THIS address lands now (1-cycle registered)
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@(posedge sample_clk); // sample the registered output
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got = tex_rd_data;
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endtask
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logic [31:0] got;
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initial begin
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fill_start = 0; tex_rd_en = 0; tex_rd_addr = 0;
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repeat (4) @(posedge axi_clk); axi_rst_n = 1;
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repeat (2) @(posedge axi_clk);
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// ---- pass 1: clean fill ----
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// fill_start is an EDGE/TOGGLE: flip once (0->1) and HOLD — a 0->1->0 pulse would
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// trigger a second fill on the falling edge. Pass 2's reset re-creates the edge.
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@(posedge axi_clk); fill_start <= 1'b1;
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// wait for fill_done
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begin int g=0; while (!fill_done && g<2000) begin @(posedge axi_clk); g++; end end
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check(fill_done, "fill_done never asserted");
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check(fill_beats == N_BEATS, $sformatf("fill_beats=%0d exp %0d", fill_beats, N_BEATS));
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check(fill_bytes == TEX_BYTES, $sformatf("fill_bytes=%0d exp %0d", fill_bytes, TEX_BYTES));
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check(rd_errs == 32'd0, $sformatf("rd_errs=%0d exp 0", rd_errs));
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// wait for tex_ready to cross into sample_clk
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begin int g=0; while (!tex_ready && g<200) begin @(posedge sample_clk); g++; end end
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check(tex_ready, "tex_ready never synced");
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// ---- verify every word via the sampler 1-cycle read port ----
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for (int i=0; i<TEX_WORDS; i++) begin
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read_word(i, got);
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check(got == tex_word(i), $sformatf("word[%0d]=%08x exp %08x", i, got, tex_word(i)));
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end
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$display("[texcache] clean: fill_done=%0d beats=%0d bytes=%0d rd_errs=%0d words_checked=%0d errors=%0d",
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fill_done, fill_beats, fill_bytes, rd_errs, TEX_WORDS, errors);
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// ---- pass 2: rd_errs exercise (reset, force SLVERR on beat 3) ----
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// The reset clears the cache's fill_start edge-sync; with fill_start still held 1
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// from pass 1, the post-reset re-sync re-creates the edge and re-fills.
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axi_rst_n = 0; err_beat = 3; repeat (3) @(posedge axi_clk); axi_rst_n = 1;
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repeat (2) @(posedge axi_clk);
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begin int g=0; while (!fill_done && g<2000) begin @(posedge axi_clk); g++; end end
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check(rd_errs == 32'd1, $sformatf("forced-err rd_errs=%0d exp 1", rd_errs));
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$display("[texcache] err-inject: rd_errs=%0d (exp 1)", rd_errs);
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if (errors==0) $display("[tb_gs_texture_cache] PASS");
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else $display("[tb_gs_texture_cache] FAIL (%0d errors)", errors);
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$finish;
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end
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initial begin #500000; $display("[tb_gs_texture_cache] TIMEOUT"); $finish; end
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endmodule
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