Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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// retroDE_ps2 — tb_gs_scanout_psm16 (Ch94)
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//
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// Locks the contract for DISPFB1.PSM=PSMCT16 (RGB5A1) scanout.
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// gs_pcrtc_stub now selects byte-offset shift and color-decode
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// path based on the PSM field in DISPFB1: PSMCT32 (=0) reads 4
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// bytes/pixel and uses {A, B, G, R} byte order; PSMCT16 (=2)
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// reads 2 bytes/pixel and unpacks RGB5A1 with 5→8 bit-replicate
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// expansion.
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//
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// gs_stub's raster channel still emits PSMCT32 only, so this TB
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// bypasses gs_stub entirely — it instantiates only `vram_stub`
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// (so we have a real RAM) and `gs_pcrtc_stub` (so we exercise
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// the scanout PSM path), and drives privileged-register-shaped
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// inputs from TB-side regs. That isolates the test to the
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// scanout PSM decode.
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//
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// Setup:
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// VRAM populated with a 4×4 RGB5A1 sprite, color
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// (R5, G5, B5) = (0x10, 0x18, 0x08) → 16-bit pixel 0x2310,
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// row stride 128 bytes (FBW=1 → 64 pixels/row × 2 bytes/pixel).
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// PSM = PSMCT16 (DISPFB1[19:15] = 0x02).
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// DISPFB1.FBP=0, FBW=1. DBX=DBY=0.
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// DISPLAY1 covers full 16×8 active area, MAGH=MAGV=0 (1×).
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//
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// Expected:
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// R8 = {0x10, 0x10[4:2]} = {0x10, 3'b100} = 8'h84
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// G8 = {0x18, 0x18[4:2]} = {0x18, 3'b110} = 8'hC6
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// B8 = {0x08, 0x08[4:2]} = {0x08, 3'b010} = 8'h42
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// At displayed (0..3, 0..3): (R, G, B) = (0x84, 0xC6, 0x42).
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// At every other displayed pixel: (0, 0, 0).
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`timescale 1ns/1ps
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module tb_gs_scanout_psm16;
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localparam int PCRTC_H_ACTIVE = 16;
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localparam int PCRTC_V_ACTIVE = 8;
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// Privileged-register-shaped TB regs feeding pcrtc directly.
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logic [63:0] pmode_q;
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logic [63:0] dispfb1_q;
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logic [63:0] display1_q;
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// VRAM write side: TB-driven (no gs_stub raster source).
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logic vram_we;
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logic [31:0] vram_waddr;
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logic [31:0] vram_wdata;
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// VRAM read side: pcrtc drives the address.
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logic [31:0] vram_raddr;
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logic [31:0] vram_rdata;
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vram_stub #(.BYTES(4096)) u_vram (
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.clk(clk), .rst_n(rst_n),
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.write_en (vram_we),
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.write_addr(vram_waddr),
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.write_data(vram_wdata),
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.write_be (4'b1111),
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.write_mask(32'hFFFF_FFFF),
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.read_addr (vram_raddr),
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.read_data (vram_rdata),
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.read2_addr(32'd0),
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.read2_data()
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);
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logic hsync_o, vsync_o, de_o;
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logic [7:0] r_o, g_o, b_o;
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logic pcrtc_ev_valid;
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trace_pkg::subsys_e pcrtc_ev_subsys;
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trace_pkg::event_e pcrtc_ev_event;
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logic [63:0] pcrtc_ev_arg0, pcrtc_ev_arg1;
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logic [63:0] pcrtc_ev_arg2, pcrtc_ev_arg3;
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logic [31:0] pcrtc_ev_flags;
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gs_pcrtc_stub #(
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.H_ACTIVE(PCRTC_H_ACTIVE), .H_FRONT(1), .H_SYNC(1), .H_BACK(1),
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.V_ACTIVE(PCRTC_V_ACTIVE), .V_FRONT(1), .V_SYNC(1), .V_BACK(1)
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) u_pcrtc (
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.clk(clk), .rst_n(rst_n),
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.pmode_q (pmode_q),
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.dispfb1_q (dispfb1_q),
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.display1_q (display1_q),
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.vram_read_addr(vram_raddr),
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.vram_read_data(vram_rdata),
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.clut_enable (1'b0),
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.clut_csa (5'd0),
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.clut_read_idx (),
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.clut_read_data(32'd0),
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.hsync(hsync_o), .vsync(vsync_o), .de(de_o),
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.r(r_o), .g(g_o), .b(b_o),
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.ev_valid(pcrtc_ev_valid),
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.ev_subsys(pcrtc_ev_subsys),
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.ev_event(pcrtc_ev_event),
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.ev_arg0(pcrtc_ev_arg0), .ev_arg1(pcrtc_ev_arg1),
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.ev_arg2(pcrtc_ev_arg2), .ev_arg3(pcrtc_ev_arg3),
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.ev_flags(pcrtc_ev_flags)
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);
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logic [7:0] cap_r [0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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logic [7:0] cap_g [0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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logic [7:0] cap_b [0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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logic cap_de[0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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int errors;
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bit capture_armed;
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initial begin
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for (int y = 0; y < PCRTC_V_ACTIVE; y++)
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for (int x = 0; x < PCRTC_H_ACTIVE; x++) begin
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cap_r[y][x] = 8'd0;
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cap_g[y][x] = 8'd0;
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cap_b[y][x] = 8'd0;
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cap_de[y][x] = 1'b0;
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end
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errors = 0;
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capture_armed = 1'b0;
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end
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always_ff @(posedge clk) begin
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if (rst_n && capture_armed && de_o
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&& (u_pcrtc.vcnt < PCRTC_V_ACTIVE)
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&& (u_pcrtc.hcnt < PCRTC_H_ACTIVE)) begin
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cap_r [u_pcrtc.vcnt][u_pcrtc.hcnt] <= r_o;
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cap_g [u_pcrtc.vcnt][u_pcrtc.hcnt] <= g_o;
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cap_b [u_pcrtc.vcnt][u_pcrtc.hcnt] <= b_o;
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cap_de[u_pcrtc.vcnt][u_pcrtc.hcnt] <= 1'b1;
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end
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end
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task automatic vram_write32(input logic [31:0] addr, input logic [31:0] data);
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@(negedge clk);
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vram_we = 1'b1;
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vram_waddr = addr;
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vram_wdata = data;
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@(posedge clk);
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@(negedge clk);
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vram_we = 1'b0;
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vram_waddr = 32'd0;
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vram_wdata = 32'd0;
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endtask
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// Build a packed RGB5A1 16-bit value: A[15] B[14:10] G[9:5] R[4:0].
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function automatic logic [15:0] psm16_pack(input logic [4:0] r5,
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input logic [4:0] g5,
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input logic [4:0] b5,
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input logic a1);
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return {a1, b5, g5, r5};
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endfunction
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// Sprite color.
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localparam logic [4:0] R5 = 5'h10;
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localparam logic [4:0] G5 = 5'h18;
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localparam logic [4:0] B5 = 5'h08;
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// Expected expanded 8-bit values (5→8 bit-replicate).
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localparam logic [7:0] EXP_R = {R5, R5[4:2]};
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localparam logic [7:0] EXP_G = {G5, G5[4:2]};
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localparam logic [7:0] EXP_B = {B5, B5[4:2]};
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localparam int SPRITE_W = 4;
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localparam int SPRITE_H = 4;
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// DISPFB1 PSM = PSMCT16 (5'h02), FBP=0, FBW=1.
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// FBP[8:0] = 0
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// FBW[14:9] = 1 → 0x200
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// PSM[19:15] = 2 → 0x10000
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localparam logic [63:0] DISPFB1_VAL = 64'h0000_0000_0001_0200;
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// DISPLAY1 covers full active area, MAGH=MAGV=0.
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localparam logic [63:0] DISPLAY1_VAL =
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(64'(PCRTC_H_ACTIVE - 1) << 32) // DW
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| (64'(PCRTC_V_ACTIVE - 1) << 44); // DH
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localparam logic [63:0] PMODE_EN1 = 64'h0000_0000_0000_0001;
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initial begin
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rst_n = 1'b0;
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pmode_q = 64'd0;
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dispfb1_q = 64'd0;
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display1_q = 64'd0;
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vram_we = 1'b0;
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vram_waddr = 32'd0;
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vram_wdata = 32'd0;
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repeat (4) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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// Populate VRAM with the 4×4 PSMCT16 sprite. FBW=1
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// means 64 pixels/row × 2 bytes = 128 bytes/row stride.
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// Row Y starts at byte Y*128. Each row stores 4 PSMCT16
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// pixels = 8 bytes = 2 32-bit writes.
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for (int y = 0; y < SPRITE_H; y++) begin
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logic [15:0] pix;
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logic [31:0] pair;
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int row_base;
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pix = psm16_pack(R5, G5, B5, 1'b0);
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pair = {pix, pix}; // two PSMCT16 pixels packed
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row_base = y * 128;
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// Pixels (0,1) at byte row_base..row_base+3.
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vram_write32(row_base, pair);
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// Pixels (2,3) at byte row_base+4..row_base+7.
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vram_write32(row_base + 32'd4, pair);
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end
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// Configure scanout. Reset has dispfb1_q=display1_q=0, so
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// we must explicitly write both before enabling EN1.
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dispfb1_q = DISPFB1_VAL;
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display1_q = DISPLAY1_VAL;
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@(posedge clk);
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// Cross-check the PSM field landed at [19:15]=2.
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if (dispfb1_q[19:15] !== 5'h02) begin
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$error("DISPFB1.PSM=%0d (expected 2 = PSMCT16)", dispfb1_q[19:15]);
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errors = errors + 1;
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end
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pmode_q = PMODE_EN1;
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@(posedge clk);
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@(posedge u_pcrtc.end_of_frame);
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@(posedge clk);
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capture_armed = 1'b1;
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@(posedge u_pcrtc.end_of_frame);
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@(posedge clk);
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capture_armed = 1'b0;
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// Per-pixel verification.
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for (int y = 0; y < PCRTC_V_ACTIVE; y++) begin
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for (int x = 0; x < PCRTC_H_ACTIVE; x++) begin
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logic [7:0] er, eg, eb;
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if (x < SPRITE_W && y < SPRITE_H) begin
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er = EXP_R; eg = EXP_G; eb = EXP_B;
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end else begin
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er = 8'd0; eg = 8'd0; eb = 8'd0;
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end
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if (!cap_de[y][x]) begin
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$error("(%0d,%0d) DE never asserted", x, y);
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errors = errors + 1;
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end
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if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
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$error("(%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
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x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
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errors = errors + 1;
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end
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end
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end
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$display("[tb_gs_scanout_psm16] sprite=%0dx%0d RGB5A1=(%02x,%02x,%02x) → RGB8=(%02x,%02x,%02x)",
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SPRITE_W, SPRITE_H, R5, G5, B5, EXP_R, EXP_G, EXP_B);
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if (errors == 0) $display("[tb_gs_scanout_psm16] PASS");
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else $display("[tb_gs_scanout_psm16] FAIL");
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$finish;
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end
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initial begin
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#5000000;
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$error("[tb_gs_scanout_psm16] timeout");
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$finish;
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end
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endmodule : tb_gs_scanout_psm16
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