Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
@@ -0,0 +1,496 @@
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// retroDE_ps2 — tb_gs_clut_load (Ch99)
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//
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// Locks the contract for TEX0.CLD-driven VRAM→CLUT load. Pre-Ch99
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// the CLUT was always TB-direct-programmed; now a TEX0_1 write
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// with CLD != 0 (and CPSM=PSMCT32) triggers `clut_loader_stub`
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// to copy 256 PSMCT32 entries from VRAM[CBP*256] into clut_stub.
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//
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// Setup (no gs_stub raster — VRAM written directly):
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// - VRAM[0..255] holds a PSMT8 sprite of indices 0x10..0x1F
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// (4×4 pixels at 1 byte/pixel).
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// - VRAM[1024..] holds 256 PSMCT32 CLUT entries; the entries
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// the sprite uses (0x10..0x1F) are programmed
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// with the same `clut_entry(i)` formula as
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// Ch97 (R=i, G=i+0x40, B=i+0x80, A=0xFF).
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// - TEX0_1: CBP=4 (=1024 bytes), CPSM=PSMCT32 (0), CSM=1
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// (CSM2 linear), CSA=0, CLD=1 ("always load").
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// - Drive TEX0_1 via gs_stub.gif_reg_*; loader's load_busy
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// pulses high for 256 cycles; TB waits for the falling edge.
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// - Configure DISPFB1.PSM=PSMT8, DISPLAY1 (full active),
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// PMODE.EN1=1, capture frame, verify each in-sprite pixel
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// reads the correct CLUT-decoded RGB.
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//
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// Out of scope (deferred):
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// - CLD modes 2..7 (load conditional on CBP/CPSM/CSA changes).
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// - CPSM != PSMCT32 (PSMCT16 CLUT entries with 5→8 expansion).
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// - CSA partial-window loads (CLD=4).
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// - Real TEX0_1 in-flight collision / re-trigger semantics.
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`timescale 1ns/1ps
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module tb_gs_clut_load;
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localparam int PCRTC_H_ACTIVE = 16;
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localparam int PCRTC_V_ACTIVE = 8;
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// gs_stub IO
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logic gif_reg_wr_en;
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logic [7:0] gif_reg_num;
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logic [63:0] gif_reg_data;
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logic priv_reg_wr_en;
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logic [15:0] priv_reg_wr_addr;
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logic [63:0] priv_reg_wr_data;
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logic [7:0] bg_r, bg_g, bg_b;
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logic [63:0] pmode_q, dispfb1_q, display1_q;
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logic [63:0] prim_q, rgbaq_q, xyz2_q, xyzf2_q, frame_1_q, zbuf_1_q;
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logic [63:0] tex0_1_q;
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logic [13:0] tex0_1_cbp_q;
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logic [3:0] tex0_1_cpsm_q;
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logic tex0_1_csm_q;
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logic [4:0] tex0_1_csa_q;
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logic [2:0] tex0_1_cld_q;
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logic tex0_1_wr_q;
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logic prim_complete;
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logic [31:0] prim_complete_count;
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logic [63:0] prim_v0_q, prim_v1_q, prim_v2_q;
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logic [63:0] prim_color_q;
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logic [63:0] prim_color_v0_q, prim_color_v1_q, prim_color_v2_q;
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trace_pkg::vertex_t prim_v0_decoded_q, prim_v1_decoded_q, prim_v2_decoded_q;
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trace_pkg::color_t prim_v0_color_decoded_q, prim_v1_color_decoded_q, prim_v2_color_decoded_q;
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logic pixel_emit;
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logic [31:0] pixel_emit_count;
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logic [11:0] pixel_x_q, pixel_y_q;
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logic [63:0] pixel_color_q;
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logic [8:0] pixel_fbp_q;
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logic [5:0] pixel_fbw_q, pixel_psm_q;
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logic [31:0] pixel_fb_addr_q;
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logic raster_pixel_emit;
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logic [31:0] raster_pixel_emit_count;
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logic [11:0] raster_pixel_x_q, raster_pixel_y_q;
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logic [63:0] raster_pixel_color_q;
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logic [31:0] raster_pixel_fb_addr_q;
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logic [3:0] raster_pixel_be_q;
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logic [5:0] raster_pixel_psm_q;
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logic raster_active;
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logic raster_overflow;
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logic raster_degenerate;
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logic gs_ev_valid;
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trace_pkg::subsys_e gs_ev_subsys;
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trace_pkg::event_e gs_ev_event;
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logic [63:0] gs_ev_arg0, gs_ev_arg1, gs_ev_arg2, gs_ev_arg3;
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logic [31:0] gs_ev_flags;
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gs_stub u_gs (
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.clk(clk), .rst_n(rst_n),
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.reg_wr_en (priv_reg_wr_en),
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.reg_wr_addr(priv_reg_wr_addr),
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.reg_wr_data(priv_reg_wr_data),
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.gif_reg_wr_en(gif_reg_wr_en),
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.gif_reg_num(gif_reg_num),
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.gif_reg_data(gif_reg_data),
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.bg_r(bg_r), .bg_g(bg_g), .bg_b(bg_b),
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.pmode_q(pmode_q), .dispfb1_q(dispfb1_q), .display1_q(display1_q),
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.prim_q(prim_q), .rgbaq_q(rgbaq_q),
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.xyz2_q(xyz2_q), .xyzf2_q(xyzf2_q),
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.frame_1_q(frame_1_q), .zbuf_1_q(zbuf_1_q),
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.tex0_1_q(tex0_1_q),
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.tex0_1_cbp_q(tex0_1_cbp_q),
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.tex0_1_cpsm_q(tex0_1_cpsm_q),
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.tex0_1_csm_q(tex0_1_csm_q),
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.tex0_1_csa_q(tex0_1_csa_q),
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.tex0_1_cld_q(tex0_1_cld_q),
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.tex0_1_wr_q(tex0_1_wr_q),
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.prim_complete(prim_complete),
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.prim_complete_count(prim_complete_count),
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.prim_v0_q(prim_v0_q), .prim_v1_q(prim_v1_q), .prim_v2_q(prim_v2_q),
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.prim_color_q(prim_color_q),
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.prim_color_v0_q(prim_color_v0_q),
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.prim_color_v1_q(prim_color_v1_q),
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.prim_color_v2_q(prim_color_v2_q),
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.prim_v0_decoded_q(prim_v0_decoded_q),
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.prim_v1_decoded_q(prim_v1_decoded_q),
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.prim_v2_decoded_q(prim_v2_decoded_q),
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.prim_v0_color_decoded_q(prim_v0_color_decoded_q),
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.prim_v1_color_decoded_q(prim_v1_color_decoded_q),
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.prim_v2_color_decoded_q(prim_v2_color_decoded_q),
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.pixel_emit(pixel_emit),
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.pixel_emit_count(pixel_emit_count),
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.pixel_x_q(pixel_x_q), .pixel_y_q(pixel_y_q),
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.pixel_color_q(pixel_color_q),
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.pixel_fbp_q(pixel_fbp_q),
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.pixel_fbw_q(pixel_fbw_q),
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.pixel_psm_q(pixel_psm_q),
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.pixel_fb_addr_q(pixel_fb_addr_q),
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.raster_pixel_emit(raster_pixel_emit),
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.raster_pixel_emit_count(raster_pixel_emit_count),
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.raster_pixel_x_q(raster_pixel_x_q),
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.raster_pixel_y_q(raster_pixel_y_q),
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.raster_pixel_color_q(raster_pixel_color_q),
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.raster_pixel_fb_addr_q(raster_pixel_fb_addr_q),
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.raster_pixel_be_q(raster_pixel_be_q),
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.raster_pixel_psm_q(raster_pixel_psm_q),
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.raster_active(raster_active),
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.raster_overflow(raster_overflow),
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.raster_degenerate(raster_degenerate),
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.ev_valid(gs_ev_valid),
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.ev_subsys(gs_ev_subsys),
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.ev_event(gs_ev_event),
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.ev_arg0(gs_ev_arg0), .ev_arg1(gs_ev_arg1),
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.ev_arg2(gs_ev_arg2), .ev_arg3(gs_ev_arg3),
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.ev_flags(gs_ev_flags)
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);
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// VRAM (TB-direct write port for sprite + CLUT-source bytes;
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// pcrtc reads via port 0; loader reads via port 1).
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logic vram_we;
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logic [31:0] vram_waddr;
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logic [31:0] vram_wdata;
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logic [3:0] vram_wbe;
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logic [31:0] vram_raddr;
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logic [31:0] vram_rdata;
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logic [31:0] vram_raddr2;
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logic [31:0] vram_rdata2;
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vram_stub #(.BYTES(8192)) u_vram (
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.clk(clk), .rst_n(rst_n),
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.write_en (vram_we),
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.write_addr(vram_waddr),
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.write_data(vram_wdata),
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.write_be (vram_wbe),
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.write_mask(32'hFFFF_FFFF),
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.read_addr (vram_raddr),
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.read_data (vram_rdata),
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.read2_addr(vram_raddr2),
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.read2_data(vram_rdata2)
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);
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// CLUT — write port driven by clut_loader_stub; read port
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// consumed by gs_pcrtc_stub.
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logic clut_we;
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logic [7:0] clut_widx;
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logic [31:0] clut_wdata;
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logic [7:0] clut_ridx;
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logic [31:0] clut_rdata;
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clut_stub u_clut (
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.clk(clk), .rst_n(rst_n),
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.write_en (clut_we),
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.write_idx (clut_widx),
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.write_data(clut_wdata),
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.read_idx (clut_ridx),
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.read_data (clut_rdata)
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);
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// The loader: TEX0_1 fields → VRAM read port 1 → clut_stub.
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logic loader_busy;
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clut_loader_stub u_loader (
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.clk(clk), .rst_n(rst_n),
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.tex0_wr_pulse (tex0_1_wr_q),
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.tex0_cbp (tex0_1_cbp_q),
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.tex0_cpsm (tex0_1_cpsm_q),
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.tex0_csm (tex0_1_csm_q),
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.tex0_csa (tex0_1_csa_q),
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.tex0_cld (tex0_1_cld_q),
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.vram_read_addr (vram_raddr2),
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.vram_read_data (vram_rdata2),
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.clut_write_en (clut_we),
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.clut_write_idx (clut_widx),
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.clut_write_data(clut_wdata),
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.load_busy (loader_busy)
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);
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logic hsync_o, vsync_o, de_o;
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logic [7:0] r_o, g_o, b_o;
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logic pcrtc_ev_valid;
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trace_pkg::subsys_e pcrtc_ev_subsys;
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trace_pkg::event_e pcrtc_ev_event;
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logic [63:0] pcrtc_ev_arg0, pcrtc_ev_arg1;
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logic [63:0] pcrtc_ev_arg2, pcrtc_ev_arg3;
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logic [31:0] pcrtc_ev_flags;
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gs_pcrtc_stub #(
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.H_ACTIVE(PCRTC_H_ACTIVE), .H_FRONT(1), .H_SYNC(1), .H_BACK(1),
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.V_ACTIVE(PCRTC_V_ACTIVE), .V_FRONT(1), .V_SYNC(1), .V_BACK(1)
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) u_pcrtc (
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.clk(clk), .rst_n(rst_n),
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.pmode_q (pmode_q),
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.dispfb1_q (dispfb1_q),
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.display1_q (display1_q),
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.vram_read_addr(vram_raddr),
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.vram_read_data(vram_rdata),
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.clut_enable (1'b1),
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.clut_csa (tex0_1_csa_q),
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.clut_read_idx (clut_ridx),
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.clut_read_data(clut_rdata),
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.hsync(hsync_o), .vsync(vsync_o), .de(de_o),
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.r(r_o), .g(g_o), .b(b_o),
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.ev_valid(pcrtc_ev_valid),
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.ev_subsys(pcrtc_ev_subsys),
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.ev_event(pcrtc_ev_event),
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.ev_arg0(pcrtc_ev_arg0), .ev_arg1(pcrtc_ev_arg1),
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.ev_arg2(pcrtc_ev_arg2), .ev_arg3(pcrtc_ev_arg3),
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.ev_flags(pcrtc_ev_flags)
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);
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logic [7:0] cap_r [0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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logic [7:0] cap_g [0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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logic [7:0] cap_b [0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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logic cap_de[0:PCRTC_V_ACTIVE-1][0:PCRTC_H_ACTIVE-1];
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int errors;
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bit capture_armed;
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initial begin
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for (int y = 0; y < PCRTC_V_ACTIVE; y++)
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for (int x = 0; x < PCRTC_H_ACTIVE; x++) begin
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cap_r[y][x] = 8'd0;
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cap_g[y][x] = 8'd0;
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cap_b[y][x] = 8'd0;
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cap_de[y][x] = 1'b0;
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end
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errors = 0;
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capture_armed = 1'b0;
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end
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always_ff @(posedge clk) begin
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if (rst_n && capture_armed && de_o
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&& (u_pcrtc.vcnt < PCRTC_V_ACTIVE)
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&& (u_pcrtc.hcnt < PCRTC_H_ACTIVE)) begin
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cap_r [u_pcrtc.vcnt][u_pcrtc.hcnt] <= r_o;
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cap_g [u_pcrtc.vcnt][u_pcrtc.hcnt] <= g_o;
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cap_b [u_pcrtc.vcnt][u_pcrtc.hcnt] <= b_o;
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cap_de[u_pcrtc.vcnt][u_pcrtc.hcnt] <= 1'b1;
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end
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end
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task automatic step_drive(input logic wr_en,
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input logic [7:0] num,
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input logic [63:0] data);
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@(negedge clk);
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gif_reg_wr_en = wr_en;
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gif_reg_num = num;
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gif_reg_data = data;
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@(posedge clk);
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endtask
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task automatic drive_reg(input logic [7:0] num, input logic [63:0] data);
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step_drive(1'b1, num, data);
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endtask
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task automatic drive_idle();
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step_drive(1'b0, 8'd0, 64'd0);
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endtask
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task automatic drive_priv(input logic [15:0] addr,
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input logic [63:0] data);
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@(negedge clk);
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priv_reg_wr_en = 1'b1;
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priv_reg_wr_addr = addr;
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priv_reg_wr_data = data;
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@(posedge clk);
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@(negedge clk);
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priv_reg_wr_en = 1'b0;
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priv_reg_wr_addr = 16'd0;
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priv_reg_wr_data = 64'd0;
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endtask
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task automatic vram_write32(input logic [31:0] addr,
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input logic [31:0] data,
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input logic [3:0] be);
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@(negedge clk);
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vram_we = 1'b1;
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vram_waddr = addr;
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vram_wdata = data;
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vram_wbe = be;
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@(posedge clk);
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@(negedge clk);
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vram_we = 1'b0;
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vram_waddr = 32'd0;
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vram_wdata = 32'd0;
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vram_wbe = 4'b0000;
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endtask
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function automatic logic [31:0] clut_entry(input logic [7:0] i);
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// Same formula as Ch97/Ch98 — A=0xFF, B=i+0x80, G=i+0x40, R=i.
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logic [7:0] r8, g8, b8, a8;
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r8 = i;
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g8 = i + 8'h40;
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b8 = i + 8'h80;
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a8 = 8'hFF;
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return {a8, b8, g8, r8};
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endfunction
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function automatic logic [63:0] tex0_pack(
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input logic [13:0] cbp,
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input logic [3:0] cpsm,
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input logic csm,
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input logic [4:0] csa,
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input logic [2:0] cld);
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logic [63:0] v;
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v = 64'd0;
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v[50:37] = cbp;
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v[54:51] = cpsm;
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v[55] = csm;
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v[60:56] = csa;
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v[63:61] = cld;
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return v;
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endfunction
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localparam logic [7:0] GIF_TEX0_1 = 8'h06;
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localparam logic [15:0] PMODE_OFF = 16'h0000;
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localparam logic [15:0] DISPFB1_OFF = 16'h0070;
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localparam logic [15:0] DISPLAY1_OFF = 16'h0080;
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localparam int SPRITE_W = 4;
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localparam int SPRITE_H = 4;
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localparam logic [7:0] BASE_IDX = 8'h10;
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localparam int ROW_STRIDE = 64; // PSMT8 + FBW=1
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localparam int CLUT_CBP = 4; // CBP*256 = 1024 bytes
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localparam logic [31:0] CLUT_BASE = 32'd1024;
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localparam logic [63:0] DISPFB1_VAL = 64'h0000_0000_0009_8200; // PSMT8/FBW=1/FBP=0
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localparam logic [63:0] DISPLAY1_VAL =
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(64'(PCRTC_H_ACTIVE - 1) << 32)
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| (64'(PCRTC_V_ACTIVE - 1) << 44);
|
||||
localparam logic [63:0] PMODE_EN1 = 64'h0000_0000_0000_0001;
|
||||
|
||||
initial begin
|
||||
rst_n = 1'b0;
|
||||
gif_reg_wr_en = 1'b0;
|
||||
gif_reg_num = 8'd0;
|
||||
gif_reg_data = 64'd0;
|
||||
priv_reg_wr_en = 1'b0;
|
||||
priv_reg_wr_addr = 16'd0;
|
||||
priv_reg_wr_data = 64'd0;
|
||||
vram_we = 1'b0;
|
||||
vram_waddr = 32'd0;
|
||||
vram_wdata = 32'd0;
|
||||
vram_wbe = 4'b0000;
|
||||
|
||||
repeat (4) @(posedge clk);
|
||||
rst_n = 1'b1;
|
||||
repeat (2) @(posedge clk);
|
||||
|
||||
// Stage the PSMT8 sprite at VRAM bytes 0..15 (4×4).
|
||||
for (int y = 0; y < SPRITE_H; y++) begin
|
||||
logic [7:0] i0, i1, i2, i3;
|
||||
logic [31:0] data;
|
||||
int row_base;
|
||||
i0 = BASE_IDX + 8'(y * SPRITE_W + 0);
|
||||
i1 = BASE_IDX + 8'(y * SPRITE_W + 1);
|
||||
i2 = BASE_IDX + 8'(y * SPRITE_W + 2);
|
||||
i3 = BASE_IDX + 8'(y * SPRITE_W + 3);
|
||||
data = {i3, i2, i1, i0};
|
||||
row_base = y * ROW_STRIDE;
|
||||
vram_write32(row_base, data, 4'b1111);
|
||||
end
|
||||
|
||||
// Stage the 256-entry PSMCT32 CLUT in VRAM at CLUT_BASE.
|
||||
// Only the entries the sprite uses (0x10..0x1F) carry
|
||||
// distinguishable values; the rest fill in with their
|
||||
// own clut_entry() values for completeness.
|
||||
for (int i = 0; i < 256; i++) begin
|
||||
logic [31:0] addr;
|
||||
addr = CLUT_BASE + 32'(i * 4);
|
||||
vram_write32(addr, clut_entry(8'(i)), 4'b1111);
|
||||
end
|
||||
|
||||
// ----------------------------------------------------------------
|
||||
// Ch99 audit-medium negative test: a TEX0_1 write with
|
||||
// CSM=0 (CSM1 swizzle) must NOT trigger a load — CSM1 is
|
||||
// out of scope at this chapter, and silently treating it
|
||||
// as CSM2-linear would deposit garbage in clut_stub. We
|
||||
// arm with CLD=1 + CPSM=PSMCT32 + CSM=0; assert loader
|
||||
// stays idle for several cycles, AND assert a different
|
||||
// CBP so any spurious load WOULD have moved data.
|
||||
// ----------------------------------------------------------------
|
||||
drive_reg(GIF_TEX0_1, tex0_pack(14'd0, 4'd0, 1'b0, 5'd0, 3'd1));
|
||||
drive_idle();
|
||||
repeat (16) @(posedge clk);
|
||||
if (loader_busy !== 1'b0) begin
|
||||
$error("CSM=0 TEX0 write started a load (loader_busy=%b)", loader_busy);
|
||||
errors = errors + 1;
|
||||
end
|
||||
|
||||
// Trigger the loader by writing TEX0_1. CSM=1 (CSM2),
|
||||
// CSA=0, CLD=1 ("always load"). CPSM=0 (PSMCT32).
|
||||
drive_reg(GIF_TEX0_1, tex0_pack(14'(CLUT_CBP), 4'd0, 1'b1, 5'd0, 3'd1));
|
||||
drive_idle();
|
||||
|
||||
// Wait for the loader to start, then complete.
|
||||
wait (loader_busy == 1'b1);
|
||||
wait (loader_busy == 1'b0);
|
||||
repeat (4) @(posedge clk);
|
||||
// (CLUT contents are spot-checked indirectly by the
|
||||
// per-pixel scanout assertions below — pcrtc drives
|
||||
// clut_ridx so the TB can't probe it directly.)
|
||||
|
||||
// Configure scanout.
|
||||
drive_priv(DISPFB1_OFF, DISPFB1_VAL);
|
||||
drive_priv(DISPLAY1_OFF, DISPLAY1_VAL);
|
||||
drive_priv(PMODE_OFF, PMODE_EN1);
|
||||
|
||||
@(posedge u_pcrtc.end_of_frame);
|
||||
@(posedge clk);
|
||||
capture_armed = 1'b1;
|
||||
@(posedge u_pcrtc.end_of_frame);
|
||||
@(posedge clk);
|
||||
capture_armed = 1'b0;
|
||||
|
||||
// Per-pixel verification.
|
||||
for (int y = 0; y < PCRTC_V_ACTIVE; y++) begin
|
||||
for (int x = 0; x < PCRTC_H_ACTIVE; x++) begin
|
||||
logic [7:0] er, eg, eb;
|
||||
bit in_sprite;
|
||||
logic [7:0] idx;
|
||||
logic [31:0] entry;
|
||||
|
||||
in_sprite = (x < SPRITE_W) && (y < SPRITE_H);
|
||||
if (in_sprite) begin
|
||||
idx = BASE_IDX + 8'(y * SPRITE_W + x);
|
||||
end else begin
|
||||
// Untouched VRAM bytes read as 0 → idx=0; the
|
||||
// loaded CLUT[0] = clut_entry(0) which is
|
||||
// non-zero. Match against that, not (0,0,0).
|
||||
idx = 8'd0;
|
||||
end
|
||||
entry = clut_entry(idx);
|
||||
er = entry[7:0];
|
||||
eg = entry[15:8];
|
||||
eb = entry[23:16];
|
||||
|
||||
if (!cap_de[y][x]) begin
|
||||
$error("(%0d,%0d) DE never asserted", x, y);
|
||||
errors = errors + 1;
|
||||
end
|
||||
if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
|
||||
$error("(%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x) in_sprite=%0d",
|
||||
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x],
|
||||
er, eg, eb, in_sprite);
|
||||
errors = errors + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
$display("[tb_gs_clut_load] CBP=%0d CLD=1 256-entry load → PSMT8 scanout uses CLUT-decoded RGB",
|
||||
CLUT_CBP);
|
||||
|
||||
if (errors == 0) $display("[tb_gs_clut_load] PASS");
|
||||
else $display("[tb_gs_clut_load] FAIL");
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#5000000;
|
||||
$error("[tb_gs_clut_load] timeout");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule : tb_gs_clut_load
|
||||
Reference in New Issue
Block a user