Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

rtl/top/de25_nano_pll_stub.sv

@@ -0,0 +1,45 @@
+// retroDE_ps2 — de25_nano_pll_stub (Ch151)
+//
+// Sim-friendly stub matching the Quartus IOPLL "pll" module signature
+// used by sibling cores (retroDE_nes/ip/pll/pll_bb.v and
+// retroDE_splash/ip/sys_pll/sys_pll_bb.v). Real synthesis swaps this
+// stub for Terasic-supplied IP via Quartus's IP catalog and a
+// `\`ifdef USE_PLL_IP` gate in the board top.
+//
+// Behavior:
+//   - `outclk_0` is a direct pass-through of `refclk` (no PLL
+//     multiplication; sim doesn't need a different frequency, and a
+//     pass-through still exercises the PLL-gated reset bridge in the
+//     Ch149 board top).
+//   - `locked` rises after a small post-reset delay (~32 cycles),
+//     mimicking real-IP behavior where lock acquires after rst goes
+//     low. Held LOW while `rst` is HIGH.
+//
+// The signature matches Quartus's IOPLL exactly so swapping in the
+// real IP is a single `\`ifdef` at instantiation; the rest of the
+// board top is unchanged.
+
+`timescale 1ns/1ps
+
+module de25_nano_pll_stub (
+    input  wire  refclk,   // reference clock from CLOCK2_50
+    input  wire  rst,      // active-HIGH async reset (Quartus convention)
+    output wire  outclk_0, // pass-through of refclk
+    output wire  locked    // high once "lock" is acquired
+);
+
+    assign outclk_0 = refclk;
+
+    // Lock counter — tick up while rst is low; saturate at 32 and hold
+    // `locked` high. While rst is high, hold counter at 0 and locked low.
+    logic [5:0] lock_cnt;
+    always_ff @(posedge refclk or posedge rst) begin
+        if (rst)
+            lock_cnt <= 6'd0;
+        else if (lock_cnt < 6'd32)
+            lock_cnt <= lock_cnt + 6'd1;
+    end
+
+    assign locked = (lock_cnt == 6'd32);
+
+endmodule : de25_nano_pll_stub