Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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// Copyright (c) 2025-2026 retroDE contributors
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// ============================================================================
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// sio2_input_stub — Ch234 retroDE-local IOP-readable pad input stub
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// ============================================================================
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// **Not real SIO2.** A deliberately minimal MMIO surface that translates
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// the Ch222 HPS-written `INPUT_P1`/`INPUT_P2` controller bitmaps into a
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// Sony-format 16-bit digital pad word, exposed as IOP-readable
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// registers in the retroDE-local I/O window
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// `0x1F80_8500..0x1F80_85FF`. Real SIO2 emulation (`0x1F80_8200..0x1F80_82FF`,
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// FIFO, command/response, IOP DMAC channel 11) is intentionally deferred
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// — see `docs/contracts/sio2_pad.md` for the reconnaissance + scoping.
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//
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// **Register surface** (offsets relative to PAD_IO_BASE = 0x1F80_8500):
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//
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// 0x500 PAD_P1_STATE (RO) [15:0] = Sony 16-bit pad word for P1
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// [31:16] = 0
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// 0x504 PAD_P2_STATE (RO) Same shape, sourced from `input_p2`.
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// 0x508 PAD_STATUS (RO) [0] = pad path present/valid = 1
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// [31:1] = 0
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// other reserved reads return 32'd0; writes accepted-and-ignored.
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//
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// **Sony pad word format (Sony "digital mode" / type 0x41 response,
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// bytes 3 and 4 of the libpad/padman struct):**
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//
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// pad_byte3 (D-pad / start / select / sticks; active-low, 0 = pressed):
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// bit 7 LEFT bit 6 DOWN bit 5 RIGHT bit 4 UP
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// bit 3 START bit 2 R3 bit 1 L3 bit 0 SELECT
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//
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// pad_byte4 (face / shoulder buttons; active-low):
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// bit 7 □ square bit 6 × cross bit 5 ○ circle bit 4 △ triangle
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// bit 3 R1 bit 2 L1 bit 1 R2 bit 0 L2
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//
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// PAD_P1_STATE[7:0] = pad_byte3
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// PAD_P1_STATE[15:8] = pad_byte4
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//
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// **INPUT_P1 → Sony mapping** (per `docs/contracts/sio2_pad.md`,
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// SNES-style 32-bit retroDE bitmap folded onto Sony names by spatial
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// face-button layout — matches the convention coco2 / a2600 already use):
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//
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// INPUT_P1[ 0] JOY_RIGHT → Sony RIGHT (byte3.5)
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// INPUT_P1[ 1] JOY_LEFT → Sony LEFT (byte3.7)
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// INPUT_P1[ 2] JOY_DOWN → Sony DOWN (byte3.6)
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// INPUT_P1[ 3] JOY_UP → Sony UP (byte3.4)
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// INPUT_P1[ 4] JOY_START → Sony START (byte3.3)
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// INPUT_P1[ 5] JOY_SELECT → Sony SELECT (byte3.0)
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// INPUT_P1[ 6] JOY_Y → Sony △ triangle (byte4.4)
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// INPUT_P1[ 7] JOY_B → Sony × cross (byte4.6)
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// INPUT_P1[ 8] JOY_X → Sony □ square (byte4.7)
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// INPUT_P1[ 9] JOY_A → Sony ○ circle (byte4.5)
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// INPUT_P1[10] JOY_L → Sony L1 (byte4.2)
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// INPUT_P1[11] JOY_R → Sony R1 (byte4.3)
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// INPUT_P1[12] JOY_L2 → Sony L2 (byte4.0)
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// INPUT_P1[13] JOY_R2 → Sony R2 (byte4.1)
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// INPUT_P1[14] JOY_L3 → Sony L3 (byte3.1)
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// INPUT_P1[15] JOY_R3 → Sony R3 (byte3.2)
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// INPUT_P1[16] JOY_OSD → not forwarded (retrodesd consumes it)
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//
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// retroDE bitmap is **active-high** (1 = pressed); Sony word is
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// **active-low** (0 = pressed). The two `pad_byteN` assigns invert
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// per-bit and reorder.
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//
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// **CDC contract.** `input_p1`/`input_p2` are bridge-clock-domain
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// signals (CLOCK2_50). This module runs on the IOP/design clock.
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// The 2-FF synchronizer chain inside is the standard retroDE
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// single-bit sync; tearing between bits during a partial-write
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// settling window is theoretically possible but practically
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// vanishingly rare (retrodesd writes the whole 32-bit latch at
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// one bridge edge ≤ 1 kHz; the IOP-side read is a small window
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// against millions of bridge cycles). A future chapter can promote
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// this to "snapshot CDC" (latch + 2-sample coherency) if tearing
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// ever becomes observable.
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//
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// In the focused TB and single-clock sim setups, the 2-FF sync is
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// a no-op functionally and adds 2 cycles of read latency from
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// input change to readable register update.
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// ============================================================================
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`timescale 1ns/1ps
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module sio2_input_stub (
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input logic clk, // IOP / design clock
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input logic rst_n,
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// Bridge-clock-domain inputs (sync'd internally).
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input logic [31:0] input_p1,
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input logic [31:0] input_p2,
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// IOP map read port. `rd_addr` is the 4-bit word offset within
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// the PAD I/O region (so 0x500 → addr 0x0, 0x504 → 0x1, etc.).
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input logic rd_en,
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input logic [3:0] rd_addr,
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output logic [31:0] rd_data,
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output logic rd_valid,
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// IOP map write port. Writes are accepted-and-ignored.
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input logic wr_en,
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input logic [3:0] wr_addr,
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input logic [31:0] wr_data,
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// Ch250 — surface the post-translation Sony 16-bit pad words for
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// fabric consumers that don't go through the IOP read memory map.
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// The synth top uses `p1_sony_word_o` bits to drive status LEDs as
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// a hardware proof that `bridge_input_p1_raw` actually reaches a
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// live fabric consumer. (Ch241 noted those wires terminated at
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// unconnected nets that Quartus elided; Ch250 ends that.) Bits
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// are still active-LOW per Sony's wire-format convention. Both
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// outputs are parallel taps of the same internal logic that feeds
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// the 0x500/0x504 read responses — no functional change to the
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// existing IOP-side path.
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output logic [15:0] p1_sony_word_o,
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output logic [15:0] p2_sony_word_o
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);
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// -----------------------------------------------------------------
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// 2-FF sync of each P1/P2 bit into the IOP clock domain.
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// -----------------------------------------------------------------
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logic [31:0] p1_sync_0, p1_sync_1;
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logic [31:0] p2_sync_0, p2_sync_1;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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p1_sync_0 <= 32'd0;
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p1_sync_1 <= 32'd0;
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p2_sync_0 <= 32'd0;
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p2_sync_1 <= 32'd0;
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end else begin
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p1_sync_0 <= input_p1;
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p1_sync_1 <= p1_sync_0;
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p2_sync_0 <= input_p2;
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p2_sync_1 <= p2_sync_0;
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end
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end
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wire [31:0] p1_q = p1_sync_1;
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wire [31:0] p2_q = p2_sync_1;
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// -----------------------------------------------------------------
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// Sony pad-word translation. Each `pad_byteN` is the *active-low*
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// Sony byte; inversion folds the active-high retroDE bitmap.
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// Bit positions per `docs/contracts/sio2_pad.md`:
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// byte3 = {LEFT, DOWN, RIGHT, UP, START, R3, L3, SELECT} (MSB→LSB)
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// byte4 = {□, ×, ○, △, R1, L1, R2, L2}
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// -----------------------------------------------------------------
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function automatic logic [15:0] sony_word(input logic [31:0] joy);
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logic [7:0] byte3;
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logic [7:0] byte4;
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// byte3 MSB→LSB: LEFT[1], DOWN[2], RIGHT[0], UP[3], START[4], R3[15], L3[14], SELECT[5]
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byte3 = ~{joy[1], joy[2], joy[0], joy[3], joy[4], joy[15], joy[14], joy[5]};
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// byte4 MSB→LSB: SQUARE[8], CROSS[7], CIRCLE[9], TRIANGLE[6], R1[11], L1[10], R2[13], L2[12]
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byte4 = ~{joy[8], joy[7], joy[9], joy[6], joy[11], joy[10], joy[13], joy[12]};
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sony_word = {byte4, byte3};
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endfunction
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wire [15:0] p1_word = sony_word(p1_q);
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wire [15:0] p2_word = sony_word(p2_q);
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// Ch250 — surface the post-translation Sony words to fabric.
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assign p1_sony_word_o = p1_word;
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assign p2_sony_word_o = p2_word;
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// -----------------------------------------------------------------
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// Register address constants (word-aligned within the PAD I/O
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// region; address bits [3:2] passed in as `rd_addr[1:0]`).
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// 0x500 → rd_addr = 4'h0 PAD_P1_STATE
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// 0x504 → rd_addr = 4'h1 PAD_P2_STATE
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// 0x508 → rd_addr = 4'h2 PAD_STATUS
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// -----------------------------------------------------------------
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localparam logic [3:0] OFF_P1_STATE = 4'h0;
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localparam logic [3:0] OFF_P2_STATE = 4'h1;
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localparam logic [3:0] OFF_STATUS = 4'h2;
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// -----------------------------------------------------------------
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// Read response. Combinational lookup + 1-cycle valid pipeline
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// (matches the rest of the IOP map peripherals).
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// -----------------------------------------------------------------
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logic [31:0] rd_data_c;
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always_comb begin
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unique case (rd_addr)
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OFF_P1_STATE: rd_data_c = {16'd0, p1_word};
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OFF_P2_STATE: rd_data_c = {16'd0, p2_word};
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OFF_STATUS: rd_data_c = {31'd0, 1'b1};
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default: rd_data_c = 32'd0;
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endcase
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end
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_data <= 32'd0;
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rd_valid <= 1'b0;
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end else begin
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rd_valid <= rd_en;
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if (rd_en)
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rd_data <= rd_data_c;
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end
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end
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// -----------------------------------------------------------------
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// Writes are accepted-and-ignored. We tie `wr_*` to a placeholder
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// wire so lint tools don't flag them as unused.
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// -----------------------------------------------------------------
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// verilator lint_off UNUSED
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wire _wr_unused = &{1'b0, wr_en, wr_addr, wr_data, 1'b0};
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// verilator lint_on UNUSED
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endmodule : sio2_input_stub
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