Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
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// retroDE_ps2 — iop_dmac_reg_stub
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//
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// IOP DMAC channel 9 (SIF0 IOP→EE) with a real, bounded data path.
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// Upgraded from the earlier register+lifecycle shell: MADR is a real
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// source pointer into IOP RAM, BCR is a real word count, and the
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// state machine pulls 32-bit beats out of IOP RAM through the IOP map
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// and emits them on a word-granularity endpoint with ready/valid/last
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// handshake. Mirrors the EE DMAC shape (dmac_reg_stub) at 32-bit width.
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//
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// Contract refs:
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// docs/contracts/iop.md (IOP DMAC ownership)
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//
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// Register surface (per-channel, low-byte offset):
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// 0x00 MADR — real source address in IOP physical space
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// 0x04 BCR — transfer length in 32-bit beats
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// 0x08 CHCR — channel control; bit[0] is the start bit
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// 0x0C DONE_COUNT — monotonic completion counter (read-only; writes
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// are accepted but ignored). Software reads this
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// to distinguish "nth completion" without needing
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// to count interrupts externally.
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// Other offsets: writes accepted but ignored; reads return 0.
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//
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// Memory master interface (to iop_memory_map_stub's dma_rd_* port):
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// mem_rd_en / mem_rd_addr issue the request (one cycle)
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// mem_rd_valid / mem_rd_data return the word one cycle later
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// mem_master_id drives the map trace attribution (convention: 4)
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//
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// Endpoint (to sif_dma_ee_ram_bridge_stub or similar 32-bit sink):
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// ep_valid / ep_data[31:0] / ep_last
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// ep_ready is the backpressure signal — when low, the state machine
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// holds in ACTIVE_SEND with the current beat. No false completion.
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//
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// State machine:
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// IDLE → FETCH_WAIT on CHCR start
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// FETCH_WAIT → ACTIVE_SEND on mem_rd_valid (word latched)
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// ACTIVE_SEND → FETCH_WAIT on endpoint accept with more beats left
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// → DONE on endpoint accept for the final beat
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// DONE → IDLE next cycle (clears CHCR.start)
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//
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// Source stepping: src_addr = madr_latched + (beat_index * 4).
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//
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// Trace payload schema (SUBSYS_DMAC):
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// DMA_CFG arg0=channel arg1=chcr arg2=madr arg3=bcr flags=reg_offset
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// DMA_START arg0=channel arg1=bcr arg2=madr arg3=path_id
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// DMA_BEAT arg0=channel arg1=beat_index arg2=src_addr arg3=remaining
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// DMA_DONE arg0=channel arg1=beats arg2=completion_code arg3=path_id
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// completion_code 0 = OK.
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`timescale 1ns/1ps
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module iop_dmac_reg_stub
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import trace_pkg::*;
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#(
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parameter logic [3:0] CHANNEL = 4'd9, // SIF0 (IOP → EE)
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parameter logic [3:0] PATH_ID = 4'd9,
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parameter logic [7:0] MASTER_ID = 8'd4 // for dma_rd trace attribution
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) (
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input logic clk,
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input logic rst_n,
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// IOP-side register access (from the memory map's iop_dmac_* port)
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input logic reg_wr_en,
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input logic reg_rd_en,
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input logic [3:0] reg_offset,
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input logic [31:0] reg_wr_data,
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output logic [31:0] reg_rd_data,
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output logic reg_rd_valid,
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// Memory read master (to iop_memory_map_stub dma_rd_* port)
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output logic mem_rd_en,
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output logic [31:0] mem_rd_addr,
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output logic [7:0] mem_master_id,
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input logic [31:0] mem_rd_data,
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input logic mem_rd_valid,
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// Endpoint (word-granularity stream to SIF egress bridge)
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output logic ep_valid,
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output logic [31:0] ep_data,
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output logic ep_last,
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input logic ep_ready,
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// Completion pulse — one cycle high when the channel reaches S_DONE.
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// Intended as an IOP INTC source; latching is the interrupt
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// controller's responsibility.
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output logic irq_completion_o,
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// Status
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output logic busy_o,
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output logic [31:0] done_count_o,
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// Trace
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output logic ev_valid,
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output subsys_e ev_subsys,
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output event_e ev_event,
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output logic [63:0] ev_arg0,
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output logic [63:0] ev_arg1,
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output logic [63:0] ev_arg2,
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output logic [63:0] ev_arg3,
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output logic [31:0] ev_flags
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);
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localparam logic [3:0] MADR_OFFSET = 4'h0;
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localparam logic [3:0] BCR_OFFSET = 4'h4;
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localparam logic [3:0] CHCR_OFFSET = 4'h8;
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localparam logic [3:0] DONE_COUNT_OFFSET = 4'hC;
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typedef enum logic [1:0] {
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S_IDLE = 2'd0,
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S_FETCH_WAIT = 2'd1,
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S_ACTIVE_SEND = 2'd2,
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S_DONE = 2'd3
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} state_e;
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logic [31:0] madr;
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logic [31:0] bcr;
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logic [31:0] chcr;
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state_e state;
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logic [31:0] madr_latched;
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logic [31:0] bcr_latched;
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logic [31:0] beat_index;
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logic [31:0] beat_payload;
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logic start_pulse;
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assign start_pulse = reg_wr_en && (reg_offset == CHCR_OFFSET)
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&& reg_wr_data[0] && !chcr[0];
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// ------------------------------------------------------------------
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// Register file
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// ------------------------------------------------------------------
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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madr <= 32'd0;
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bcr <= 32'd0;
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chcr <= 32'd0;
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end else begin
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if (reg_wr_en) begin
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case (reg_offset)
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MADR_OFFSET: madr <= reg_wr_data;
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BCR_OFFSET: bcr <= reg_wr_data;
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CHCR_OFFSET: chcr <= reg_wr_data;
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default: ;
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endcase
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end
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if (state == S_DONE) chcr[0] <= 1'b0;
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end
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end
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// ------------------------------------------------------------------
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// Register read (1-cycle latency, matches rest of stub ecosystem)
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// ------------------------------------------------------------------
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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reg_rd_data <= 32'd0;
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reg_rd_valid <= 1'b0;
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end else begin
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reg_rd_valid <= reg_rd_en;
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if (reg_rd_en) begin
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case (reg_offset)
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MADR_OFFSET: reg_rd_data <= madr;
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BCR_OFFSET: reg_rd_data <= bcr;
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CHCR_OFFSET: reg_rd_data <= chcr;
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DONE_COUNT_OFFSET: reg_rd_data <= done_count_o;
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default: reg_rd_data <= 32'd0;
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endcase
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end
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end
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end
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// ------------------------------------------------------------------
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// Transfer state machine
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// ------------------------------------------------------------------
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logic [31:0] src_addr;
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assign src_addr = madr_latched + (beat_index << 2); // 4 bytes/beat
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logic beat_accepted;
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assign beat_accepted = ep_valid && ep_ready;
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// Pulse mem_rd_en for one cycle whenever we first enter FETCH_WAIT.
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logic prev_state_fw;
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always_ff @(posedge clk) begin
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if (!rst_n) prev_state_fw <= 1'b0;
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else prev_state_fw <= (state == S_FETCH_WAIT);
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end
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logic entering_fw;
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assign entering_fw = (state == S_FETCH_WAIT) && !prev_state_fw;
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assign mem_rd_en = entering_fw;
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assign mem_rd_addr = src_addr;
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assign mem_master_id = MASTER_ID;
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// Drive endpoint only in ACTIVE_SEND with the latched payload.
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assign ep_valid = (state == S_ACTIVE_SEND);
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assign ep_data = beat_payload;
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assign ep_last = (state == S_ACTIVE_SEND) &&
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(beat_index + 32'd1 == bcr_latched);
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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state <= S_IDLE;
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madr_latched <= 32'd0;
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bcr_latched <= 32'd0;
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beat_index <= 32'd0;
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beat_payload <= 32'd0;
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end else begin
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unique case (state)
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S_IDLE: begin
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if (start_pulse) begin
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state <= S_FETCH_WAIT;
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madr_latched <= madr;
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bcr_latched <= bcr;
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beat_index <= 32'd0;
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end
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end
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S_FETCH_WAIT: begin
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if (mem_rd_valid) begin
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beat_payload <= mem_rd_data;
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state <= S_ACTIVE_SEND;
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end
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end
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S_ACTIVE_SEND: begin
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if (beat_accepted) begin
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if (beat_index + 32'd1 == bcr_latched) begin
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state <= S_DONE;
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end else begin
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beat_index <= beat_index + 32'd1;
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state <= S_FETCH_WAIT;
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end
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end
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end
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S_DONE: begin
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state <= S_IDLE;
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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assign busy_o = (state != S_IDLE);
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assign irq_completion_o = (state == S_DONE);
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// ------------------------------------------------------------------
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// Trace emission — one event per cycle. Priority:
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// DONE > BEAT > START > CFG (register write)
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// ------------------------------------------------------------------
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logic prev_in_transfer;
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always_ff @(posedge clk) begin
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if (!rst_n) prev_in_transfer <= 1'b0;
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else prev_in_transfer <= (state != S_IDLE);
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end
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logic enter_start;
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assign enter_start = (state == S_FETCH_WAIT) && !prev_in_transfer;
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logic enter_done;
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assign enter_done = (state == S_DONE);
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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ev_valid <= 1'b0;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_DMA_CFG;
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ev_arg0 <= 64'd0;
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ev_arg1 <= 64'd0;
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ev_arg2 <= 64'd0;
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ev_arg3 <= 64'd0;
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ev_flags <= 32'd0;
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done_count_o <= 32'd0;
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end else if (enter_done) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_DMA_DONE;
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ev_arg0 <= {60'd0, CHANNEL};
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ev_arg1 <= {32'd0, beat_index + 32'd1}; // beats completed
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ev_arg2 <= 64'd0; // completion OK
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ev_arg3 <= {60'd0, PATH_ID};
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ev_flags <= 32'd0;
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done_count_o <= done_count_o + 32'd1;
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end else if (beat_accepted) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_DMA_BEAT;
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ev_arg0 <= {60'd0, CHANNEL};
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ev_arg1 <= {32'd0, beat_index};
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ev_arg2 <= {32'd0, src_addr};
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ev_arg3 <= {32'd0, bcr_latched - beat_index - 32'd1};
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ev_flags <= 32'd0;
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end else if (enter_start) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_DMA_START;
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ev_arg0 <= {60'd0, CHANNEL};
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ev_arg1 <= {32'd0, bcr_latched};
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ev_arg2 <= {32'd0, madr_latched};
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ev_arg3 <= {60'd0, PATH_ID};
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ev_flags <= 32'd0;
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end else if (reg_wr_en) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_DMA_CFG;
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ev_arg0 <= {60'd0, CHANNEL};
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ev_arg1 <= {32'd0, (reg_offset == CHCR_OFFSET) ? reg_wr_data : chcr};
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ev_arg2 <= {32'd0, (reg_offset == MADR_OFFSET) ? reg_wr_data : madr};
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ev_arg3 <= {32'd0, (reg_offset == BCR_OFFSET) ? reg_wr_data : bcr};
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ev_flags <= {28'd0, reg_offset};
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end else begin
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ev_valid <= 1'b0;
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end
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end
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endmodule : iop_dmac_reg_stub
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