Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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// retroDE_ps2 — ee_dmac_passive_chan_stub
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//
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// Ch288 — Lightweight per-channel register surface for the EE DMAC
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// channels NOT covered by a dedicated transfer-FSM stub. Hosts the
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// four standard per-channel registers (CHCR/MADR/QWC/TADR) for each
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// covered channel; reset to zero, writes latch, reads return the
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// latched value. NO transfer FSM, NO start-bit side effects, NO
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// D_STAT interaction. This is the "init-time channel-clear / quiet
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// register surface" Codex framed for Ch288.
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//
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// Channels covered (4 KiB window each, starting at 0x1000_8000):
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// ch0 (VIF0) 0x1000_8000-0x1000_8FFF
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// ch1 (VIF1) 0x1000_9000-0x1000_9FFF
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// ch3 (IPU_FROM) 0x1000_B000-0x1000_BFFF
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// ch4 (IPU_TO) 0x1000_C000-0x1000_CFFF ← qbert's first hit
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// ch5 (SIF0) 0x1000_D000-0x1000_DFFF
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//
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// SKIPPED:
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// ch2 (GIF) 0x1000_A000-0x1000_AFFF — already routed
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// externally to dmac_reg_stub via the map's
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// ee_dmac_ch2_* ports. Do NOT shadow it here.
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//
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// Channel index extracted from chan_addr[15:12]:
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// 0x8 → ch0, 0x9 → ch1, 0xB → ch3, 0xC → ch4, 0xD → ch5
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// (0xA / ch2 is filtered by the caller; if chan_addr[15:12]==0xA
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// arrives here the module silently drops it.)
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//
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// Register offsets (chan_addr[11:0], matches dmac_reg_stub layout):
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// 0x00 CHCR — control (start bit at [0]); latched, no FSM
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// 0x10 MADR — main address
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// 0x20 QWC — quadword count
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// 0x30 TADR — tag address
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// any other offset: read = 0, write dropped + traced
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`timescale 1ns/1ps
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module ee_dmac_passive_chan_stub
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import trace_pkg::*;
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(
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input logic clk,
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input logic rst_n,
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// Write port. chan_addr is the 16-bit offset into the entire
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// 0x1000_8000-base window: chan_addr[15:12] = channel selector,
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// chan_addr[11:0] = register offset within that channel.
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input logic reg_wr_en,
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input logic [15:0] chan_addr,
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input logic [31:0] reg_wr_data,
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// Read port (1-cycle latency).
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input logic reg_rd_en,
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output logic [31:0] reg_rd_data,
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output logic reg_rd_valid,
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// Trace
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output logic ev_valid,
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output subsys_e ev_subsys,
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output event_e ev_event,
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output logic [63:0] ev_arg0,
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output logic [63:0] ev_arg1,
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output logic [63:0] ev_arg2,
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output logic [63:0] ev_arg3,
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output logic [31:0] ev_flags
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);
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localparam logic [11:0] CHCR_OFFSET = 12'h000;
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localparam logic [11:0] MADR_OFFSET = 12'h010;
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localparam logic [11:0] QWC_OFFSET = 12'h020;
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localparam logic [11:0] TADR_OFFSET = 12'h030;
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// Channel index from the high nibble of chan_addr. Out-of-range
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// nibbles (anything outside 0x8/0x9/0xB/0xC/0xD) get
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// chan_valid=0 and the access is dropped.
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logic [3:0] chan_nibble;
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logic [2:0] chan_idx; // 0..4 packed: 0=ch0, 1=ch1, 2=ch3, 3=ch4, 4=ch5
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logic chan_valid;
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always_comb begin
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chan_nibble = chan_addr[15:12];
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chan_idx = 3'd0;
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chan_valid = 1'b0;
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unique case (chan_nibble)
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4'h8: begin chan_idx = 3'd0; chan_valid = 1'b1; end // ch0
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4'h9: begin chan_idx = 3'd1; chan_valid = 1'b1; end // ch1
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4'hB: begin chan_idx = 3'd2; chan_valid = 1'b1; end // ch3
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4'hC: begin chan_idx = 3'd3; chan_valid = 1'b1; end // ch4
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4'hD: begin chan_idx = 3'd4; chan_valid = 1'b1; end // ch5
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default: ;
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endcase
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end
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logic [11:0] reg_offset;
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assign reg_offset = chan_addr[11:0];
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// ------------------------------------------------------------------
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// Register file: 5 channels × 4 registers
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// ------------------------------------------------------------------
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logic [31:0] chcr [0:4];
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logic [31:0] madr [0:4];
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logic [31:0] qwc [0:4];
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logic [31:0] tadr [0:4];
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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for (int i = 0; i < 5; i++) begin
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chcr[i] <= 32'd0;
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madr[i] <= 32'd0;
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qwc[i] <= 32'd0;
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tadr[i] <= 32'd0;
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end
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end else if (reg_wr_en && chan_valid) begin
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unique case (reg_offset)
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CHCR_OFFSET: chcr[chan_idx] <= reg_wr_data;
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MADR_OFFSET: madr[chan_idx] <= reg_wr_data;
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QWC_OFFSET: qwc[chan_idx] <= reg_wr_data;
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TADR_OFFSET: tadr[chan_idx] <= reg_wr_data;
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default: ;
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endcase
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end
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end
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// Read mux (1-cycle latency). Returns 0 for invalid channel /
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// unknown offset.
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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reg_rd_data <= 32'd0;
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reg_rd_valid <= 1'b0;
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end else begin
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reg_rd_valid <= reg_rd_en;
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if (reg_rd_en && chan_valid) begin
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unique case (reg_offset)
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CHCR_OFFSET: reg_rd_data <= chcr[chan_idx];
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MADR_OFFSET: reg_rd_data <= madr[chan_idx];
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QWC_OFFSET: reg_rd_data <= qwc[chan_idx];
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TADR_OFFSET: reg_rd_data <= tadr[chan_idx];
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default: reg_rd_data <= 32'd0;
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endcase
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end else if (reg_rd_en) begin
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reg_rd_data <= 32'd0; // invalid channel
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end
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end
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end
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// ------------------------------------------------------------------
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// Trace — write priority over read; tagged SUBSYS_DMAC with
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// arg0 = chan_nibble (0x8/0x9/0xB/0xC/0xD = phys channel), arg1
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// = data, arg2 = reg_offset, arg3 = chan_idx (packed 0..4).
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// ------------------------------------------------------------------
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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ev_valid <= 1'b0;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_WRITE;
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ev_arg0 <= 64'd0;
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ev_arg1 <= 64'd0;
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ev_arg2 <= 64'd0;
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ev_arg3 <= 64'd0;
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ev_flags <= 32'd0;
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end else if (reg_wr_en) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_WRITE;
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ev_arg0 <= {60'd0, chan_nibble};
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ev_arg1 <= {32'd0, reg_wr_data};
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ev_arg2 <= {52'd0, reg_offset};
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ev_arg3 <= {61'd0, chan_idx};
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ev_flags <= {31'd0, chan_valid};
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end else if (reg_rd_en) begin
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ev_valid <= 1'b1;
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ev_subsys <= SUBSYS_DMAC;
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ev_event <= EV_READ;
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ev_arg0 <= {60'd0, chan_nibble};
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ev_arg1 <= 64'd0;
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ev_arg2 <= {52'd0, reg_offset};
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ev_arg3 <= {61'd0, chan_idx};
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ev_flags <= {31'd0, chan_valid};
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end else begin
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ev_valid <= 1'b0;
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end
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end
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endmodule : ee_dmac_passive_chan_stub
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