Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
@@ -0,0 +1,27 @@
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DEFINE std $CDS_ROOT/tools/inca/files/STD/
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||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
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||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
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||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
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||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
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||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
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||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
DEFINE work ./libraries/work/
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||||
DEFINE altera_merlin_axi_translator_1987 ./libraries/altera_merlin_axi_translator_1987/
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||||
DEFINE altera_merlin_slave_translator_191 ./libraries/altera_merlin_slave_translator_191/
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||||
DEFINE altera_merlin_axi_master_ni_19117 ./libraries/altera_merlin_axi_master_ni_19117/
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||||
DEFINE altera_merlin_slave_agent_1930 ./libraries/altera_merlin_slave_agent_1930/
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DEFINE altera_avalon_sc_fifo_1932 ./libraries/altera_avalon_sc_fifo_1932/
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DEFINE altera_merlin_router_1921 ./libraries/altera_merlin_router_1921/
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||||
DEFINE altera_avalon_st_pipeline_stage_1930 ./libraries/altera_avalon_st_pipeline_stage_1930/
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DEFINE altera_merlin_burst_adapter_1940 ./libraries/altera_merlin_burst_adapter_1940/
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DEFINE altera_merlin_demultiplexer_1921 ./libraries/altera_merlin_demultiplexer_1921/
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DEFINE altera_merlin_multiplexer_1922 ./libraries/altera_merlin_multiplexer_1922/
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DEFINE altera_mm_interconnect_1920 ./libraries/altera_mm_interconnect_1920/
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DEFINE altera_irq_mapper_2001 ./libraries/altera_irq_mapper_2001/
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DEFINE altera_reset_controller_1924 ./libraries/altera_reset_controller_1924/
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DEFINE qsys_top ./libraries/qsys_top/
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SOFTINCLUDE _device.cds.lib
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INCLUDE _default.cds.lib
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@@ -0,0 +1,10 @@
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DEFINE std $CDS_ROOT/tools/inca/files/STD/
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||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
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DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
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DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
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||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
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DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
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DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
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DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
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@@ -0,0 +1,2 @@
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DEFINE WORK work
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Executable
+440
@@ -0,0 +1,440 @@
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# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
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||||
|
||||
# ----------------------------------------
|
||||
# xcelium - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# qsys_top
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# Xcelium Simulation Script.
|
||||
# To write a top-level shell script that compiles Intel simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "xcelium_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated files
|
||||
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
|
||||
# # into the location from which you launch the simulator, or incorporate
|
||||
# # into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/xcelium/xcelium_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# xmvlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/xcelium/xcelium_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If qsys_top is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:52:56
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="qsys_top.qsys_top"
|
||||
QSYS_SIMDIR="./../"
|
||||
QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
|
||||
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
DEFAULT_ELAB_OPTIONS=" -access +w+r+c -update -namemap_mixgen +DISABLEGENCHK -relax"
|
||||
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# check tclsh version no earlier than 8.5
|
||||
version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
|
||||
if [ $version -eq -1 ]; then
|
||||
echo "Error: Minimum required tcl package version is 8.5." >&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# read .sh file to override initialized variables
|
||||
if [ -n "${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} ]; then
|
||||
echo "Sourcing ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}"
|
||||
source ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error:: This file ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} has invalid expression/s" >&2
|
||||
exit $?
|
||||
fi
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `xmsim -version` != *"xmsim(64)"* ]]; then
|
||||
SIMULATOR_TOOL_BITNESS="bit_32"
|
||||
else
|
||||
SIMULATOR_TOOL_BITNESS="bit_64"
|
||||
fi
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [qsys_top::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
|
||||
puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
|
||||
}
|
||||
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [qsys_top::get_elab_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [qsys_top::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
eval $cmd_output
|
||||
|
||||
#-------------------------------------------
|
||||
# Decision to skip device compilation,
|
||||
# based on value of PRECOMP_DEVICE_LIB_FILE.
|
||||
# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
|
||||
if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
|
||||
SKIP_DEV_COM=1
|
||||
else
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
fi
|
||||
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set libraries [dict merge $libraries [qsys_top::get_design_libraries]]
|
||||
set design_libraries [dict keys $libraries]
|
||||
foreach file $design_libraries { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver tennm_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
fi
|
||||
|
||||
for library in $design_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
mkdir -p ./libraries/work
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _device.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > _device.cds.lib
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "DEFINE $library ./libraries/$library" >> _device.cds.lib
|
||||
done
|
||||
else
|
||||
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> _device.cds.lib
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# write out device.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > ./cds_libs/device.cds.lib
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "DEFINE $library ./../libraries/$library" >> ./cds_libs/device.cds.lib
|
||||
done
|
||||
else
|
||||
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> ./cds_libs/device.cds.lib
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _default.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > _default.cds.lib
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "DEFINE $library ./libraries/$library" >> _default.cds.lib
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# create cds_libs for each design library
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "INCLUDE simulator.cds.lib" > cds_libs/$library.cds.lib
|
||||
echo "INCLUDE device.cds.lib" >> cds_libs/$library.cds.lib
|
||||
if [[ $design_libraries =~ "altera_common_sv_packages" ]] && [[ $library != "altera_common_sv_packages" ]]; then
|
||||
echo "DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/" >> cds_libs/$library.cds.lib
|
||||
fi
|
||||
echo "DEFINE $library ./../libraries/$library" >> cds_libs/$library.cds.lib
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 2]
|
||||
set memory_files [list]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set memory_files [concat $memory_files [qsys_top::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
memory_files=$cmd_output
|
||||
if [ $SKIP_FILE_COPY -eq 0 ]; then
|
||||
for file in $memory_files
|
||||
do
|
||||
cp -f $file ./
|
||||
done
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/cadence/tennm_atoms_ncrypt.sv" -work tennm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
||||
fi
|
||||
gcc -fPIC -g -shared -o libdpi.so -I/`ncroot`/tools/inca/include "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp"
|
||||
|
||||
# ----------------------------------------
|
||||
# add device library elaboration and simulation properties
|
||||
|
||||
# ----------------------------------------
|
||||
# get common system verilog package design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set design_files [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set design_files [dict merge $design_files [qsys_top::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
||||
set common_design_files [dict values $design_files]
|
||||
foreach file $common_design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
common_design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 5]
|
||||
set files [list]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set files [concat $files [qsys_top::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files $files
|
||||
foreach file $design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set libraries [dict merge $libraries [qsys_top::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
foreach library $dpi_libraries { puts -nonewline "$library " }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
dpi_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
eval "$common_design_files"
|
||||
eval "$design_files"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
xmelab $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
if [ -n "$dpi_libraries" ]; then
|
||||
echo "Using DPI Library settings"
|
||||
FILES=""
|
||||
for library in $dpi_libraries; do
|
||||
FILES+="-sv_lib $library"
|
||||
done
|
||||
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME $FILES
|
||||
else
|
||||
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
fi
|
||||
Reference in New Issue
Block a user