Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
@@ -0,0 +1,168 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/rst_in/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../hps_subsys/hps_subsys/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/clk_100/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/qsys_top/user_rst_clkgate_0/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../peripheral_subsys/peripheral_subsys/sim/common/modelsim_files.tcl]
|
||||
|
||||
namespace eval qsys_top {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [clk_100::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_design_libraries]]
|
||||
dict set libraries altera_merlin_axi_translator_1987 1
|
||||
dict set libraries altera_merlin_slave_translator_191 1
|
||||
dict set libraries altera_merlin_axi_master_ni_19117 1
|
||||
dict set libraries altera_merlin_slave_agent_1930 1
|
||||
dict set libraries altera_avalon_sc_fifo_1932 1
|
||||
dict set libraries altera_merlin_router_1921 1
|
||||
dict set libraries altera_avalon_st_pipeline_stage_1930 1
|
||||
dict set libraries altera_merlin_burst_adapter_1940 1
|
||||
dict set libraries altera_merlin_demultiplexer_1921 1
|
||||
dict set libraries altera_merlin_multiplexer_1922 1
|
||||
dict set libraries altera_mm_interconnect_1920 1
|
||||
dict set libraries altera_irq_mapper_2001 1
|
||||
dict set libraries altera_reset_controller_1924 1
|
||||
dict set libraries qsys_top 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [hps_subsys::get_memory_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [clk_100::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [user_rst_clkgate_0::get_memory_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [peripheral_subsys::get_memory_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [rst_in::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set design_files [dict merge $design_files [hps_subsys::get_common_design_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set design_files [dict merge $design_files [clk_100::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set design_files [dict merge $design_files [user_rst_clkgate_0::get_common_design_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set design_files [dict merge $design_files [peripheral_subsys::get_common_design_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [rst_in::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [hps_subsys::get_design_files "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [clk_100::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [user_rst_clkgate_0::get_design_files "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [peripheral_subsys::get_design_files "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "-makelib altera_merlin_axi_translator_1987 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_slave_translator_191 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_axi_master_ni_19117 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_axi_master_ni_19117 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_slave_agent_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_slave_agent_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_avalon_sc_fifo_1932 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_router_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_router_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_avalon_st_pipeline_stage_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_avalon_st_pipeline_stage_1930 \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_burst_adapter_1940 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_demultiplexer_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_demultiplexer_1921 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_merlin_multiplexer_1922 \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_mm_interconnect_1920 \"[normalize_path "$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"]\" -end"
|
||||
lappend design_files "-makelib altera_irq_mapper_2001 \"[normalize_path "$QSYS_SIMDIR/../altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"]\" -end"
|
||||
lappend design_files "-makelib altera_reset_controller_1924 \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v"]\" -end"
|
||||
lappend design_files "-makelib altera_reset_controller_1924 \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v"]\" -end"
|
||||
lappend design_files "-makelib qsys_top \"[normalize_path "$QSYS_SIMDIR/qsys_top.v"]\" -end"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [hps_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [clk_100::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [user_rst_clkgate_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [peripheral_subsys::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [hps_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [clk_100::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [user_rst_clkgate_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [peripheral_subsys::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [hps_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [clk_100::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [user_rst_clkgate_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [peripheral_subsys::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc normalize_path {FILEPATH} {
|
||||
if {[catch { package require fileutil } err]} {
|
||||
return $FILEPATH
|
||||
}
|
||||
set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
|
||||
if {[file pathtype $FILEPATH] eq "relative"} {
|
||||
set path [fileutil::relative [pwd] $path]
|
||||
}
|
||||
return $path
|
||||
}
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/rst_in/sim/"]]
|
||||
set libraries [dict merge $libraries [hps_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../hps_subsys/hps_subsys/sim/"]]
|
||||
set libraries [dict merge $libraries [clk_100::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/clk_100/sim/"]]
|
||||
set libraries [dict merge $libraries [user_rst_clkgate_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/qsys_top/user_rst_clkgate_0/sim/"]]
|
||||
set libraries [dict merge $libraries [peripheral_subsys::get_dpi_libraries "$QSYS_SIMDIR/../../peripheral_subsys/peripheral_subsys/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user