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Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

Browse Source 
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-06-29 20:10:50 -04:00
commit ec82764bef
2462 changed files with 2174303 additions and 0 deletions
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qsys/qsys_top/qsys_top.csv
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# system info qsys_top on 2026.04.08.10:52:54
system_info:
name,value
DEVICE,A5EB013BB23BE4SCS
DEVICE_FAMILY,Agilex 5
GENERATION_ID,0
#
#
# Files generated for qsys_top on 2026.04.08.10:52:54
files:
filepath,kind,attributes,module,is_top
sim/qsys_top.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top,true
altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_mm_interconnect_1920_ykfyxdi,false
altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv,SYSTEM_VERILOG,,qsys_top_altera_irq_mapper_2001_lp4cnei,false
altera_reset_controller_1924/sim/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
altera_reset_controller_1924/sim/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
altera_reset_controller_1924/sim/altera_reset_controller.sdc,SDC_ENTITY,NO_SDC_PROMOTION,altera_reset_controller,false
altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_translator_1987_lty7xoq,false
altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_translator_191_xg7rzxi,false
altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v,VERILOG,,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi,false
altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_ox5xuhq,false
altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_sxavatq,false
altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q,false
altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_qyizksq,false
altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di,false
altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
qsys_top.clk_100,clk_100
qsys_top.rst_in,rst_in
qsys_top.user_rst_clkgate_0,user_rst_clkgate_0
qsys_top.subsys_hps,hps_subsys
qsys_top.subsys_periph,peripheral_subsys
qsys_top.mm_interconnect_0,qsys_top_altera_mm_interconnect_1920_ykfyxdi
qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator,qsys_top_altera_merlin_axi_translator_1987_lty7xoq
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_translator,qsys_top_altera_merlin_slave_translator_191_xg7rzxi
qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_agent,qsys_top_altera_merlin_axi_master_ni_19117_qautany
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent,qsys_top_altera_merlin_slave_agent_1930_jxauz3i
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rdata_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
qsys_top.mm_interconnect_0.router,qsys_top_altera_merlin_router_1921_ox5xuhq
qsys_top.mm_interconnect_0.router_001,qsys_top_altera_merlin_router_1921_ox5xuhq
qsys_top.mm_interconnect_0.router_002,qsys_top_altera_merlin_router_1921_sxavatq
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di
qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage.my_altera_avalon_st_pipeline_stage,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.cmd_demux,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
qsys_top.mm_interconnect_0.cmd_demux_001,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
qsys_top.mm_interconnect_0.cmd_mux,qsys_top_altera_merlin_multiplexer_1922_666s25q
qsys_top.mm_interconnect_0.rsp_demux,qsys_top_altera_merlin_demultiplexer_1921_qyizksq
qsys_top.mm_interconnect_0.rsp_mux,qsys_top_altera_merlin_multiplexer_1922_yjgptii
qsys_top.mm_interconnect_0.rsp_mux_001,qsys_top_altera_merlin_multiplexer_1922_yjgptii
qsys_top.mm_interconnect_0.agent_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.agent_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline_002,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.mm_interconnect_0.mux_pipeline_003,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
qsys_top.irq_mapper,qsys_top_altera_irq_mapper_2001_lp4cnei
qsys_top.rst_controller,altera_reset_controller
1 # system info qsys_top on 2026.04.08.10:52:54
2 system_info:
3 name,value
4 DEVICE,A5EB013BB23BE4SCS
5 DEVICE_FAMILY,Agilex 5
6 GENERATION_ID,0
7 #
8 #
9 # Files generated for qsys_top on 2026.04.08.10:52:54
10 files:
11 filepath,kind,attributes,module,is_top
12 sim/qsys_top.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top,true
13 altera_mm_interconnect_1920/sim/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_mm_interconnect_1920_ykfyxdi,false
14 altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv,SYSTEM_VERILOG,,qsys_top_altera_irq_mapper_2001_lp4cnei,false
15 altera_reset_controller_1924/sim/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
16 altera_reset_controller_1924/sim/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
17 altera_reset_controller_1924/sim/altera_reset_controller.sdc,SDC_ENTITY,NO_SDC_PROMOTION,altera_reset_controller,false
18 altera_merlin_axi_translator_1987/sim/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_translator_1987_lty7xoq,false
19 altera_merlin_slave_translator_191/sim/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_translator_191_xg7rzxi,false
20 altera_merlin_axi_master_ni_19117/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
21 altera_merlin_axi_master_ni_19117/sim/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_axi_master_ni_19117_qautany,false
22 altera_merlin_slave_agent_1930/sim/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
23 altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_slave_agent_1930_jxauz3i,false
24 altera_avalon_sc_fifo_1932/sim/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v,VERILOG,,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi,false
25 altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_ox5xuhq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_ox5xuhq,false
26 altera_merlin_router_1921/sim/qsys_top_altera_merlin_router_1921_sxavatq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_router_1921_sxavatq,false
27 altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
28 altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
29 altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
30 altera_merlin_burst_adapter_1940/sim/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
31 altera_merlin_burst_adapter_1940/sim/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
32 altera_merlin_burst_adapter_1940/sim/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
33 altera_merlin_burst_adapter_1940/sim/altera_default_burst_converter.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
34 altera_merlin_burst_adapter_1940/sim/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy,false
35 altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q,false
36 altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
37 altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_666s25q,false
38 altera_merlin_demultiplexer_1921/sim/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_demultiplexer_1921_qyizksq,false
39 altera_merlin_multiplexer_1922/sim/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
40 altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsys_top_altera_merlin_multiplexer_1922_yjgptii,false
41 altera_merlin_burst_adapter_1940/sim/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di,false
42 altera_avalon_st_pipeline_stage_1930/sim/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
43 altera_avalon_st_pipeline_stage_1930/sim/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq,false
44 #
45 # Map from instance-path to kind of module
46 instances:
47 instancePath,module
48 qsys_top.clk_100,clk_100
49 qsys_top.rst_in,rst_in
50 qsys_top.user_rst_clkgate_0,user_rst_clkgate_0
51 qsys_top.subsys_hps,hps_subsys
52 qsys_top.subsys_periph,peripheral_subsys
53 qsys_top.mm_interconnect_0,qsys_top_altera_mm_interconnect_1920_ykfyxdi
54 qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_translator,qsys_top_altera_merlin_axi_translator_1987_lty7xoq
55 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_translator,qsys_top_altera_merlin_slave_translator_191_xg7rzxi
56 qsys_top.mm_interconnect_0.subsys_hps_lwhps2fpga_agent,qsys_top_altera_merlin_axi_master_ni_19117_qautany
57 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent,qsys_top_altera_merlin_slave_agent_1930_jxauz3i
58 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rsp_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
59 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_agent_rdata_fifo,qsys_top_altera_avalon_sc_fifo_1932_22gxxgi
60 qsys_top.mm_interconnect_0.router,qsys_top_altera_merlin_router_1921_ox5xuhq
61 qsys_top.mm_interconnect_0.router_001,qsys_top_altera_merlin_router_1921_ox5xuhq
62 qsys_top.mm_interconnect_0.router_002,qsys_top_altera_merlin_router_1921_sxavatq
63 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter,qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy
64 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage,qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di
65 qsys_top.mm_interconnect_0.subsys_periph_pb_cpu_0_s0_burst_adapter.my_altera_avalon_st_pipeline_stage.my_altera_avalon_st_pipeline_stage,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
66 qsys_top.mm_interconnect_0.cmd_demux,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
67 qsys_top.mm_interconnect_0.cmd_demux_001,qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q
68 qsys_top.mm_interconnect_0.cmd_mux,qsys_top_altera_merlin_multiplexer_1922_666s25q
69 qsys_top.mm_interconnect_0.rsp_demux,qsys_top_altera_merlin_demultiplexer_1921_qyizksq
70 qsys_top.mm_interconnect_0.rsp_mux,qsys_top_altera_merlin_multiplexer_1922_yjgptii
71 qsys_top.mm_interconnect_0.rsp_mux_001,qsys_top_altera_merlin_multiplexer_1922_yjgptii
72 qsys_top.mm_interconnect_0.agent_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
73 qsys_top.mm_interconnect_0.agent_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
74 qsys_top.mm_interconnect_0.mux_pipeline,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
75 qsys_top.mm_interconnect_0.mux_pipeline_001,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
76 qsys_top.mm_interconnect_0.mux_pipeline_002,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
77 qsys_top.mm_interconnect_0.mux_pipeline_003,qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq
78 qsys_top.irq_mapper,qsys_top_altera_irq_mapper_2001_lp4cnei
79 qsys_top.rst_controller,altera_reset_controller