Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
+234
@@ -0,0 +1,234 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
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||||
// $Revision: #1 $
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||||
// $Date: 2026/02/05 $
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||||
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||||
// -------------------------------------------------------
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||||
// Merlin Router
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||||
//
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// Asserts the appropriate one-hot encoded channel based on
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||||
// the address.
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//
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// Also sets the binary-encoded destination id.
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||||
// -------------------------------------------------------
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||||
|
||||
`timescale 1 ns / 1 ns
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|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// decoder_type 0 (address decoder)
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// default_channel 0
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// default_destid 0
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// default_rd_channel -1
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// default_wr_channel -1
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// has_default_slave 0
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// memory_aliasing_decode 0
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// output_name qsys_top_altera_merlin_router_1921_ox5xuhq
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// pkt_addr_h 64
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// pkt_addr_l 36
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// pkt_dest_id_h 102
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// pkt_dest_id_l 102
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// pkt_protection_h 109
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// pkt_protection_l 107
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// pkt_trans_read 68
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// pkt_trans_write 67
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// slaves_info 0:1:0x0:0x20000:both:1:0:0:1
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// st_channel_w 2
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// st_data_w 171
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// ------------------------------------------
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module qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode
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#(
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parameter DEFAULT_CHANNEL = 0,
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DEFAULT_WR_CHANNEL = -1,
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DEFAULT_RD_CHANNEL = -1,
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DEFAULT_DESTID = 0
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)
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(output [102 - 102 : 0] default_destination_id,
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output [2-1 : 0] default_wr_channel,
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output [2-1 : 0] default_rd_channel,
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output [2-1 : 0] default_src_channel
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||||
);
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assign default_destination_id =
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DEFAULT_DESTID[102 - 102 : 0];
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generate
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if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
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assign default_src_channel = '0;
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end
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else begin : default_channel_assignment
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assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
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end
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endgenerate
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generate
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if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
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assign default_wr_channel = '0;
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assign default_rd_channel = '0;
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end
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||||
else begin : default_rw_channel_assignment
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assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
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assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
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end
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||||
endgenerate
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||||
endmodule
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module qsys_top_altera_merlin_router_1921_ox5xuhq
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||||
(
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||||
// -------------------
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||||
// Clock & Reset
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||||
// -------------------
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||||
input clk,
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||||
input reset,
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||||
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||||
// -------------------
|
||||
// Command Sink (Input)
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||||
// -------------------
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||||
input sink_valid,
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input [171-1 : 0] sink_data,
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||||
input sink_startofpacket,
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input sink_endofpacket,
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||||
output sink_ready,
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||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
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||||
output src_valid,
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||||
output reg [171-1 : 0] src_data,
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||||
output reg [2-1 : 0] src_channel,
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||||
output src_startofpacket,
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||||
output src_endofpacket,
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||||
input src_ready
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||||
);
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||||
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||||
// -------------------------------------------------------
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||||
// Local parameters and variables
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||||
// -------------------------------------------------------
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||||
localparam PKT_ADDR_H = 64;
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localparam PKT_ADDR_L = 36;
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localparam PKT_DEST_ID_H = 102;
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localparam PKT_DEST_ID_L = 102;
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localparam PKT_PROTECTION_H = 109;
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localparam PKT_PROTECTION_L = 107;
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localparam ST_DATA_W = 171;
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localparam ST_CHANNEL_W = 2;
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localparam DECODER_TYPE = 0;
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localparam PKT_TRANS_WRITE = 67;
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localparam PKT_TRANS_READ = 68;
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localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
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localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
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||||
|
||||
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||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h20000;
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||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
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||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
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||||
(RANGE_ADDR_WIDTH == 0) ?
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||||
PKT_ADDR_H :
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||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
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||||
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
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||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
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||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
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||||
assign src_endofpacket = sink_endofpacket;
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||||
wire [PKT_DEST_ID_W-1:0] default_destid;
|
||||
wire [2-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode the_default_decode(
|
||||
.default_destination_id (default_destid),
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||||
.default_wr_channel (),
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||||
.default_rd_channel (),
|
||||
.default_src_channel (default_src_channel)
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||||
);
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||||
|
||||
always @* begin
|
||||
src_data = sink_data;
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||||
src_channel = default_src_channel;
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||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
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||||
|
||||
// --------------------------------------------------
|
||||
// Address Decoder
|
||||
// Sets the channel and destination ID based on the address
|
||||
// --------------------------------------------------
|
||||
|
||||
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||||
// slave 0: [0x0, 0x20000)
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||||
src_channel = 2'b1;
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||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// It's the 21st century. Consider using $clog2().
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
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||||
reg [65:0] i;
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||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
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||||
|
||||
while (i < val) begin
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||||
log2ceil = log2ceil + 1;
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i = i << 1;
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||||
end
|
||||
end
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||||
endfunction
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||||
|
||||
endmodule
|
||||
|
||||
|
||||
+245
@@ -0,0 +1,245 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Merlin Router
|
||||
//
|
||||
// Asserts the appropriate one-hot encoded channel based on
|
||||
// the dest id.
|
||||
//
|
||||
// -------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// decoder_type 1 (dest id decoder)
|
||||
// default_channel -1
|
||||
// default_destid 0
|
||||
// default_rd_channel 1
|
||||
// default_wr_channel 0
|
||||
// has_default_slave 0
|
||||
// memory_aliasing_decode 0
|
||||
// output_name qsys_top_altera_merlin_router_1921_sxavatq
|
||||
// pkt_addr_h 64
|
||||
// pkt_addr_l 36
|
||||
// pkt_dest_id_h 102
|
||||
// pkt_dest_id_l 102
|
||||
// pkt_protection_h 109
|
||||
// pkt_protection_l 107
|
||||
// pkt_trans_read 68
|
||||
// pkt_trans_write 67
|
||||
// slaves_info 0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1
|
||||
// st_channel_w 2
|
||||
// st_data_w 171
|
||||
// ------------------------------------------
|
||||
|
||||
module qsys_top_altera_merlin_router_1921_sxavatq_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = -1,
|
||||
DEFAULT_WR_CHANNEL = 0,
|
||||
DEFAULT_RD_CHANNEL = 1,
|
||||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [102 - 102 : 0] default_destination_id,
|
||||
output [2-1 : 0] default_wr_channel,
|
||||
output [2-1 : 0] default_rd_channel,
|
||||
output [2-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
DEFAULT_DESTID[102 - 102 : 0];
|
||||
|
||||
generate
|
||||
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
|
||||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
|
||||
assign default_wr_channel = '0;
|
||||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module qsys_top_altera_merlin_router_1921_sxavatq
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command Sink (Input)
|
||||
// -------------------
|
||||
input sink_valid,
|
||||
input [171-1 : 0] sink_data,
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
|
||||
output src_valid,
|
||||
output reg [171-1 : 0] src_data,
|
||||
output reg [2-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Local parameters and variables
|
||||
// -------------------------------------------------------
|
||||
localparam PKT_ADDR_H = 64;
|
||||
localparam PKT_ADDR_L = 36;
|
||||
localparam PKT_DEST_ID_H = 102;
|
||||
localparam PKT_DEST_ID_L = 102;
|
||||
localparam PKT_PROTECTION_H = 109;
|
||||
localparam PKT_PROTECTION_L = 107;
|
||||
localparam ST_DATA_W = 171;
|
||||
localparam ST_CHANNEL_W = 2;
|
||||
localparam DECODER_TYPE = 1;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 67;
|
||||
localparam PKT_TRANS_READ = 68;
|
||||
|
||||
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
|
||||
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h0;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
PKT_ADDR_H :
|
||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
|
||||
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
|
||||
|
||||
reg [PKT_DEST_ID_W-1 : 0] destid;
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
|
||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [2-1 : 0] default_rd_channel;
|
||||
wire [2-1 : 0] default_wr_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Write and read transaction signals
|
||||
// -------------------------------------------------------
|
||||
wire write_transaction;
|
||||
assign write_transaction = sink_data[PKT_TRANS_WRITE];
|
||||
wire read_transaction;
|
||||
assign read_transaction = sink_data[PKT_TRANS_READ];
|
||||
|
||||
|
||||
qsys_top_altera_merlin_router_1921_sxavatq_default_decode the_default_decode(
|
||||
.default_destination_id (),
|
||||
.default_wr_channel (default_wr_channel),
|
||||
.default_rd_channel (default_rd_channel),
|
||||
.default_src_channel ()
|
||||
);
|
||||
|
||||
always @* begin
|
||||
src_data = sink_data;
|
||||
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
|
||||
|
||||
// --------------------------------------------------
|
||||
// DestinationID Decoder
|
||||
// Sets the channel based on the destination ID.
|
||||
// --------------------------------------------------
|
||||
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
|
||||
|
||||
|
||||
|
||||
if (destid == 0 && write_transaction) begin
|
||||
src_channel = 2'b01;
|
||||
end
|
||||
|
||||
if (destid == 0 && read_transaction) begin
|
||||
src_channel = 2'b10;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// It's the 21st century. Consider using $clog2().
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
|
||||
reg [65:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+234
@@ -0,0 +1,234 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Merlin Router
|
||||
//
|
||||
// Asserts the appropriate one-hot encoded channel based on
|
||||
// the address.
|
||||
//
|
||||
// Also sets the binary-encoded destination id.
|
||||
// -------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// decoder_type 0 (address decoder)
|
||||
// default_channel 0
|
||||
// default_destid 0
|
||||
// default_rd_channel -1
|
||||
// default_wr_channel -1
|
||||
// has_default_slave 0
|
||||
// memory_aliasing_decode 0
|
||||
// output_name qsys_top_altera_merlin_router_1921_ox5xuhq
|
||||
// pkt_addr_h 64
|
||||
// pkt_addr_l 36
|
||||
// pkt_dest_id_h 102
|
||||
// pkt_dest_id_l 102
|
||||
// pkt_protection_h 109
|
||||
// pkt_protection_l 107
|
||||
// pkt_trans_read 68
|
||||
// pkt_trans_write 67
|
||||
// slaves_info 0:1:0x0:0x20000:both:1:0:0:1
|
||||
// st_channel_w 2
|
||||
// st_data_w 171
|
||||
// ------------------------------------------
|
||||
|
||||
module qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = 0,
|
||||
DEFAULT_WR_CHANNEL = -1,
|
||||
DEFAULT_RD_CHANNEL = -1,
|
||||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [102 - 102 : 0] default_destination_id,
|
||||
output [2-1 : 0] default_wr_channel,
|
||||
output [2-1 : 0] default_rd_channel,
|
||||
output [2-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
DEFAULT_DESTID[102 - 102 : 0];
|
||||
|
||||
generate
|
||||
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
|
||||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
|
||||
assign default_wr_channel = '0;
|
||||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module qsys_top_altera_merlin_router_1921_ox5xuhq
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command Sink (Input)
|
||||
// -------------------
|
||||
input sink_valid,
|
||||
input [171-1 : 0] sink_data,
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
|
||||
output src_valid,
|
||||
output reg [171-1 : 0] src_data,
|
||||
output reg [2-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Local parameters and variables
|
||||
// -------------------------------------------------------
|
||||
localparam PKT_ADDR_H = 64;
|
||||
localparam PKT_ADDR_L = 36;
|
||||
localparam PKT_DEST_ID_H = 102;
|
||||
localparam PKT_DEST_ID_L = 102;
|
||||
localparam PKT_PROTECTION_H = 109;
|
||||
localparam PKT_PROTECTION_L = 107;
|
||||
localparam ST_DATA_W = 171;
|
||||
localparam ST_CHANNEL_W = 2;
|
||||
localparam DECODER_TYPE = 0;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 67;
|
||||
localparam PKT_TRANS_READ = 68;
|
||||
|
||||
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
|
||||
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h20000;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
PKT_ADDR_H :
|
||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
|
||||
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
|
||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [PKT_DEST_ID_W-1:0] default_destid;
|
||||
wire [2-1 : 0] default_src_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
qsys_top_altera_merlin_router_1921_ox5xuhq_default_decode the_default_decode(
|
||||
.default_destination_id (default_destid),
|
||||
.default_wr_channel (),
|
||||
.default_rd_channel (),
|
||||
.default_src_channel (default_src_channel)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
src_data = sink_data;
|
||||
src_channel = default_src_channel;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
|
||||
|
||||
// --------------------------------------------------
|
||||
// Address Decoder
|
||||
// Sets the channel and destination ID based on the address
|
||||
// --------------------------------------------------
|
||||
|
||||
|
||||
// slave 0: [0x0, 0x20000)
|
||||
src_channel = 2'b1;
|
||||
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// It's the 21st century. Consider using $clog2().
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
|
||||
reg [65:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+245
@@ -0,0 +1,245 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Merlin Router
|
||||
//
|
||||
// Asserts the appropriate one-hot encoded channel based on
|
||||
// the dest id.
|
||||
//
|
||||
// -------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// decoder_type 1 (dest id decoder)
|
||||
// default_channel -1
|
||||
// default_destid 0
|
||||
// default_rd_channel 1
|
||||
// default_wr_channel 0
|
||||
// has_default_slave 0
|
||||
// memory_aliasing_decode 0
|
||||
// output_name qsys_top_altera_merlin_router_1921_sxavatq
|
||||
// pkt_addr_h 64
|
||||
// pkt_addr_l 36
|
||||
// pkt_dest_id_h 102
|
||||
// pkt_dest_id_l 102
|
||||
// pkt_protection_h 109
|
||||
// pkt_protection_l 107
|
||||
// pkt_trans_read 68
|
||||
// pkt_trans_write 67
|
||||
// slaves_info 0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1
|
||||
// st_channel_w 2
|
||||
// st_data_w 171
|
||||
// ------------------------------------------
|
||||
|
||||
module qsys_top_altera_merlin_router_1921_sxavatq_default_decode
|
||||
#(
|
||||
parameter DEFAULT_CHANNEL = -1,
|
||||
DEFAULT_WR_CHANNEL = 0,
|
||||
DEFAULT_RD_CHANNEL = 1,
|
||||
DEFAULT_DESTID = 0
|
||||
)
|
||||
(output [102 - 102 : 0] default_destination_id,
|
||||
output [2-1 : 0] default_wr_channel,
|
||||
output [2-1 : 0] default_rd_channel,
|
||||
output [2-1 : 0] default_src_channel
|
||||
);
|
||||
|
||||
assign default_destination_id =
|
||||
DEFAULT_DESTID[102 - 102 : 0];
|
||||
|
||||
generate
|
||||
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
|
||||
assign default_src_channel = '0;
|
||||
end
|
||||
else begin : default_channel_assignment
|
||||
assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
|
||||
assign default_wr_channel = '0;
|
||||
assign default_rd_channel = '0;
|
||||
end
|
||||
else begin : default_rw_channel_assignment
|
||||
assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
|
||||
assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module qsys_top_altera_merlin_router_1921_sxavatq
|
||||
(
|
||||
// -------------------
|
||||
// Clock & Reset
|
||||
// -------------------
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
// -------------------
|
||||
// Command Sink (Input)
|
||||
// -------------------
|
||||
input sink_valid,
|
||||
input [171-1 : 0] sink_data,
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
output sink_ready,
|
||||
|
||||
// -------------------
|
||||
// Command Source (Output)
|
||||
// -------------------
|
||||
output src_valid,
|
||||
output reg [171-1 : 0] src_data,
|
||||
output reg [2-1 : 0] src_channel,
|
||||
output src_startofpacket,
|
||||
output src_endofpacket,
|
||||
input src_ready
|
||||
);
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Local parameters and variables
|
||||
// -------------------------------------------------------
|
||||
localparam PKT_ADDR_H = 64;
|
||||
localparam PKT_ADDR_L = 36;
|
||||
localparam PKT_DEST_ID_H = 102;
|
||||
localparam PKT_DEST_ID_L = 102;
|
||||
localparam PKT_PROTECTION_H = 109;
|
||||
localparam PKT_PROTECTION_L = 107;
|
||||
localparam ST_DATA_W = 171;
|
||||
localparam ST_CHANNEL_W = 2;
|
||||
localparam DECODER_TYPE = 1;
|
||||
|
||||
localparam PKT_TRANS_WRITE = 67;
|
||||
localparam PKT_TRANS_READ = 68;
|
||||
|
||||
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
|
||||
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Figure out the number of bits to mask off for each slave span
|
||||
// during address decoding
|
||||
// -------------------------------------------------------
|
||||
// -------------------------------------------------------
|
||||
// Work out which address bits are significant based on the
|
||||
// address range of the slaves. If the required width is too
|
||||
// large or too small, we use the address field width instead.
|
||||
// -------------------------------------------------------
|
||||
localparam ADDR_RANGE = 64'h0;
|
||||
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
|
||||
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
|
||||
(RANGE_ADDR_WIDTH == 0) ?
|
||||
PKT_ADDR_H :
|
||||
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
|
||||
|
||||
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
|
||||
|
||||
reg [PKT_DEST_ID_W-1 : 0] destid;
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Pass almost everything through, untouched
|
||||
// -------------------------------------------------------
|
||||
assign sink_ready = src_ready;
|
||||
assign src_valid = sink_valid;
|
||||
assign src_startofpacket = sink_startofpacket;
|
||||
assign src_endofpacket = sink_endofpacket;
|
||||
wire [2-1 : 0] default_rd_channel;
|
||||
wire [2-1 : 0] default_wr_channel;
|
||||
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------------
|
||||
// Write and read transaction signals
|
||||
// -------------------------------------------------------
|
||||
wire write_transaction;
|
||||
assign write_transaction = sink_data[PKT_TRANS_WRITE];
|
||||
wire read_transaction;
|
||||
assign read_transaction = sink_data[PKT_TRANS_READ];
|
||||
|
||||
|
||||
qsys_top_altera_merlin_router_1921_sxavatq_default_decode the_default_decode(
|
||||
.default_destination_id (),
|
||||
.default_wr_channel (default_wr_channel),
|
||||
.default_rd_channel (default_rd_channel),
|
||||
.default_src_channel ()
|
||||
);
|
||||
|
||||
always @* begin
|
||||
src_data = sink_data;
|
||||
src_channel = write_transaction ? default_wr_channel : default_rd_channel;
|
||||
|
||||
// --------------------------------------------------
|
||||
// DestinationID Decoder
|
||||
// Sets the channel based on the destination ID.
|
||||
// --------------------------------------------------
|
||||
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
|
||||
|
||||
|
||||
|
||||
if (destid == 0 && write_transaction) begin
|
||||
src_channel = 2'b01;
|
||||
end
|
||||
|
||||
if (destid == 0 && read_transaction) begin
|
||||
src_channel = 2'b10;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// --------------------------------------------------
|
||||
// Ceil(log2()) function
|
||||
// It's the 21st century. Consider using $clog2().
|
||||
// --------------------------------------------------
|
||||
function integer log2ceil;
|
||||
input reg[65:0] val;
|
||||
reg [65:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
Reference in New Issue
Block a user