Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

qsys/qsys_top/altera_irq_mapper_2001/sim/qsys_top_altera_irq_mapper_2001_lp4cnei.sv

@@ -0,0 +1,58 @@
+// (C) 2001-2026 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2026/02/05 $
+
+// -------------------------------------------------------
+// Altera IRQ Mapper
+//
+// Parameters
+//   NUM_RCVRS        : 2
+//   SENDER_IRW_WIDTH : 32
+//   IRQ_MAP          : 0:1,1:0
+//
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module qsys_top_altera_irq_mapper_2001_lp4cnei
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+    // -------------------
+    // IRQ Receivers
+    // -------------------
+    input                receiver0_irq,
+    input                receiver1_irq,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output reg [31 : 0] sender_irq
+);
+
+
+    always @* begin
+      sender_irq = 0;
+
+        sender_irq[1] = receiver0_irq;
+        sender_irq[0] = receiver1_irq;
+    end
+
+endmodule
+

qsys/qsys_top/altera_irq_mapper_2001/synth/qsys_top_altera_irq_mapper_2001_lp4cnei.sv

@@ -0,0 +1,58 @@
+// (C) 2001-2026 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2026/02/05 $
+
+// -------------------------------------------------------
+// Altera IRQ Mapper
+//
+// Parameters
+//   NUM_RCVRS        : 2
+//   SENDER_IRW_WIDTH : 32
+//   IRQ_MAP          : 0:1,1:0
+//
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module qsys_top_altera_irq_mapper_2001_lp4cnei
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+    // -------------------
+    // IRQ Receivers
+    // -------------------
+    input                receiver0_irq,
+    input                receiver1_irq,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output reg [31 : 0] sender_irq
+);
+
+
+    always @* begin
+      sender_irq = 0;
+
+        sender_irq[1] = receiver0_irq;
+        sender_irq[0] = receiver1_irq;
+    end
+
+endmodule
+