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Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

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RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-06-29 20:10:50 -04:00
commit ec82764bef
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qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v
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//Legal Notice: (C)2026 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
module button_pio_altera_avalon_pio_1924_qjofkqi (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_data_in <= 0;
else if (clk_en)
d1_data_in <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d2_data_in <= 0;
else if (clk_en)
d2_data_in <= d1_data_in;
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio.cmp
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component button_pio is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
irq : out std_logic -- irq
);
end component button_pio;
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio.html
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for button_pio</title>
<style type="text/css">
body { font-family:arial ;}
a { text-decoration:underline ; color:#003000 ;}
a:hover { text-decoration:underline ; color:0030f0 ;}
td { padding : 5px ;}
table.topTitle { width:100% ;}
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
table.blueBar { width : 100% ; border-spacing : 0px ;}
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
table.blueBar td.l { text-align : left ;}
table.blueBar td.r { text-align : right ;}
table.items { width:100% ; border-collapse:collapse ;}
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ; font-size:12px ;}
body { font-family:arial ;}
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
table.x td { border:1px solid #bbb ;}
td.tableTitle { font-weight:bold ; text-align:center ;}
table.grid { border-collapse:collapse ;}
table.grid td { border:1px solid #bbb ;}
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
.flowbox { display:inline-block ;}
.parametersbox table { font-size:10px ;}
td.parametername { font-style:italic ;}
td.parametervalue { font-weight:bold ;}
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
</head>
<body>
<table class="topTitle">
<tr>
<td class="l">button_pio</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2026.05.11.21:03:50</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/>All Components
<br/>&#160;&#160;
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
</a> altera_avalon_pio 19.2.4</span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
</a>
</td>
</tr>
<tr>
<td class="slaveb">s1&#160;</td>
</tr>
</table>
<a name="module_altera_avalon_pio_inst"> </a>
<div>
<hr/>
<h2>altera_avalon_pio_inst</h2>altera_avalon_pio v19.2.4
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">bitClearingEdgeCapReg</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">bitModifyingOutReg</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">captureEdge</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">direction</td>
<td class="parametervalue">Input</td>
</tr>
<tr>
<td class="parametername">edgeType</td>
<td class="parametervalue">FALLING</td>
</tr>
<tr>
<td class="parametername">generateIRQ</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">irqType</td>
<td class="parametervalue">EDGE</td>
</tr>
<tr>
<td class="parametername">resetValue</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">simDoTestBenchWiring</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">simDrivenValue</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">width</td>
<td class="parametervalue">4</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">CAPTURE</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">DATA_WIDTH</td>
<td class="parametervalue">4</td>
</tr>
<tr>
<td class="parametername">DO_TEST_BENCH_WIRING</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">DRIVEN_SIM_VALUE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">EDGE_TYPE</td>
<td class="parametervalue">FALLING</td>
</tr>
<tr>
<td class="parametername">FREQ</td>
<td class="parametervalue">100000000</td>
</tr>
<tr>
<td class="parametername">HAS_IN</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">HAS_OUT</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">HAS_TRI</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">IRQ_TYPE</td>
<td class="parametervalue">EDGE</td>
</tr>
<tr>
<td class="parametername">RESET_VALUE</td>
<td class="parametervalue">0</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.01 seconds</td>
</tr>
</table>
</body>
</html>
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio.qgsynthc
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<?xml version="1.0" ?>
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
<instanceKey xsi:type="xs:string">button_pio</instanceKey>
<instanceData xsi:type="data">
<parameters></parameters>
<interconnectAssignments></interconnectAssignments>
<className>button_pio</className>
<version>1.0</version>
<name>button_pio</name>
<uniqueName>button_pio</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
</instanceData>
<children>
<node>
<instanceKey xsi:type="xs:string">altera_avalon_pio_inst</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>DEVICE_FAMILY</name>
<value>Agilex 5</value>
</parameter>
<parameter>
<name>bitClearingEdgeCapReg</name>
<value>true</value>
</parameter>
<parameter>
<name>bitModifyingOutReg</name>
<value>false</value>
</parameter>
<parameter>
<name>captureEdge</name>
<value>true</value>
</parameter>
<parameter>
<name>clockRate</name>
<value>100000000</value>
</parameter>
<parameter>
<name>derived_capture</name>
<value>true</value>
</parameter>
<parameter>
<name>derived_do_test_bench_wiring</name>
<value>false</value>
</parameter>
<parameter>
<name>derived_edge_type</name>
<value>FALLING</value>
</parameter>
<parameter>
<name>derived_has_in</name>
<value>true</value>
</parameter>
<parameter>
<name>derived_has_irq</name>
<value>true</value>
</parameter>
<parameter>
<name>derived_has_out</name>
<value>false</value>
</parameter>
<parameter>
<name>derived_has_tri</name>
<value>false</value>
</parameter>
<parameter>
<name>derived_irq_type</name>
<value>EDGE</value>
</parameter>
<parameter>
<name>direction</name>
<value>Input</value>
</parameter>
<parameter>
<name>edgeType</name>
<value>FALLING</value>
</parameter>
<parameter>
<name>generateIRQ</name>
<value>true</value>
</parameter>
<parameter>
<name>irqType</name>
<value>EDGE</value>
</parameter>
<parameter>
<name>resetValue</name>
<value>0</value>
</parameter>
<parameter>
<name>simDoTestBenchWiring</name>
<value>false</value>
</parameter>
<parameter>
<name>simDrivenValue</name>
<value>0</value>
</parameter>
<parameter>
<name>width</name>
<value>4</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>altera_avalon_pio</className>
<version>19.2.4</version>
<name>altera_avalon_pio_inst</name>
<uniqueName>button_pio_altera_avalon_pio_1924_qjofkqi</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
<path>button_pio.altera_avalon_pio_inst</path>
</instanceData>
<children></children>
</node>
</children>
</node>
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio.qip
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set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_VERSION "26.1"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_avalon_pio"
set_global_assignment -entity "button_pio" -library "button_pio" -name PRE_COMPILED_MODULE "ON"
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_FILE [file join $::quartus(qip_path) "../button_pio.ip"]
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_TYPE "altera_avalon_pio"
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_VERSION "19.2.4"
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_HASH "qjofkqi"
set_global_assignment -library "button_pio" -name SOPCINFO_FILE [file join $::quartus(qip_path) "button_pio.sopcinfo"]
set_global_assignment -entity "button_pio" -library "button_pio" -name SLD_INFO "QSYS_NAME button_pio HAS_SOPCINFO 1 GENERATION_ID 0"
set_global_assignment -library "button_pio" -name MISC_FILE [file join $::quartus(qip_path) "button_pio.cmp"]
set_global_assignment -library "button_pio" -name SLD_FILE [file join $::quartus(qip_path) "button_pio.regmap"]
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "button_pio" -name MISC_FILE [file join $::quartus(qip_path) "../button_pio.ip"]
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_NAME "YnV0dG9uX3Bpb19hbHRlcmFfYXZhbG9uX3Bpb18xOTI0X3Fqb2ZrcWk="
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIElQ"
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_VERSION "MTkuMi40"
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvUGVyaXBoZXJhbHM="
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLmh0bWw="
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLXJldmlzaW9uLWhpc3RvcnkuaHRtbA=="
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_NAME "YnV0dG9uX3Bpbw=="
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -library "altera_avalon_pio_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v"]
set_global_assignment -library "button_pio" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/button_pio.v"]
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_NAME "altera_avalon_pio"
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_VERSION "19.2.4"
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_ENV "QsysPrimePro"
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio.regmap
+242
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@@ -0,0 +1,242 @@
<?xml version="1.0" encoding="UTF-8"?>
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
<name>button_pio</name>
<peripherals>
<peripheral>
<name>button_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>button_pio_altera_avalon_pio_inst_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>32</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DATA</name>
<displayName>Data</displayName>
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>data</name>
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DIRECTION</name>
<displayName>Direction</displayName>
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>direction</name>
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRQ_MASK</name>
<displayName>Interrupt mask</displayName>
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>interruptmask</name>
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>EDGE_CAP</name>
<displayName>Edge capture</displayName>
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>edgecapture</name>
<description>Edge detection for each input port.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SET_BIT</name>
<displayName>Outset</displayName>
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outset</name>
<description>Specifies which bit of the output port to set.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>CLEAR_BITS</name>
<displayName>Outclear</displayName>
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field><name>outclear</name>
<description>Specifies which output bit to clear.</description>
<bitOffset>0x0</bitOffset>
<bitWidth>32</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio.sopcinfo
+1196
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File diff suppressed because it is too large Load Diff
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio.xml
+238
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@@ -0,0 +1,238 @@
<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2026.05.11.21:03:51"
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="Agilex 5"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="A5ED065BB32AE6SR0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="6"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_BOARD"
type="String"
defaultValue="default"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_RATE"
type="Long"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_CLOCK_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_CLK_RESET_DOMAIN"
type="Integer"
defaultValue="-1"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_S1_CPU_INFO_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<interface name="clk" kind="clock" start="0">
<property name="clockRate" value="0" />
<property name="externallyDriven" value="false" />
<property name="ptfSchematicName" value="" />
<port name="clk" direction="input" role="clk" width="1" />
</interface>
<interface name="reset" kind="reset" start="0">
<property name="associatedClock" value="clk" />
<property name="synchronousEdges" value="DEASSERT" />
<port name="reset_n" direction="input" role="reset_n" width="1" />
</interface>
<interface name="s1" kind="avalon" start="0">
<property name="addressAlignment" value="NATIVE" />
<property name="addressGroup" value="0" />
<property name="addressSpan" value="4" />
<property name="addressUnits" value="WORDS" />
<property name="alwaysBurstMaxBurst" value="false" />
<property name="associatedClock" value="clk" />
<property name="associatedReset" value="reset" />
<property name="bitsPerSymbol" value="8" />
<property name="bridgedAddressOffset" value="0" />
<property name="bridgesToMaster" value="" />
<property name="burstOnBurstBoundariesOnly" value="false" />
<property name="burstcountUnits" value="WORDS" />
<property name="constantBurstBehavior" value="false" />
<property name="explicitAddressSpan" value="0" />
<property name="holdTime" value="0" />
<property name="interleaveBursts" value="false" />
<property name="isBigEndian" value="false" />
<property name="isFlash" value="false" />
<property name="isMemoryDevice" value="false" />
<property name="isNonVolatileStorage" value="false" />
<property name="linewrapBursts" value="false" />
<property name="maximumPendingReadTransactions" value="0" />
<property name="maximumPendingWriteTransactions" value="0" />
<property name="minimumReadLatency" value="1" />
<property name="minimumResponseLatency" value="1" />
<property name="minimumUninterruptedRunLength" value="1" />
<property name="prSafe" value="false" />
<property name="printableDevice" value="false" />
<property name="readLatency" value="0" />
<property name="readWaitStates" value="1" />
<property name="readWaitTime" value="1" />
<property name="registerIncomingSignals" value="false" />
<property name="registerOutgoingSignals" value="false" />
<property name="setupTime" value="0" />
<property name="timingUnits" value="Cycles" />
<property name="transparentBridge" value="false" />
<property name="waitrequestAllowance" value="0" />
<property name="waitrequestTimeout" value="1024" />
<property name="wellBehavedWaitrequest" value="false" />
<property name="writeLatency" value="0" />
<property name="writeWaitStates" value="0" />
<property name="writeWaitTime" value="0" />
<property name="dfhFeatureGuid" value="0" />
<property name="dfhGroupId" value="0" />
<property name="dfhParameterId" value="" />
<property name="dfhParameterName" value="" />
<property name="dfhParameterVersion" value="" />
<property name="dfhParameterData" value="" />
<property name="dfhParameterDataLength" value="" />
<property name="dfhFeatureMajorVersion" value="0" />
<property name="dfhFeatureMinorVersion" value="0" />
<property name="dfhFeatureId" value="35" />
<property name="dfhFeatureType" value="3" />
<port name="address" direction="input" role="address" width="2" />
<port name="write_n" direction="input" role="write_n" width="1" />
<port name="writedata" direction="input" role="writedata" width="32" />
<port name="chipselect" direction="input" role="chipselect" width="1" />
<port name="readdata" direction="output" role="readdata" width="32" />
</interface>
<interface name="external_connection" kind="conduit" start="0">
<property name="associatedClock" value="" />
<property name="associatedReset" value="" />
<property name="prSafe" value="false" />
<port name="in_port" direction="input" role="export" width="4" />
</interface>
<interface name="irq" kind="interrupt" start="0">
<property name="associatedAddressablePoint" value="button_pio.s1" />
<property name="associatedClock" value="clk" />
<property name="associatedReset" value="reset" />
<property name="bridgedReceiverOffset" value="0" />
<property name="bridgesToReceiver" value="" />
<property name="irqScheme" value="NONE" />
<port name="irq" direction="output" role="irq" width="1" />
</interface>
</perimeter>
<entity kind="button_pio" version="1.0" name="button_pio">
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
<parameter name="AUTO_BOARD" value="default" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_S1_CPU_INFO_ID" value="" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
<generatedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/synth/button_pio.v"
attributes="CONTAINS_INLINE_CONFIGURATION" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/synth/button_pio.v"
attributes="CONTAINS_INLINE_CONFIGURATION" />
</childGeneratedFiles>
<sourceFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio.ip" />
</sourceFiles>
<childSourceFiles>
<file
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
</childSourceFiles>
<messages>
<message level="Info" culprit="button_pio">"Generating: button_pio"</message>
<message level="Info" culprit="button_pio">"Generating: button_pio_altera_avalon_pio_1924_qjofkqi"</message>
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
</messages>
</entity>
<entity
kind="altera_avalon_pio"
version="19.2.4"
name="button_pio_altera_avalon_pio_1924_qjofkqi">
<parameter name="DEVICE_FAMILY" value="Agilex 5" />
<parameter name="derived_do_test_bench_wiring" value="false" />
<parameter name="generateIRQ" value="true" />
<parameter name="derived_has_irq" value="true" />
<parameter name="captureEdge" value="true" />
<parameter name="clockRate" value="100000000" />
<parameter name="derived_has_out" value="false" />
<parameter name="derived_has_in" value="true" />
<parameter name="resetValue" value="0" />
<parameter name="derived_has_tri" value="false" />
<parameter name="derived_capture" value="true" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="derived_edge_type" value="FALLING" />
<parameter name="irqType" value="EDGE" />
<parameter name="derived_irq_type" value="EDGE" />
<parameter name="edgeType" value="FALLING" />
<parameter name="width" value="4" />
<parameter name="bitClearingEdgeCapReg" value="true" />
<parameter name="direction" value="Input" />
<generatedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v"
attributes="" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v"
attributes="" />
</childGeneratedFiles>
<sourceFiles>
<file
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="button_pio" as="altera_avalon_pio_inst" />
<messages>
<message level="Info" culprit="button_pio">"Generating: button_pio_altera_avalon_pio_1924_qjofkqi"</message>
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]</message>
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
</messages>
</entity>
</deploy>
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio_bb.v
+13
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module button_pio (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata, // .readdata
input wire [3:0] in_port, // external_connection.export
output wire irq // irq.irq
);
endmodule
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio_generation.rpt
+14
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Info: Generated by version: 26.1 build 110
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: button_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: button_pio: "Transforming system: button_pio"
Info: button_pio: "Naming system components in system: button_pio"
Info: button_pio: "Processing generation queue"
Info: button_pio: "Generating: button_pio"
Info: button_pio: "Generating: button_pio_altera_avalon_pio_1924_qjofkqi"
Info: altera_avalon_pio_inst: Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
Info: altera_avalon_pio_inst: Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]
Info: altera_avalon_pio_inst: Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
Info: button_pio: Done "button_pio" with 2 modules, 2 files
Info: Finished: Create HDL design files for synthesis
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio_generation_previous.rpt
+14
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@@ -0,0 +1,14 @@
Info: Generated by version: 25.3.1 build 100
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: button_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: button_pio: "Transforming system: button_pio"
Info: button_pio: "Naming system components in system: button_pio"
Info: button_pio: "Processing generation queue"
Info: button_pio: "Generating: button_pio"
Info: button_pio: "Generating: button_pio_altera_avalon_pio_1924_qjofkqi"
Info: altera_avalon_pio_inst: Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
Info: altera_avalon_pio_inst: Generation command is [exec /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/bin/perl -I /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/europa -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/perl_lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio -- /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_1616509418156170056.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/home/ubuntu/altera_pro/25.3.1/quartus --verilog --config=/tmp/alt0585_1616509418156170056.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]
Info: altera_avalon_pio_inst: Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
Info: button_pio: Done "button_pio" with 2 modules, 2 files
Info: Finished: Create HDL design files for synthesis
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio_inst.v
+12
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button_pio u0 (
.clk (_connected_to_clk_), // input, width = 1, clk.clk
.reset_n (_connected_to_reset_n_), // input, width = 1, reset.reset_n
.address (_connected_to_address_), // input, width = 2, s1.address
.write_n (_connected_to_write_n_), // input, width = 1, .write_n
.writedata (_connected_to_writedata_), // input, width = 32, .writedata
.chipselect (_connected_to_chipselect_), // input, width = 1, .chipselect
.readdata (_connected_to_readdata_), // output, width = 32, .readdata
.in_port (_connected_to_in_port_), // input, width = 4, external_connection.export
.irq (_connected_to_irq_) // output, width = 1, irq.irq
);
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/button_pio_inst.vhd
+27
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component button_pio is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
irq : out std_logic -- irq
);
end component button_pio;
u0 : component button_pio
port map (
clk => CONNECTED_TO_clk, -- clk.clk
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
address => CONNECTED_TO_address, -- s1.address
write_n => CONNECTED_TO_write_n, -- .write_n
writedata => CONNECTED_TO_writedata, -- .writedata
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata, -- .readdata
in_port => CONNECTED_TO_in_port, -- external_connection.export
irq => CONNECTED_TO_irq -- irq.irq
);
qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/synth/button_pio.v
+30
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// button_pio.v
// Generated using ACDS version 26.1 110
`timescale 1 ps / 1 ps
module button_pio (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata, // .readdata
input wire [3:0] in_port, // external_connection.export
output wire irq // irq.irq
);
button_pio_altera_avalon_pio_1924_qjofkqi altera_avalon_pio_inst (
.clk (clk), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.address (address), // input, width = 2, s1.address
.write_n (write_n), // input, width = 1, .write_n
.writedata (writedata), // input, width = 32, .writedata
.chipselect (chipselect), // input, width = 1, .chipselect
.readdata (readdata), // output, width = 32, .readdata
.in_port (in_port), // input, width = 4, external_connection.export
.irq (irq) // output, width = 1, irq.irq
);
endmodule