Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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//Legal Notice: (C)2026 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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||||
//including, without limitation, that your use is for the sole purpose
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||||
//of programming logic devices manufactured by Altera and sold by Altera
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||||
//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
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module button_pio_altera_avalon_pio_1924_qjofkqi (
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// inputs:
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address,
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chipselect,
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clk,
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in_port,
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reset_n,
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write_n,
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writedata,
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// outputs:
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irq,
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readdata
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)
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;
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output irq;
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output [ 31: 0] readdata;
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input [ 1: 0] address;
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input chipselect;
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input clk;
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input [ 3: 0] in_port;
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input reset_n;
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input write_n;
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input [ 31: 0] writedata;
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wire clk_en;
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reg [ 3: 0] d1_data_in;
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reg [ 3: 0] d2_data_in;
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wire [ 3: 0] data_in;
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reg [ 3: 0] edge_capture;
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wire edge_capture_wr_strobe;
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wire [ 3: 0] edge_detect;
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wire irq;
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reg [ 3: 0] irq_mask;
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wire [ 3: 0] read_mux_out;
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reg [ 31: 0] readdata;
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assign clk_en = 1;
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//s1, which is an e_avalon_slave
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assign read_mux_out = ({4 {(address == 0)}} & data_in) |
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({4 {(address == 2)}} & irq_mask) |
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({4 {(address == 3)}} & edge_capture);
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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readdata <= 0;
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else if (clk_en)
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readdata <= {32'b0 | read_mux_out};
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end
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assign data_in = in_port;
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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irq_mask <= 0;
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else if (chipselect && ~write_n && (address == 2))
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irq_mask <= writedata[3 : 0];
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end
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assign irq = |(edge_capture & irq_mask);
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assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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edge_capture[0] <= 0;
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else if (clk_en)
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if (edge_capture_wr_strobe && writedata[0])
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edge_capture[0] <= 0;
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else if (edge_detect[0])
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edge_capture[0] <= -1;
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end
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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edge_capture[1] <= 0;
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else if (clk_en)
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if (edge_capture_wr_strobe && writedata[1])
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edge_capture[1] <= 0;
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else if (edge_detect[1])
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edge_capture[1] <= -1;
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end
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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edge_capture[2] <= 0;
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else if (clk_en)
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if (edge_capture_wr_strobe && writedata[2])
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edge_capture[2] <= 0;
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else if (edge_detect[2])
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edge_capture[2] <= -1;
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end
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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edge_capture[3] <= 0;
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else if (clk_en)
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if (edge_capture_wr_strobe && writedata[3])
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edge_capture[3] <= 0;
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else if (edge_detect[3])
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edge_capture[3] <= -1;
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end
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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d1_data_in <= 0;
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else if (clk_en)
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d1_data_in <= data_in;
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end
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always @(posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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d2_data_in <= 0;
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else if (clk_en)
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d2_data_in <= d1_data_in;
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end
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assign edge_detect = ~d1_data_in & d2_data_in;
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endmodule
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@@ -0,0 +1,14 @@
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component button_pio is
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port (
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clk : in std_logic := 'X'; -- clk
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reset_n : in std_logic := 'X'; -- reset_n
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address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
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write_n : in std_logic := 'X'; -- write_n
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writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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chipselect : in std_logic := 'X'; -- chipselect
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readdata : out std_logic_vector(31 downto 0); -- readdata
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in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
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irq : out std_logic -- irq
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);
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end component button_pio;
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@@ -0,0 +1,244 @@
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<html xmlns="http://www.w3.org/1999/xhtml">
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<head>
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||||
<title>datasheet for button_pio</title>
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<style type="text/css">
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||||
body { font-family:arial ;}
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||||
a { text-decoration:underline ; color:#003000 ;}
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||||
a:hover { text-decoration:underline ; color:0030f0 ;}
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td { padding : 5px ;}
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table.topTitle { width:100% ;}
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table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
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||||
table.blueBar td.l { text-align : left ;}
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||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
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||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
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||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
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||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
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||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
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||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
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||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
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||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
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||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
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||||
.flowbox { display:inline-block ;}
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||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
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||||
td.parametervalue { font-weight:bold ;}
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||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
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||||
</head>
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||||
<body>
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||||
<table class="topTitle">
|
||||
<tr>
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||||
<td class="l">button_pio</td>
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||||
<td class="r">
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||||
<br/>
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||||
<br/>
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||||
</td>
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||||
</tr>
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||||
</table>
|
||||
<table class="blueBar">
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||||
<tr>
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||||
<td class="l">2026.05.11.21:03:50</td>
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||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
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||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
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||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/>All Components
|
||||
<br/>  
|
||||
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
|
||||
</a> altera_avalon_pio 19.2.4</span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
|
||||
</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s1 </td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_avalon_pio_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_avalon_pio_inst</h2>altera_avalon_pio v19.2.4
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">bitClearingEdgeCapReg</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">bitModifyingOutReg</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">captureEdge</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">direction</td>
|
||||
<td class="parametervalue">Input</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">edgeType</td>
|
||||
<td class="parametervalue">FALLING</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateIRQ</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">irqType</td>
|
||||
<td class="parametervalue">EDGE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">resetValue</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">simDoTestBenchWiring</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">simDrivenValue</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">width</td>
|
||||
<td class="parametervalue">4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CAPTURE</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DATA_WIDTH</td>
|
||||
<td class="parametervalue">4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DO_TEST_BENCH_WIRING</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DRIVEN_SIM_VALUE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EDGE_TYPE</td>
|
||||
<td class="parametervalue">FALLING</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">FREQ</td>
|
||||
<td class="parametervalue">100000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_IN</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_OUT</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_TRI</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">IRQ_TYPE</td>
|
||||
<td class="parametervalue">EDGE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">RESET_VALUE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,116 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">button_pio</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>button_pio</className>
|
||||
<version>1.0</version>
|
||||
<name>button_pio</name>
|
||||
<uniqueName>button_pio</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_avalon_pio_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>DEVICE_FAMILY</name>
|
||||
<value>Agilex 5</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>bitClearingEdgeCapReg</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>bitModifyingOutReg</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>captureEdge</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>clockRate</name>
|
||||
<value>100000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_capture</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_do_test_bench_wiring</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_edge_type</name>
|
||||
<value>FALLING</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_in</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_irq</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_out</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_tri</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_irq_type</name>
|
||||
<value>EDGE</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>direction</name>
|
||||
<value>Input</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>edgeType</name>
|
||||
<value>FALLING</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>generateIRQ</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>irqType</name>
|
||||
<value>EDGE</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>resetValue</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>simDoTestBenchWiring</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>simDrivenValue</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>width</name>
|
||||
<value>4</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_avalon_pio</className>
|
||||
<version>19.2.4</version>
|
||||
<name>altera_avalon_pio_inst</name>
|
||||
<uniqueName>button_pio_altera_avalon_pio_1924_qjofkqi</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>button_pio.altera_avalon_pio_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,45 @@
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_FILE [file join $::quartus(qip_path) "../button_pio.ip"]
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_TYPE "altera_avalon_pio"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_VERSION "19.2.4"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name OCS_IP_HASH "qjofkqi"
|
||||
set_global_assignment -library "button_pio" -name SOPCINFO_FILE [file join $::quartus(qip_path) "button_pio.sopcinfo"]
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name SLD_INFO "QSYS_NAME button_pio HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "button_pio" -name MISC_FILE [file join $::quartus(qip_path) "button_pio.cmp"]
|
||||
set_global_assignment -library "button_pio" -name SLD_FILE [file join $::quartus(qip_path) "button_pio.regmap"]
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "button_pio" -name MISC_FILE [file join $::quartus(qip_path) "../button_pio.ip"]
|
||||
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_NAME "YnV0dG9uX3Bpb19hbHRlcmFfYXZhbG9uX3Bpb18xOTI0X3Fqb2ZrcWk="
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIElQ"
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_VERSION "MTkuMi40"
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvUGVyaXBoZXJhbHM="
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLmh0bWw="
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLXJldmlzaW9uLWhpc3RvcnkuaHRtbA=="
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_NAME "YnV0dG9uX3Bpbw=="
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "button_pio" -library "button_pio" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "altera_avalon_pio_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v"]
|
||||
set_global_assignment -library "button_pio" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/button_pio.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_VERSION "19.2.4"
|
||||
set_global_assignment -entity "button_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
@@ -0,0 +1,242 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
|
||||
<name>button_pio</name>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>button_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>button_pio_altera_avalon_pio_inst_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
</peripherals>
|
||||
</device>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,238 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:51"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5ED065BB32AE6SR0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_S1_CPU_INFO_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="reset" kind="reset" start="0">
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="synchronousEdges" value="DEASSERT" />
|
||||
<port name="reset_n" direction="input" role="reset_n" width="1" />
|
||||
</interface>
|
||||
<interface name="s1" kind="avalon" start="0">
|
||||
<property name="addressAlignment" value="NATIVE" />
|
||||
<property name="addressGroup" value="0" />
|
||||
<property name="addressSpan" value="4" />
|
||||
<property name="addressUnits" value="WORDS" />
|
||||
<property name="alwaysBurstMaxBurst" value="false" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bitsPerSymbol" value="8" />
|
||||
<property name="bridgedAddressOffset" value="0" />
|
||||
<property name="bridgesToMaster" value="" />
|
||||
<property name="burstOnBurstBoundariesOnly" value="false" />
|
||||
<property name="burstcountUnits" value="WORDS" />
|
||||
<property name="constantBurstBehavior" value="false" />
|
||||
<property name="explicitAddressSpan" value="0" />
|
||||
<property name="holdTime" value="0" />
|
||||
<property name="interleaveBursts" value="false" />
|
||||
<property name="isBigEndian" value="false" />
|
||||
<property name="isFlash" value="false" />
|
||||
<property name="isMemoryDevice" value="false" />
|
||||
<property name="isNonVolatileStorage" value="false" />
|
||||
<property name="linewrapBursts" value="false" />
|
||||
<property name="maximumPendingReadTransactions" value="0" />
|
||||
<property name="maximumPendingWriteTransactions" value="0" />
|
||||
<property name="minimumReadLatency" value="1" />
|
||||
<property name="minimumResponseLatency" value="1" />
|
||||
<property name="minimumUninterruptedRunLength" value="1" />
|
||||
<property name="prSafe" value="false" />
|
||||
<property name="printableDevice" value="false" />
|
||||
<property name="readLatency" value="0" />
|
||||
<property name="readWaitStates" value="1" />
|
||||
<property name="readWaitTime" value="1" />
|
||||
<property name="registerIncomingSignals" value="false" />
|
||||
<property name="registerOutgoingSignals" value="false" />
|
||||
<property name="setupTime" value="0" />
|
||||
<property name="timingUnits" value="Cycles" />
|
||||
<property name="transparentBridge" value="false" />
|
||||
<property name="waitrequestAllowance" value="0" />
|
||||
<property name="waitrequestTimeout" value="1024" />
|
||||
<property name="wellBehavedWaitrequest" value="false" />
|
||||
<property name="writeLatency" value="0" />
|
||||
<property name="writeWaitStates" value="0" />
|
||||
<property name="writeWaitTime" value="0" />
|
||||
<property name="dfhFeatureGuid" value="0" />
|
||||
<property name="dfhGroupId" value="0" />
|
||||
<property name="dfhParameterId" value="" />
|
||||
<property name="dfhParameterName" value="" />
|
||||
<property name="dfhParameterVersion" value="" />
|
||||
<property name="dfhParameterData" value="" />
|
||||
<property name="dfhParameterDataLength" value="" />
|
||||
<property name="dfhFeatureMajorVersion" value="0" />
|
||||
<property name="dfhFeatureMinorVersion" value="0" />
|
||||
<property name="dfhFeatureId" value="35" />
|
||||
<property name="dfhFeatureType" value="3" />
|
||||
<port name="address" direction="input" role="address" width="2" />
|
||||
<port name="write_n" direction="input" role="write_n" width="1" />
|
||||
<port name="writedata" direction="input" role="writedata" width="32" />
|
||||
<port name="chipselect" direction="input" role="chipselect" width="1" />
|
||||
<port name="readdata" direction="output" role="readdata" width="32" />
|
||||
</interface>
|
||||
<interface name="external_connection" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<property name="prSafe" value="false" />
|
||||
<port name="in_port" direction="input" role="export" width="4" />
|
||||
</interface>
|
||||
<interface name="irq" kind="interrupt" start="0">
|
||||
<property name="associatedAddressablePoint" value="button_pio.s1" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bridgedReceiverOffset" value="0" />
|
||||
<property name="bridgesToReceiver" value="" />
|
||||
<property name="irqScheme" value="NONE" />
|
||||
<port name="irq" direction="output" role="irq" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="button_pio" version="1.0" name="button_pio">
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_S1_CPU_INFO_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/synth/button_pio.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/synth/button_pio.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Info" culprit="button_pio">"Generating: button_pio"</message>
|
||||
<message level="Info" culprit="button_pio">"Generating: button_pio_altera_avalon_pio_1924_qjofkqi"</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
kind="altera_avalon_pio"
|
||||
version="19.2.4"
|
||||
name="button_pio_altera_avalon_pio_1924_qjofkqi">
|
||||
<parameter name="DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="derived_do_test_bench_wiring" value="false" />
|
||||
<parameter name="generateIRQ" value="true" />
|
||||
<parameter name="derived_has_irq" value="true" />
|
||||
<parameter name="captureEdge" value="true" />
|
||||
<parameter name="clockRate" value="100000000" />
|
||||
<parameter name="derived_has_out" value="false" />
|
||||
<parameter name="derived_has_in" value="true" />
|
||||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="derived_has_tri" value="false" />
|
||||
<parameter name="derived_capture" value="true" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="derived_edge_type" value="FALLING" />
|
||||
<parameter name="irqType" value="EDGE" />
|
||||
<parameter name="derived_irq_type" value="EDGE" />
|
||||
<parameter name="edgeType" value="FALLING" />
|
||||
<parameter name="width" value="4" />
|
||||
<parameter name="bitClearingEdgeCapReg" value="true" />
|
||||
<parameter name="direction" value="Input" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v"
|
||||
attributes="" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v"
|
||||
attributes="" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="button_pio" as="altera_avalon_pio_inst" />
|
||||
<messages>
|
||||
<message level="Info" culprit="button_pio">"Generating: button_pio_altera_avalon_pio_1924_qjofkqi"</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,13 @@
|
||||
module button_pio (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
input wire [1:0] address, // s1.address
|
||||
input wire write_n, // .write_n
|
||||
input wire [31:0] writedata, // .writedata
|
||||
input wire chipselect, // .chipselect
|
||||
output wire [31:0] readdata, // .readdata
|
||||
input wire [3:0] in_port, // external_connection.export
|
||||
output wire irq // irq.irq
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: button_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: button_pio: "Transforming system: button_pio"
|
||||
Info: button_pio: "Naming system components in system: button_pio"
|
||||
Info: button_pio: "Processing generation queue"
|
||||
Info: button_pio: "Generating: button_pio"
|
||||
Info: button_pio: "Generating: button_pio_altera_avalon_pio_1924_qjofkqi"
|
||||
Info: altera_avalon_pio_inst: Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: altera_avalon_pio_inst: Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: altera_avalon_pio_inst: Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: button_pio: Done "button_pio" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/button_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: button_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: button_pio: "Transforming system: button_pio"
|
||||
Info: button_pio: "Naming system components in system: button_pio"
|
||||
Info: button_pio: "Processing generation queue"
|
||||
Info: button_pio: "Generating: button_pio"
|
||||
Info: button_pio: "Generating: button_pio_altera_avalon_pio_1924_qjofkqi"
|
||||
Info: altera_avalon_pio_inst: Starting RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: altera_avalon_pio_inst: Generation command is [exec /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/bin/perl -I /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/europa -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/perl_lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio -- /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=button_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_1616509418156170056.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/home/ubuntu/altera_pro/25.3.1/quartus --verilog --config=/tmp/alt0585_1616509418156170056.dir/0002_altera_avalon_pio_inst_gen//button_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: altera_avalon_pio_inst: Done RTL generation for module 'button_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: button_pio: Done "button_pio" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,12 @@
|
||||
button_pio u0 (
|
||||
.clk (_connected_to_clk_), // input, width = 1, clk.clk
|
||||
.reset_n (_connected_to_reset_n_), // input, width = 1, reset.reset_n
|
||||
.address (_connected_to_address_), // input, width = 2, s1.address
|
||||
.write_n (_connected_to_write_n_), // input, width = 1, .write_n
|
||||
.writedata (_connected_to_writedata_), // input, width = 32, .writedata
|
||||
.chipselect (_connected_to_chipselect_), // input, width = 1, .chipselect
|
||||
.readdata (_connected_to_readdata_), // output, width = 32, .readdata
|
||||
.in_port (_connected_to_in_port_), // input, width = 4, external_connection.export
|
||||
.irq (_connected_to_irq_) // output, width = 1, irq.irq
|
||||
);
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
component button_pio is
|
||||
port (
|
||||
clk : in std_logic := 'X'; -- clk
|
||||
reset_n : in std_logic := 'X'; -- reset_n
|
||||
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
|
||||
write_n : in std_logic := 'X'; -- write_n
|
||||
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||||
chipselect : in std_logic := 'X'; -- chipselect
|
||||
readdata : out std_logic_vector(31 downto 0); -- readdata
|
||||
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
|
||||
irq : out std_logic -- irq
|
||||
);
|
||||
end component button_pio;
|
||||
|
||||
u0 : component button_pio
|
||||
port map (
|
||||
clk => CONNECTED_TO_clk, -- clk.clk
|
||||
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
|
||||
address => CONNECTED_TO_address, -- s1.address
|
||||
write_n => CONNECTED_TO_write_n, -- .write_n
|
||||
writedata => CONNECTED_TO_writedata, -- .writedata
|
||||
chipselect => CONNECTED_TO_chipselect, -- .chipselect
|
||||
readdata => CONNECTED_TO_readdata, -- .readdata
|
||||
in_port => CONNECTED_TO_in_port, -- external_connection.export
|
||||
irq => CONNECTED_TO_irq -- irq.irq
|
||||
);
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
// button_pio.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module button_pio (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
input wire [1:0] address, // s1.address
|
||||
input wire write_n, // .write_n
|
||||
input wire [31:0] writedata, // .writedata
|
||||
input wire chipselect, // .chipselect
|
||||
output wire [31:0] readdata, // .readdata
|
||||
input wire [3:0] in_port, // external_connection.export
|
||||
output wire irq // irq.irq
|
||||
);
|
||||
|
||||
button_pio_altera_avalon_pio_1924_qjofkqi altera_avalon_pio_inst (
|
||||
.clk (clk), // input, width = 1, clk.clk
|
||||
.reset_n (reset_n), // input, width = 1, reset.reset_n
|
||||
.address (address), // input, width = 2, s1.address
|
||||
.write_n (write_n), // input, width = 1, .write_n
|
||||
.writedata (writedata), // input, width = 32, .writedata
|
||||
.chipselect (chipselect), // input, width = 1, .chipselect
|
||||
.readdata (readdata), // output, width = 32, .readdata
|
||||
.in_port (in_port), // input, width = 4, external_connection.export
|
||||
.irq (irq) // output, width = 1, irq.irq
|
||||
);
|
||||
|
||||
endmodule
|
||||
+1547
File diff suppressed because it is too large
Load Diff
+155
@@ -0,0 +1,155 @@
|
||||
//Legal Notice: (C)2026 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
//simulation files), and any associated documentation or information are
|
||||
//expressly subject to the terms and conditions of the Altera Program
|
||||
//License Subscription Agreement or other applicable license agreement,
|
||||
//including, without limitation, that your use is for the sole purpose
|
||||
//of programming logic devices manufactured by Altera and sold by Altera
|
||||
//or its authorized distributors. Please refer to the applicable
|
||||
//agreement for further details.
|
||||
|
||||
// synthesis translate_off
|
||||
`timescale 1ns / 1ps
|
||||
// synthesis translate_on
|
||||
|
||||
// turn off superfluous verilog processor warnings
|
||||
// altera message_level Level1
|
||||
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
|
||||
|
||||
module dipsw_pio_altera_avalon_pio_1924_qjofkqi (
|
||||
// inputs:
|
||||
address,
|
||||
chipselect,
|
||||
clk,
|
||||
in_port,
|
||||
reset_n,
|
||||
write_n,
|
||||
writedata,
|
||||
|
||||
// outputs:
|
||||
irq,
|
||||
readdata
|
||||
)
|
||||
;
|
||||
|
||||
output irq;
|
||||
output [ 31: 0] readdata;
|
||||
input [ 1: 0] address;
|
||||
input chipselect;
|
||||
input clk;
|
||||
input [ 3: 0] in_port;
|
||||
input reset_n;
|
||||
input write_n;
|
||||
input [ 31: 0] writedata;
|
||||
|
||||
|
||||
wire clk_en;
|
||||
reg [ 3: 0] d1_data_in;
|
||||
reg [ 3: 0] d2_data_in;
|
||||
wire [ 3: 0] data_in;
|
||||
reg [ 3: 0] edge_capture;
|
||||
wire edge_capture_wr_strobe;
|
||||
wire [ 3: 0] edge_detect;
|
||||
wire irq;
|
||||
reg [ 3: 0] irq_mask;
|
||||
wire [ 3: 0] read_mux_out;
|
||||
reg [ 31: 0] readdata;
|
||||
assign clk_en = 1;
|
||||
//s1, which is an e_avalon_slave
|
||||
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
|
||||
({4 {(address == 2)}} & irq_mask) |
|
||||
({4 {(address == 3)}} & edge_capture);
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
readdata <= 0;
|
||||
else if (clk_en)
|
||||
readdata <= {32'b0 | read_mux_out};
|
||||
end
|
||||
|
||||
|
||||
assign data_in = in_port;
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
irq_mask <= 0;
|
||||
else if (chipselect && ~write_n && (address == 2))
|
||||
irq_mask <= writedata[3 : 0];
|
||||
end
|
||||
|
||||
|
||||
assign irq = |(edge_capture & irq_mask);
|
||||
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
edge_capture[0] <= 0;
|
||||
else if (clk_en)
|
||||
if (edge_capture_wr_strobe && writedata[0])
|
||||
edge_capture[0] <= 0;
|
||||
else if (edge_detect[0])
|
||||
edge_capture[0] <= -1;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
edge_capture[1] <= 0;
|
||||
else if (clk_en)
|
||||
if (edge_capture_wr_strobe && writedata[1])
|
||||
edge_capture[1] <= 0;
|
||||
else if (edge_detect[1])
|
||||
edge_capture[1] <= -1;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
edge_capture[2] <= 0;
|
||||
else if (clk_en)
|
||||
if (edge_capture_wr_strobe && writedata[2])
|
||||
edge_capture[2] <= 0;
|
||||
else if (edge_detect[2])
|
||||
edge_capture[2] <= -1;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
edge_capture[3] <= 0;
|
||||
else if (clk_en)
|
||||
if (edge_capture_wr_strobe && writedata[3])
|
||||
edge_capture[3] <= 0;
|
||||
else if (edge_detect[3])
|
||||
edge_capture[3] <= -1;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
d1_data_in <= 0;
|
||||
else if (clk_en)
|
||||
d1_data_in <= data_in;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
d2_data_in <= 0;
|
||||
else if (clk_en)
|
||||
d2_data_in <= d1_data_in;
|
||||
end
|
||||
|
||||
|
||||
assign edge_detect = ~d1_data_in & d2_data_in;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
component dipsw_pio is
|
||||
port (
|
||||
clk : in std_logic := 'X'; -- clk
|
||||
reset_n : in std_logic := 'X'; -- reset_n
|
||||
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
|
||||
write_n : in std_logic := 'X'; -- write_n
|
||||
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||||
chipselect : in std_logic := 'X'; -- chipselect
|
||||
readdata : out std_logic_vector(31 downto 0); -- readdata
|
||||
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
|
||||
irq : out std_logic -- irq
|
||||
);
|
||||
end component dipsw_pio;
|
||||
|
||||
@@ -0,0 +1,244 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for dipsw_pio</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">dipsw_pio</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:51</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/>All Components
|
||||
<br/>  
|
||||
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
|
||||
</a> altera_avalon_pio 19.2.4</span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
|
||||
</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s1 </td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_avalon_pio_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_avalon_pio_inst</h2>altera_avalon_pio v19.2.4
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">bitClearingEdgeCapReg</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">bitModifyingOutReg</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">captureEdge</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">direction</td>
|
||||
<td class="parametervalue">Input</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">edgeType</td>
|
||||
<td class="parametervalue">FALLING</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateIRQ</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">irqType</td>
|
||||
<td class="parametervalue">EDGE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">resetValue</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">simDoTestBenchWiring</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">simDrivenValue</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">width</td>
|
||||
<td class="parametervalue">4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CAPTURE</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DATA_WIDTH</td>
|
||||
<td class="parametervalue">4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DO_TEST_BENCH_WIRING</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DRIVEN_SIM_VALUE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EDGE_TYPE</td>
|
||||
<td class="parametervalue">FALLING</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">FREQ</td>
|
||||
<td class="parametervalue">100000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_IN</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_OUT</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_TRI</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">IRQ_TYPE</td>
|
||||
<td class="parametervalue">EDGE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">RESET_VALUE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,116 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">dipsw_pio</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>dipsw_pio</className>
|
||||
<version>1.0</version>
|
||||
<name>dipsw_pio</name>
|
||||
<uniqueName>dipsw_pio</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_avalon_pio_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>DEVICE_FAMILY</name>
|
||||
<value>Agilex 5</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>bitClearingEdgeCapReg</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>bitModifyingOutReg</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>captureEdge</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>clockRate</name>
|
||||
<value>100000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_capture</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_do_test_bench_wiring</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_edge_type</name>
|
||||
<value>FALLING</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_in</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_irq</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_out</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_tri</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_irq_type</name>
|
||||
<value>EDGE</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>direction</name>
|
||||
<value>Input</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>edgeType</name>
|
||||
<value>FALLING</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>generateIRQ</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>irqType</name>
|
||||
<value>EDGE</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>resetValue</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>simDoTestBenchWiring</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>simDrivenValue</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>width</name>
|
||||
<value>4</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_avalon_pio</className>
|
||||
<version>19.2.4</version>
|
||||
<name>altera_avalon_pio_inst</name>
|
||||
<uniqueName>dipsw_pio_altera_avalon_pio_1924_qjofkqi</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>dipsw_pio.altera_avalon_pio_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,45 @@
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name OCS_IP_FILE [file join $::quartus(qip_path) "../dipsw_pio.ip"]
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name OCS_IP_TYPE "altera_avalon_pio"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name OCS_IP_VERSION "19.2.4"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name OCS_IP_HASH "qjofkqi"
|
||||
set_global_assignment -library "dipsw_pio" -name SOPCINFO_FILE [file join $::quartus(qip_path) "dipsw_pio.sopcinfo"]
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name SLD_INFO "QSYS_NAME dipsw_pio HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "dipsw_pio" -name MISC_FILE [file join $::quartus(qip_path) "dipsw_pio.cmp"]
|
||||
set_global_assignment -library "dipsw_pio" -name SLD_FILE [file join $::quartus(qip_path) "dipsw_pio.regmap"]
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "dipsw_pio" -name MISC_FILE [file join $::quartus(qip_path) "../dipsw_pio.ip"]
|
||||
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_NAME "ZGlwc3dfcGlvX2FsdGVyYV9hdmFsb25fcGlvXzE5MjRfcWpvZmtxaQ=="
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIElQ"
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_VERSION "MTkuMi40"
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvUGVyaXBoZXJhbHM="
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLmh0bWw="
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLXJldmlzaW9uLWhpc3RvcnkuaHRtbA=="
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_COMPONENT_NAME "ZGlwc3dfcGlv"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "dipsw_pio" -library "dipsw_pio" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "altera_avalon_pio_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v"]
|
||||
set_global_assignment -library "dipsw_pio" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/dipsw_pio.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_VERSION "19.2.4"
|
||||
set_global_assignment -entity "dipsw_pio_altera_avalon_pio_1924_qjofkqi" -library "altera_avalon_pio_1924" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
@@ -0,0 +1,242 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
|
||||
<name>dipsw_pio</name>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>dipsw_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>dipsw_pio_altera_avalon_pio_inst_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
</peripherals>
|
||||
</device>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,238 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:51"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5ED065BB32AE6SR0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_S1_CPU_INFO_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="reset" kind="reset" start="0">
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="synchronousEdges" value="DEASSERT" />
|
||||
<port name="reset_n" direction="input" role="reset_n" width="1" />
|
||||
</interface>
|
||||
<interface name="s1" kind="avalon" start="0">
|
||||
<property name="addressAlignment" value="NATIVE" />
|
||||
<property name="addressGroup" value="0" />
|
||||
<property name="addressSpan" value="4" />
|
||||
<property name="addressUnits" value="WORDS" />
|
||||
<property name="alwaysBurstMaxBurst" value="false" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bitsPerSymbol" value="8" />
|
||||
<property name="bridgedAddressOffset" value="0" />
|
||||
<property name="bridgesToMaster" value="" />
|
||||
<property name="burstOnBurstBoundariesOnly" value="false" />
|
||||
<property name="burstcountUnits" value="WORDS" />
|
||||
<property name="constantBurstBehavior" value="false" />
|
||||
<property name="explicitAddressSpan" value="0" />
|
||||
<property name="holdTime" value="0" />
|
||||
<property name="interleaveBursts" value="false" />
|
||||
<property name="isBigEndian" value="false" />
|
||||
<property name="isFlash" value="false" />
|
||||
<property name="isMemoryDevice" value="false" />
|
||||
<property name="isNonVolatileStorage" value="false" />
|
||||
<property name="linewrapBursts" value="false" />
|
||||
<property name="maximumPendingReadTransactions" value="0" />
|
||||
<property name="maximumPendingWriteTransactions" value="0" />
|
||||
<property name="minimumReadLatency" value="1" />
|
||||
<property name="minimumResponseLatency" value="1" />
|
||||
<property name="minimumUninterruptedRunLength" value="1" />
|
||||
<property name="prSafe" value="false" />
|
||||
<property name="printableDevice" value="false" />
|
||||
<property name="readLatency" value="0" />
|
||||
<property name="readWaitStates" value="1" />
|
||||
<property name="readWaitTime" value="1" />
|
||||
<property name="registerIncomingSignals" value="false" />
|
||||
<property name="registerOutgoingSignals" value="false" />
|
||||
<property name="setupTime" value="0" />
|
||||
<property name="timingUnits" value="Cycles" />
|
||||
<property name="transparentBridge" value="false" />
|
||||
<property name="waitrequestAllowance" value="0" />
|
||||
<property name="waitrequestTimeout" value="1024" />
|
||||
<property name="wellBehavedWaitrequest" value="false" />
|
||||
<property name="writeLatency" value="0" />
|
||||
<property name="writeWaitStates" value="0" />
|
||||
<property name="writeWaitTime" value="0" />
|
||||
<property name="dfhFeatureGuid" value="0" />
|
||||
<property name="dfhGroupId" value="0" />
|
||||
<property name="dfhParameterId" value="" />
|
||||
<property name="dfhParameterName" value="" />
|
||||
<property name="dfhParameterVersion" value="" />
|
||||
<property name="dfhParameterData" value="" />
|
||||
<property name="dfhParameterDataLength" value="" />
|
||||
<property name="dfhFeatureMajorVersion" value="0" />
|
||||
<property name="dfhFeatureMinorVersion" value="0" />
|
||||
<property name="dfhFeatureId" value="35" />
|
||||
<property name="dfhFeatureType" value="3" />
|
||||
<port name="address" direction="input" role="address" width="2" />
|
||||
<port name="write_n" direction="input" role="write_n" width="1" />
|
||||
<port name="writedata" direction="input" role="writedata" width="32" />
|
||||
<port name="chipselect" direction="input" role="chipselect" width="1" />
|
||||
<port name="readdata" direction="output" role="readdata" width="32" />
|
||||
</interface>
|
||||
<interface name="external_connection" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<property name="prSafe" value="false" />
|
||||
<port name="in_port" direction="input" role="export" width="4" />
|
||||
</interface>
|
||||
<interface name="irq" kind="interrupt" start="0">
|
||||
<property name="associatedAddressablePoint" value="dipsw_pio.s1" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bridgedReceiverOffset" value="0" />
|
||||
<property name="bridgesToReceiver" value="" />
|
||||
<property name="irqScheme" value="NONE" />
|
||||
<port name="irq" direction="output" role="irq" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="dipsw_pio" version="1.0" name="dipsw_pio">
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_S1_CPU_INFO_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/synth/dipsw_pio.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/synth/dipsw_pio.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Info" culprit="dipsw_pio">"Generating: dipsw_pio"</message>
|
||||
<message level="Info" culprit="dipsw_pio">"Generating: dipsw_pio_altera_avalon_pio_1924_qjofkqi"</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=dipsw_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_420007878313678203.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_420007878313678203.dir/0002_altera_avalon_pio_inst_gen//dipsw_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
kind="altera_avalon_pio"
|
||||
version="19.2.4"
|
||||
name="dipsw_pio_altera_avalon_pio_1924_qjofkqi">
|
||||
<parameter name="DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="derived_do_test_bench_wiring" value="false" />
|
||||
<parameter name="generateIRQ" value="true" />
|
||||
<parameter name="derived_has_irq" value="true" />
|
||||
<parameter name="captureEdge" value="true" />
|
||||
<parameter name="clockRate" value="100000000" />
|
||||
<parameter name="derived_has_out" value="false" />
|
||||
<parameter name="derived_has_in" value="true" />
|
||||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="derived_has_tri" value="false" />
|
||||
<parameter name="derived_capture" value="true" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="derived_edge_type" value="FALLING" />
|
||||
<parameter name="irqType" value="EDGE" />
|
||||
<parameter name="derived_irq_type" value="EDGE" />
|
||||
<parameter name="edgeType" value="FALLING" />
|
||||
<parameter name="width" value="4" />
|
||||
<parameter name="bitClearingEdgeCapReg" value="true" />
|
||||
<parameter name="direction" value="Input" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v"
|
||||
attributes="" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v"
|
||||
attributes="" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="dipsw_pio" as="altera_avalon_pio_inst" />
|
||||
<messages>
|
||||
<message level="Info" culprit="dipsw_pio">"Generating: dipsw_pio_altera_avalon_pio_1924_qjofkqi"</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=dipsw_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_420007878313678203.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_420007878313678203.dir/0002_altera_avalon_pio_inst_gen//dipsw_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,13 @@
|
||||
module dipsw_pio (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
input wire [1:0] address, // s1.address
|
||||
input wire write_n, // .write_n
|
||||
input wire [31:0] writedata, // .writedata
|
||||
input wire chipselect, // .chipselect
|
||||
output wire [31:0] readdata, // .readdata
|
||||
input wire [3:0] in_port, // external_connection.export
|
||||
output wire irq // irq.irq
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: dipsw_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: dipsw_pio: "Transforming system: dipsw_pio"
|
||||
Info: dipsw_pio: "Naming system components in system: dipsw_pio"
|
||||
Info: dipsw_pio: "Processing generation queue"
|
||||
Info: dipsw_pio: "Generating: dipsw_pio"
|
||||
Info: dipsw_pio: "Generating: dipsw_pio_altera_avalon_pio_1924_qjofkqi"
|
||||
Info: altera_avalon_pio_inst: Starting RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: altera_avalon_pio_inst: Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=dipsw_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_420007878313678203.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_420007878313678203.dir/0002_altera_avalon_pio_inst_gen//dipsw_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: altera_avalon_pio_inst: Done RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: dipsw_pio: Done "dipsw_pio" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: dipsw_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: dipsw_pio: "Transforming system: dipsw_pio"
|
||||
Info: dipsw_pio: "Naming system components in system: dipsw_pio"
|
||||
Info: dipsw_pio: "Processing generation queue"
|
||||
Info: dipsw_pio: "Generating: dipsw_pio"
|
||||
Info: dipsw_pio: "Generating: dipsw_pio_altera_avalon_pio_1924_qjofkqi"
|
||||
Info: altera_avalon_pio_inst: Starting RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: altera_avalon_pio_inst: Generation command is [exec /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/bin/perl -I /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/europa -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/perl_lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio -- /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=dipsw_pio_altera_avalon_pio_1924_qjofkqi --dir=/tmp/alt0585_16739321146044125982.dir/0002_altera_avalon_pio_inst_gen/ --quartus_dir=/home/ubuntu/altera_pro/25.3.1/quartus --verilog --config=/tmp/alt0585_16739321146044125982.dir/0002_altera_avalon_pio_inst_gen//dipsw_pio_altera_avalon_pio_1924_qjofkqi_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: altera_avalon_pio_inst: Done RTL generation for module 'dipsw_pio_altera_avalon_pio_1924_qjofkqi'
|
||||
Info: dipsw_pio: Done "dipsw_pio" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,12 @@
|
||||
dipsw_pio u0 (
|
||||
.clk (_connected_to_clk_), // input, width = 1, clk.clk
|
||||
.reset_n (_connected_to_reset_n_), // input, width = 1, reset.reset_n
|
||||
.address (_connected_to_address_), // input, width = 2, s1.address
|
||||
.write_n (_connected_to_write_n_), // input, width = 1, .write_n
|
||||
.writedata (_connected_to_writedata_), // input, width = 32, .writedata
|
||||
.chipselect (_connected_to_chipselect_), // input, width = 1, .chipselect
|
||||
.readdata (_connected_to_readdata_), // output, width = 32, .readdata
|
||||
.in_port (_connected_to_in_port_), // input, width = 4, external_connection.export
|
||||
.irq (_connected_to_irq_) // output, width = 1, irq.irq
|
||||
);
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
component dipsw_pio is
|
||||
port (
|
||||
clk : in std_logic := 'X'; -- clk
|
||||
reset_n : in std_logic := 'X'; -- reset_n
|
||||
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
|
||||
write_n : in std_logic := 'X'; -- write_n
|
||||
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||||
chipselect : in std_logic := 'X'; -- chipselect
|
||||
readdata : out std_logic_vector(31 downto 0); -- readdata
|
||||
in_port : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
|
||||
irq : out std_logic -- irq
|
||||
);
|
||||
end component dipsw_pio;
|
||||
|
||||
u0 : component dipsw_pio
|
||||
port map (
|
||||
clk => CONNECTED_TO_clk, -- clk.clk
|
||||
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
|
||||
address => CONNECTED_TO_address, -- s1.address
|
||||
write_n => CONNECTED_TO_write_n, -- .write_n
|
||||
writedata => CONNECTED_TO_writedata, -- .writedata
|
||||
chipselect => CONNECTED_TO_chipselect, -- .chipselect
|
||||
readdata => CONNECTED_TO_readdata, -- .readdata
|
||||
in_port => CONNECTED_TO_in_port, -- external_connection.export
|
||||
irq => CONNECTED_TO_irq -- irq.irq
|
||||
);
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
// dipsw_pio.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module dipsw_pio (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
input wire [1:0] address, // s1.address
|
||||
input wire write_n, // .write_n
|
||||
input wire [31:0] writedata, // .writedata
|
||||
input wire chipselect, // .chipselect
|
||||
output wire [31:0] readdata, // .readdata
|
||||
input wire [3:0] in_port, // external_connection.export
|
||||
output wire irq // irq.irq
|
||||
);
|
||||
|
||||
dipsw_pio_altera_avalon_pio_1924_qjofkqi altera_avalon_pio_inst (
|
||||
.clk (clk), // input, width = 1, clk.clk
|
||||
.reset_n (reset_n), // input, width = 1, reset.reset_n
|
||||
.address (address), // input, width = 2, s1.address
|
||||
.write_n (write_n), // input, width = 1, .write_n
|
||||
.writedata (writedata), // input, width = 32, .writedata
|
||||
.chipselect (chipselect), // input, width = 1, .chipselect
|
||||
.readdata (readdata), // output, width = 32, .readdata
|
||||
.in_port (in_port), // input, width = 4, external_connection.export
|
||||
.irq (irq) // output, width = 1, irq.irq
|
||||
);
|
||||
|
||||
endmodule
|
||||
+1439
File diff suppressed because it is too large
Load Diff
+79
@@ -0,0 +1,79 @@
|
||||
//Legal Notice: (C)2026 Altera Corporation. All rights reserved. Your
|
||||
//use of Altera Corporation's design tools, logic functions and other
|
||||
//software and tools, and its AMPP partner logic functions, and any
|
||||
//output files any of the foregoing (including device programming or
|
||||
//simulation files), and any associated documentation or information are
|
||||
//expressly subject to the terms and conditions of the Altera Program
|
||||
//License Subscription Agreement or other applicable license agreement,
|
||||
//including, without limitation, that your use is for the sole purpose
|
||||
//of programming logic devices manufactured by Altera and sold by Altera
|
||||
//or its authorized distributors. Please refer to the applicable
|
||||
//agreement for further details.
|
||||
|
||||
// synthesis translate_off
|
||||
`timescale 1ns / 1ps
|
||||
// synthesis translate_on
|
||||
|
||||
// turn off superfluous verilog processor warnings
|
||||
// altera message_level Level1
|
||||
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
|
||||
|
||||
module led_pio_altera_avalon_pio_1924_yrkgeby (
|
||||
// inputs:
|
||||
address,
|
||||
chipselect,
|
||||
clk,
|
||||
in_port,
|
||||
reset_n,
|
||||
write_n,
|
||||
writedata,
|
||||
|
||||
// outputs:
|
||||
out_port,
|
||||
readdata
|
||||
)
|
||||
;
|
||||
|
||||
output [ 2: 0] out_port;
|
||||
output [ 31: 0] readdata;
|
||||
input [ 1: 0] address;
|
||||
input chipselect;
|
||||
input clk;
|
||||
input [ 2: 0] in_port;
|
||||
input reset_n;
|
||||
input write_n;
|
||||
input [ 31: 0] writedata;
|
||||
|
||||
|
||||
wire clk_en;
|
||||
wire [ 2: 0] data_in;
|
||||
reg [ 2: 0] data_out;
|
||||
wire [ 2: 0] out_port;
|
||||
wire [ 2: 0] read_mux_out;
|
||||
reg [ 31: 0] readdata;
|
||||
assign clk_en = 1;
|
||||
//s1, which is an e_avalon_slave
|
||||
assign read_mux_out = {3 {(address == 0)}} & data_in;
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
readdata <= 0;
|
||||
else if (clk_en)
|
||||
readdata <= {32'b0 | read_mux_out};
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (reset_n == 0)
|
||||
data_out <= 7;
|
||||
else if (chipselect && ~write_n && (address == 0))
|
||||
data_out <= writedata[2 : 0];
|
||||
end
|
||||
|
||||
|
||||
assign out_port = data_out;
|
||||
assign data_in = in_port;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
component led_pio is
|
||||
port (
|
||||
clk : in std_logic := 'X'; -- clk
|
||||
reset_n : in std_logic := 'X'; -- reset_n
|
||||
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
|
||||
write_n : in std_logic := 'X'; -- write_n
|
||||
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||||
chipselect : in std_logic := 'X'; -- chipselect
|
||||
readdata : out std_logic_vector(31 downto 0); -- readdata
|
||||
in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port
|
||||
out_port : out std_logic_vector(2 downto 0) -- out_port
|
||||
);
|
||||
end component led_pio;
|
||||
|
||||
@@ -0,0 +1,244 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for led_pio</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">led_pio</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:51</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/>All Components
|
||||
<br/>  
|
||||
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
|
||||
</a> altera_avalon_pio 19.2.4</span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_altera_avalon_pio_inst"><b>altera_avalon_pio_inst</b>
|
||||
</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s1 </td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_avalon_pio_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_avalon_pio_inst</h2>altera_avalon_pio v19.2.4
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">bitClearingEdgeCapReg</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">bitModifyingOutReg</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">captureEdge</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">direction</td>
|
||||
<td class="parametervalue">InOut</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">edgeType</td>
|
||||
<td class="parametervalue">RISING</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateIRQ</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">irqType</td>
|
||||
<td class="parametervalue">LEVEL</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">resetValue</td>
|
||||
<td class="parametervalue">7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">simDoTestBenchWiring</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">simDrivenValue</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">width</td>
|
||||
<td class="parametervalue">3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CAPTURE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DATA_WIDTH</td>
|
||||
<td class="parametervalue">3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DO_TEST_BENCH_WIRING</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">DRIVEN_SIM_VALUE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EDGE_TYPE</td>
|
||||
<td class="parametervalue">NONE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">FREQ</td>
|
||||
<td class="parametervalue">100000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_IN</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_OUT</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">HAS_TRI</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">IRQ_TYPE</td>
|
||||
<td class="parametervalue">NONE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">RESET_VALUE</td>
|
||||
<td class="parametervalue">7</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,116 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">led_pio</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>led_pio</className>
|
||||
<version>1.0</version>
|
||||
<name>led_pio</name>
|
||||
<uniqueName>led_pio</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_avalon_pio_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>DEVICE_FAMILY</name>
|
||||
<value>Agilex 5</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>bitClearingEdgeCapReg</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>bitModifyingOutReg</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>captureEdge</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>clockRate</name>
|
||||
<value>100000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_capture</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_do_test_bench_wiring</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_edge_type</name>
|
||||
<value>NONE</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_in</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_irq</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_out</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_has_tri</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>derived_irq_type</name>
|
||||
<value>NONE</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>direction</name>
|
||||
<value>InOut</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>edgeType</name>
|
||||
<value>RISING</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>generateIRQ</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>irqType</name>
|
||||
<value>LEVEL</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>resetValue</name>
|
||||
<value>7</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>simDoTestBenchWiring</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>simDrivenValue</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>width</name>
|
||||
<value>3</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_avalon_pio</className>
|
||||
<version>19.2.4</version>
|
||||
<name>altera_avalon_pio_inst</name>
|
||||
<uniqueName>led_pio_altera_avalon_pio_1924_yrkgeby</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>led_pio.altera_avalon_pio_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,45 @@
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name OCS_IP_FILE [file join $::quartus(qip_path) "../led_pio.ip"]
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name OCS_IP_TYPE "altera_avalon_pio"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name OCS_IP_VERSION "19.2.4"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name OCS_IP_HASH "yrkgeby"
|
||||
set_global_assignment -library "led_pio" -name SOPCINFO_FILE [file join $::quartus(qip_path) "led_pio.sopcinfo"]
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name SLD_INFO "QSYS_NAME led_pio HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "led_pio" -name MISC_FILE [file join $::quartus(qip_path) "led_pio.cmp"]
|
||||
set_global_assignment -library "led_pio" -name SLD_FILE [file join $::quartus(qip_path) "led_pio.regmap"]
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "led_pio" -name MISC_FILE [file join $::quartus(qip_path) "../led_pio.ip"]
|
||||
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_NAME "bGVkX3Bpb19hbHRlcmFfYXZhbG9uX3Bpb18xOTI0X3lya2dlYnk="
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08pIElQ"
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_VERSION "MTkuMi40"
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvUGVyaXBoZXJhbHM="
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLmh0bWw="
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3Bpby1jb3JlLXJldmlzaW9uLWhpc3RvcnkuaHRtbA=="
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_COMPONENT_NAME "bGVkX3Bpbw=="
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "led_pio" -library "led_pio" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "altera_avalon_pio_1924" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_pio_1924/synth/led_pio_altera_avalon_pio_1924_yrkgeby.v"]
|
||||
set_global_assignment -library "led_pio" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/led_pio.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_TOOL_NAME "altera_avalon_pio"
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_TOOL_VERSION "19.2.4"
|
||||
set_global_assignment -entity "led_pio_altera_avalon_pio_1924_yrkgeby" -library "altera_avalon_pio_1924" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
@@ -0,0 +1,242 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
|
||||
<name>led_pio</name>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>led_pio_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>led_pio_altera_avalon_pio_inst_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>32</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>DATA</name>
|
||||
<displayName>Data</displayName>
|
||||
<description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>data</name>
|
||||
<description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>DIRECTION</name>
|
||||
<displayName>Direction</displayName>
|
||||
<description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>direction</name>
|
||||
<description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>IRQ_MASK</name>
|
||||
<displayName>Interrupt mask</displayName>
|
||||
<description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
|
||||
<addressOffset>0x8</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>interruptmask</name>
|
||||
<description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>EDGE_CAP</name>
|
||||
<displayName>Edge capture</displayName>
|
||||
<description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
|
||||
<addressOffset>0xc</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-write</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>edgecapture</name>
|
||||
<description>Edge detection for each input port.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-write</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>SET_BIT</name>
|
||||
<displayName>Outset</displayName>
|
||||
<description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x10</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outset</name>
|
||||
<description>Specifies which bit of the output port to set.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>CLEAR_BITS</name>
|
||||
<displayName>Outclear</displayName>
|
||||
<description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
|
||||
<addressOffset>0x14</addressOffset>
|
||||
<size>32</size>
|
||||
<access>write-only</access>
|
||||
<resetValue>0x0</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>outclear</name>
|
||||
<description>Specifies which output bit to clear.</description>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>write-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
</peripherals>
|
||||
</device>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,230 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:51"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5ED065BB32AE6SR0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_S1_CPU_INFO_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="reset" kind="reset" start="0">
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="synchronousEdges" value="DEASSERT" />
|
||||
<port name="reset_n" direction="input" role="reset_n" width="1" />
|
||||
</interface>
|
||||
<interface name="s1" kind="avalon" start="0">
|
||||
<property name="addressAlignment" value="NATIVE" />
|
||||
<property name="addressGroup" value="0" />
|
||||
<property name="addressSpan" value="4" />
|
||||
<property name="addressUnits" value="WORDS" />
|
||||
<property name="alwaysBurstMaxBurst" value="false" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bitsPerSymbol" value="8" />
|
||||
<property name="bridgedAddressOffset" value="0" />
|
||||
<property name="bridgesToMaster" value="" />
|
||||
<property name="burstOnBurstBoundariesOnly" value="false" />
|
||||
<property name="burstcountUnits" value="WORDS" />
|
||||
<property name="constantBurstBehavior" value="false" />
|
||||
<property name="explicitAddressSpan" value="0" />
|
||||
<property name="holdTime" value="0" />
|
||||
<property name="interleaveBursts" value="false" />
|
||||
<property name="isBigEndian" value="false" />
|
||||
<property name="isFlash" value="false" />
|
||||
<property name="isMemoryDevice" value="false" />
|
||||
<property name="isNonVolatileStorage" value="false" />
|
||||
<property name="linewrapBursts" value="false" />
|
||||
<property name="maximumPendingReadTransactions" value="0" />
|
||||
<property name="maximumPendingWriteTransactions" value="0" />
|
||||
<property name="minimumReadLatency" value="1" />
|
||||
<property name="minimumResponseLatency" value="1" />
|
||||
<property name="minimumUninterruptedRunLength" value="1" />
|
||||
<property name="prSafe" value="false" />
|
||||
<property name="printableDevice" value="false" />
|
||||
<property name="readLatency" value="0" />
|
||||
<property name="readWaitStates" value="1" />
|
||||
<property name="readWaitTime" value="1" />
|
||||
<property name="registerIncomingSignals" value="false" />
|
||||
<property name="registerOutgoingSignals" value="false" />
|
||||
<property name="setupTime" value="0" />
|
||||
<property name="timingUnits" value="Cycles" />
|
||||
<property name="transparentBridge" value="false" />
|
||||
<property name="waitrequestAllowance" value="0" />
|
||||
<property name="waitrequestTimeout" value="1024" />
|
||||
<property name="wellBehavedWaitrequest" value="false" />
|
||||
<property name="writeLatency" value="0" />
|
||||
<property name="writeWaitStates" value="0" />
|
||||
<property name="writeWaitTime" value="0" />
|
||||
<property name="dfhFeatureGuid" value="0" />
|
||||
<property name="dfhGroupId" value="0" />
|
||||
<property name="dfhParameterId" value="" />
|
||||
<property name="dfhParameterName" value="" />
|
||||
<property name="dfhParameterVersion" value="" />
|
||||
<property name="dfhParameterData" value="" />
|
||||
<property name="dfhParameterDataLength" value="" />
|
||||
<property name="dfhFeatureMajorVersion" value="0" />
|
||||
<property name="dfhFeatureMinorVersion" value="0" />
|
||||
<property name="dfhFeatureId" value="35" />
|
||||
<property name="dfhFeatureType" value="3" />
|
||||
<port name="address" direction="input" role="address" width="2" />
|
||||
<port name="write_n" direction="input" role="write_n" width="1" />
|
||||
<port name="writedata" direction="input" role="writedata" width="32" />
|
||||
<port name="chipselect" direction="input" role="chipselect" width="1" />
|
||||
<port name="readdata" direction="output" role="readdata" width="32" />
|
||||
</interface>
|
||||
<interface name="external_connection" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<property name="prSafe" value="false" />
|
||||
<port name="in_port" direction="input" role="in_port" width="3" />
|
||||
<port name="out_port" direction="output" role="out_port" width="3" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="led_pio" version="1.0" name="led_pio">
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_S1_CPU_INFO_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/synth/led_pio.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/synth/led_pio.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Info" culprit="led_pio">"Generating: led_pio"</message>
|
||||
<message level="Info" culprit="led_pio">"Generating: led_pio_altera_avalon_pio_1924_yrkgeby"</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=led_pio_altera_avalon_pio_1924_yrkgeby --dir=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen//led_pio_altera_avalon_pio_1924_yrkgeby_component_configuration.pl --do_build_sim=0 ]</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
kind="altera_avalon_pio"
|
||||
version="19.2.4"
|
||||
name="led_pio_altera_avalon_pio_1924_yrkgeby">
|
||||
<parameter name="DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="derived_do_test_bench_wiring" value="false" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="derived_has_irq" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="100000000" />
|
||||
<parameter name="derived_has_out" value="true" />
|
||||
<parameter name="derived_has_in" value="true" />
|
||||
<parameter name="resetValue" value="7" />
|
||||
<parameter name="derived_has_tri" value="false" />
|
||||
<parameter name="derived_capture" value="false" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="derived_edge_type" value="NONE" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
<parameter name="derived_irq_type" value="NONE" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="width" value="3" />
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="direction" value="InOut" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/altera_avalon_pio_1924/synth/led_pio_altera_avalon_pio_1924_yrkgeby.v"
|
||||
attributes="" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/altera_avalon_pio_1924/synth/led_pio_altera_avalon_pio_1924_yrkgeby.v"
|
||||
attributes="" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="led_pio" as="altera_avalon_pio_inst" />
|
||||
<messages>
|
||||
<message level="Info" culprit="led_pio">"Generating: led_pio_altera_avalon_pio_1924_yrkgeby"</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst"> Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=led_pio_altera_avalon_pio_1924_yrkgeby --dir=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen//led_pio_altera_avalon_pio_1924_yrkgeby_component_configuration.pl --do_build_sim=0 ]</message>
|
||||
<message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,13 @@
|
||||
module led_pio (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
input wire [1:0] address, // s1.address
|
||||
input wire write_n, // .write_n
|
||||
input wire [31:0] writedata, // .writedata
|
||||
input wire chipselect, // .chipselect
|
||||
output wire [31:0] readdata, // .readdata
|
||||
input wire [2:0] in_port, // external_connection.in_port
|
||||
output wire [2:0] out_port // .out_port
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: led_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: led_pio: "Transforming system: led_pio"
|
||||
Info: led_pio: "Naming system components in system: led_pio"
|
||||
Info: led_pio: "Processing generation queue"
|
||||
Info: led_pio: "Generating: led_pio"
|
||||
Info: led_pio: "Generating: led_pio_altera_avalon_pio_1924_yrkgeby"
|
||||
Info: altera_avalon_pio_inst: Starting RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'
|
||||
Info: altera_avalon_pio_inst: Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=led_pio_altera_avalon_pio_1924_yrkgeby --dir=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen//led_pio_altera_avalon_pio_1924_yrkgeby_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: altera_avalon_pio_inst: Done RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'
|
||||
Info: led_pio: Done "led_pio" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,14 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: led_pio.altera_avalon_pio_inst: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: led_pio: "Transforming system: led_pio"
|
||||
Info: led_pio: "Naming system components in system: led_pio"
|
||||
Info: led_pio: "Processing generation queue"
|
||||
Info: led_pio: "Generating: led_pio"
|
||||
Info: led_pio: "Generating: led_pio_altera_avalon_pio_1924_yrkgeby"
|
||||
Info: altera_avalon_pio_inst: Starting RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'
|
||||
Info: altera_avalon_pio_inst: Generation command is [exec /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/bin/perl -I /home/ubuntu/altera_pro/25.3.1/quartus/linux64//perl/lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/europa -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin/perl_lib -I /home/ubuntu/altera_pro/25.3.1/quartus/sopc_builder/bin -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio -- /home/ubuntu/altera_pro/25.3.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=led_pio_altera_avalon_pio_1924_yrkgeby --dir=/tmp/alt0585_1616509418156170056.dir/0003_altera_avalon_pio_inst_gen/ --quartus_dir=/home/ubuntu/altera_pro/25.3.1/quartus --verilog --config=/tmp/alt0585_1616509418156170056.dir/0003_altera_avalon_pio_inst_gen//led_pio_altera_avalon_pio_1924_yrkgeby_component_configuration.pl --do_build_sim=0 ]
|
||||
Info: altera_avalon_pio_inst: Done RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'
|
||||
Info: led_pio: Done "led_pio" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,12 @@
|
||||
led_pio u0 (
|
||||
.clk (_connected_to_clk_), // input, width = 1, clk.clk
|
||||
.reset_n (_connected_to_reset_n_), // input, width = 1, reset.reset_n
|
||||
.address (_connected_to_address_), // input, width = 2, s1.address
|
||||
.write_n (_connected_to_write_n_), // input, width = 1, .write_n
|
||||
.writedata (_connected_to_writedata_), // input, width = 32, .writedata
|
||||
.chipselect (_connected_to_chipselect_), // input, width = 1, .chipselect
|
||||
.readdata (_connected_to_readdata_), // output, width = 32, .readdata
|
||||
.in_port (_connected_to_in_port_), // input, width = 3, external_connection.in_port
|
||||
.out_port (_connected_to_out_port_) // output, width = 3, .out_port
|
||||
);
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
component led_pio is
|
||||
port (
|
||||
clk : in std_logic := 'X'; -- clk
|
||||
reset_n : in std_logic := 'X'; -- reset_n
|
||||
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
|
||||
write_n : in std_logic := 'X'; -- write_n
|
||||
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||||
chipselect : in std_logic := 'X'; -- chipselect
|
||||
readdata : out std_logic_vector(31 downto 0); -- readdata
|
||||
in_port : in std_logic_vector(2 downto 0) := (others => 'X'); -- in_port
|
||||
out_port : out std_logic_vector(2 downto 0) -- out_port
|
||||
);
|
||||
end component led_pio;
|
||||
|
||||
u0 : component led_pio
|
||||
port map (
|
||||
clk => CONNECTED_TO_clk, -- clk.clk
|
||||
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
|
||||
address => CONNECTED_TO_address, -- s1.address
|
||||
write_n => CONNECTED_TO_write_n, -- .write_n
|
||||
writedata => CONNECTED_TO_writedata, -- .writedata
|
||||
chipselect => CONNECTED_TO_chipselect, -- .chipselect
|
||||
readdata => CONNECTED_TO_readdata, -- .readdata
|
||||
in_port => CONNECTED_TO_in_port, -- external_connection.in_port
|
||||
out_port => CONNECTED_TO_out_port -- .out_port
|
||||
);
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
// led_pio.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module led_pio (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
input wire [1:0] address, // s1.address
|
||||
input wire write_n, // .write_n
|
||||
input wire [31:0] writedata, // .writedata
|
||||
input wire chipselect, // .chipselect
|
||||
output wire [31:0] readdata, // .readdata
|
||||
input wire [2:0] in_port, // external_connection.in_port
|
||||
output wire [2:0] out_port // .out_port
|
||||
);
|
||||
|
||||
led_pio_altera_avalon_pio_1924_yrkgeby altera_avalon_pio_inst (
|
||||
.clk (clk), // input, width = 1, clk.clk
|
||||
.reset_n (reset_n), // input, width = 1, reset.reset_n
|
||||
.address (address), // input, width = 2, s1.address
|
||||
.write_n (write_n), // input, width = 1, .write_n
|
||||
.writedata (writedata), // input, width = 32, .writedata
|
||||
.chipselect (chipselect), // input, width = 1, .chipselect
|
||||
.readdata (readdata), // output, width = 32, .readdata
|
||||
.in_port (in_port), // input, width = 3, external_connection.in_port
|
||||
.out_port (out_port) // output, width = 3, .out_port
|
||||
);
|
||||
|
||||
endmodule
|
||||
+1956
File diff suppressed because it is too large
Load Diff
+1392
File diff suppressed because it is too large
Load Diff
+416
@@ -0,0 +1,416 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2019 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_merlin_waitrequest_adapter/altera_merlin_waitrequest_adapter.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
`default_nettype none
|
||||
|
||||
module altera_merlin_waitrequest_adapter # (
|
||||
parameter
|
||||
UAV_ADDRESS_W = 32,
|
||||
UAV_DATA_W = 32,
|
||||
UAV_BURSTCOUNT_W = 10,
|
||||
UAV_BYTEENABLE_W = 4,
|
||||
|
||||
// Optional
|
||||
USE_WRITERESPONSE = 1,
|
||||
USE_READRESPONSE = 1,
|
||||
|
||||
S0_WAITREQUEST_ALLOWANCE = 1, // Master waitrequest allowance
|
||||
M0_WAITREQUEST_ALLOWANCE = 0, // Slave waitrequest allowance
|
||||
SYNC_RESET = 0
|
||||
|
||||
)(
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
// Universal Avalon Master
|
||||
input wire s0_write,
|
||||
input wire s0_read,
|
||||
input wire [UAV_ADDRESS_W -1 : 0] s0_address,
|
||||
input wire [UAV_BURSTCOUNT_W -1 : 0] s0_burstcount,
|
||||
input wire [UAV_BYTEENABLE_W -1 : 0] s0_byteenable,
|
||||
input wire [UAV_DATA_W -1 : 0] s0_writedata,
|
||||
input wire s0_lock,
|
||||
input wire s0_debugaccess,
|
||||
|
||||
output wire [UAV_DATA_W -1 : 0] s0_readdata,
|
||||
output wire s0_readdatavalid,
|
||||
output wire s0_waitrequest,
|
||||
output wire [1 : 0] s0_response,
|
||||
output wire s0_writeresponsevalid,
|
||||
|
||||
// Universal Avalon Master
|
||||
output wire m0_write,
|
||||
output wire m0_read,
|
||||
output wire [UAV_ADDRESS_W -1 : 0] m0_address,
|
||||
output wire [UAV_BURSTCOUNT_W -1 : 0] m0_burstcount,
|
||||
output wire [UAV_BYTEENABLE_W -1 : 0] m0_byteenable,
|
||||
output wire [UAV_DATA_W -1 : 0] m0_writedata,
|
||||
output wire m0_lock,
|
||||
output wire m0_debugaccess,
|
||||
|
||||
input wire [UAV_DATA_W -1 : 0] m0_readdata,
|
||||
input wire m0_readdatavalid,
|
||||
input wire m0_waitrequest,
|
||||
input wire [1 : 0] m0_response,
|
||||
input wire m0_writeresponsevalid
|
||||
);
|
||||
|
||||
// Local parameters
|
||||
localparam SYMBOL_W = 8;
|
||||
localparam WRITE_W = 1;
|
||||
localparam READ_W = 1;
|
||||
localparam LOCK_W = 1;
|
||||
localparam DEBUGACCESS_W = 1;
|
||||
|
||||
localparam PAYLOAD_W = WRITE_W + READ_W + LOCK_W + DEBUGACCESS_W +
|
||||
UAV_ADDRESS_W + UAV_DATA_W + UAV_BYTEENABLE_W + UAV_BURSTCOUNT_W ;
|
||||
|
||||
localparam LOG_IN_WAIT = $clog2(S0_WAITREQUEST_ALLOWANCE);
|
||||
localparam LOG_OUT_WAIT = $clog2(M0_WAITREQUEST_ALLOWANCE);
|
||||
localparam DIFF_WAITREQ = (S0_WAITREQUEST_ALLOWANCE > M0_WAITREQUEST_ALLOWANCE) ?
|
||||
(S0_WAITREQUEST_ALLOWANCE - M0_WAITREQUEST_ALLOWANCE) :
|
||||
(M0_WAITREQUEST_ALLOWANCE - S0_WAITREQUEST_ALLOWANCE);
|
||||
|
||||
// For master_gt0_slave_eq0
|
||||
localparam USE_MEMORY = (S0_WAITREQUEST_ALLOWANCE > 2);
|
||||
// Add more buffer in FIFO so waitreq does not assert waitreq on very
|
||||
// first transaction - hence 2**(LOG_IN+WAIT+1)
|
||||
// so buffer is getting 2X here, but we dont want too deep buffer
|
||||
// dont do this if (2Xrequired buffer - new_buffer) >6
|
||||
localparam FIFO_DEPTH = (USE_MEMORY == 1) ? 2**LOG_IN_WAIT : S0_WAITREQUEST_ALLOWANCE + 2;
|
||||
localparam BUFFER_2X = 2*S0_WAITREQUEST_ALLOWANCE;
|
||||
localparam FIFO_DEPTH_DEEPER = 2**(LOG_IN_WAIT+1);
|
||||
localparam FIFO_SIZE = ((FIFO_DEPTH_DEEPER-BUFFER_2X)>6) ? 2**LOG_IN_WAIT : FIFO_DEPTH_DEEPER ;
|
||||
localparam FIFO_DEPTH_M20K = (USE_MEMORY == 1) ? FIFO_SIZE : S0_WAITREQUEST_ALLOWANCE + 2;
|
||||
localparam EMPTY_LATENCY = (USE_MEMORY == 1) ? 3 : 0;
|
||||
localparam ALMOST_FULL_THRESHOLD = (USE_MEMORY == 1) ? (((FIFO_DEPTH % S0_WAITREQUEST_ALLOWANCE) == 0) ? 1 : (FIFO_DEPTH % S0_WAITREQUEST_ALLOWANCE))
|
||||
: 2;
|
||||
localparam ALMOST_FULL_THRESHOLD_M20K = (USE_MEMORY == 1) ? (ALMOST_FULL_THRESHOLD+4) : ALMOST_FULL_THRESHOLD ;
|
||||
localparam IMPL = (USE_MEMORY == 1) ? "infer" : "reg";
|
||||
|
||||
localparam NUM_128BIT_SLOTS = (PAYLOAD_W / 128) + (((PAYLOAD_W % 128) == 0) ? 0 : 1);
|
||||
localparam LAST_PAYLOAD_W = ((PAYLOAD_W % 128) == 0) ? 128 : (PAYLOAD_W % 128);
|
||||
genvar i;
|
||||
|
||||
wire [PAYLOAD_W-1:0] m0_payload;
|
||||
wire [PAYLOAD_W-1:0] s0_payload;
|
||||
|
||||
wire m0_valid;
|
||||
wire fifo_pop;
|
||||
wire s0_valid = s0_read | s0_write;
|
||||
|
||||
wire m0_payload_read;
|
||||
wire m0_payload_write;
|
||||
|
||||
assign m0_write = m0_payload_write & m0_valid;
|
||||
assign m0_read = m0_payload_read & m0_valid;
|
||||
|
||||
// Response Signals
|
||||
// Pass-through
|
||||
assign s0_readdata = m0_readdata;
|
||||
assign s0_readdatavalid = m0_readdatavalid;
|
||||
assign s0_response = m0_response;
|
||||
assign s0_writeresponsevalid = m0_writeresponsevalid;
|
||||
|
||||
// Slave payload
|
||||
assign s0_payload = {
|
||||
s0_write,
|
||||
s0_read,
|
||||
s0_address,
|
||||
s0_burstcount,
|
||||
s0_byteenable,
|
||||
s0_writedata,
|
||||
s0_lock,
|
||||
s0_debugaccess
|
||||
};
|
||||
|
||||
// Master payload
|
||||
assign {
|
||||
m0_payload_write,
|
||||
m0_payload_read,
|
||||
m0_address,
|
||||
m0_burstcount,
|
||||
m0_byteenable,
|
||||
m0_writedata,
|
||||
m0_lock,
|
||||
m0_debugaccess
|
||||
} = m0_payload;
|
||||
|
||||
|
||||
// Generation of internal reset synchronization
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// Adapter core logic
|
||||
generate
|
||||
if(S0_WAITREQUEST_ALLOWANCE == M0_WAITREQUEST_ALLOWANCE) begin : eq_wait_req
|
||||
assign m0_payload = s0_payload;
|
||||
assign m0_valid = s0_valid;
|
||||
assign s0_waitrequest = m0_waitrequest;
|
||||
end
|
||||
|
||||
if(S0_WAITREQUEST_ALLOWANCE == 0 && M0_WAITREQUEST_ALLOWANCE != 0) begin : master_eq0_slave_gt0
|
||||
assign m0_payload = s0_payload;
|
||||
assign m0_valid = s0_valid & ~m0_waitrequest;
|
||||
assign s0_waitrequest = m0_waitrequest;
|
||||
end
|
||||
|
||||
if(S0_WAITREQUEST_ALLOWANCE > 0 && (S0_WAITREQUEST_ALLOWANCE < M0_WAITREQUEST_ALLOWANCE)) begin : master_lt_slave_neq0
|
||||
assign m0_valid = s0_valid;
|
||||
assign m0_payload = s0_payload;
|
||||
assign s0_waitrequest = m0_waitrequest;
|
||||
end
|
||||
|
||||
if(S0_WAITREQUEST_ALLOWANCE > 0 && (M0_WAITREQUEST_ALLOWANCE == 0)) begin : master_gt0_slave_eq0
|
||||
wire fifo_data_valid;
|
||||
|
||||
assign fifo_pop = fifo_data_valid & ~m0_waitrequest;
|
||||
assign m0_valid = fifo_data_valid;
|
||||
|
||||
|
||||
for (i = 0; i < NUM_128BIT_SLOTS; i = i + 1) begin : gen_inst
|
||||
if (i == NUM_128BIT_SLOTS - 1) begin
|
||||
altera_avalon_sc_fifo # (
|
||||
.SYMBOLS_PER_BEAT (1),
|
||||
.BITS_PER_SYMBOL (LAST_PAYLOAD_W),
|
||||
.FIFO_DEPTH (FIFO_DEPTH_M20K),
|
||||
.EMPTY_LATENCY (EMPTY_LATENCY),
|
||||
.USE_FILL_LEVEL (1),
|
||||
.USE_MEMORY_BLOCKS (USE_MEMORY),
|
||||
.USE_ALMOST_FULL_IF (1),
|
||||
.ALMOST_FULL_THRESHOLD (ALMOST_FULL_THRESHOLD_M20K),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) adapter_fifo (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.in_data (s0_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
|
||||
.in_valid (s0_valid), // Write
|
||||
.in_startofpacket (1'b0),
|
||||
.in_endofpacket (1'b0),
|
||||
.in_empty (1'b0),
|
||||
.in_error (1'b0),
|
||||
.in_channel (1'b0),
|
||||
.in_ready (),
|
||||
|
||||
.out_data (m0_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
|
||||
.out_valid (fifo_data_valid),
|
||||
.out_startofpacket(),
|
||||
.out_endofpacket (),
|
||||
.out_empty (),
|
||||
.out_error (),
|
||||
.out_channel (),
|
||||
|
||||
.out_ready (fifo_pop), // Read
|
||||
.almost_full_data (s0_waitrequest)
|
||||
|
||||
);
|
||||
end
|
||||
else begin
|
||||
altera_avalon_sc_fifo # (
|
||||
.SYMBOLS_PER_BEAT (1),
|
||||
.BITS_PER_SYMBOL (128),
|
||||
.FIFO_DEPTH (FIFO_DEPTH_M20K),
|
||||
.EMPTY_LATENCY (EMPTY_LATENCY),
|
||||
.USE_FILL_LEVEL (1),
|
||||
.USE_MEMORY_BLOCKS (USE_MEMORY),
|
||||
.USE_ALMOST_FULL_IF (1),
|
||||
.ALMOST_FULL_THRESHOLD (ALMOST_FULL_THRESHOLD_M20K),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) adapter_fifo (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.in_data (s0_payload[(i+1)*128-1:i*128]),
|
||||
.in_valid (s0_valid), // Write
|
||||
.in_startofpacket (1'b0),
|
||||
.in_endofpacket (1'b0),
|
||||
.in_empty (1'b0),
|
||||
.in_error (1'b0),
|
||||
.in_channel (1'b0),
|
||||
.in_ready (),
|
||||
|
||||
.out_data (m0_payload[(i+1)*128-1:i*128]),
|
||||
.out_valid (),
|
||||
.out_startofpacket(),
|
||||
.out_endofpacket (),
|
||||
.out_empty (),
|
||||
.out_error (),
|
||||
.out_channel (),
|
||||
|
||||
.out_ready (fifo_pop), // Read
|
||||
.almost_full_data ()
|
||||
|
||||
);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if(M0_WAITREQUEST_ALLOWANCE > 0 && (S0_WAITREQUEST_ALLOWANCE > M0_WAITREQUEST_ALLOWANCE)) begin
|
||||
|
||||
reg [LOG_OUT_WAIT:0] count;
|
||||
wire fifo_data_valid;
|
||||
reg [S0_WAITREQUEST_ALLOWANCE - M0_WAITREQUEST_ALLOWANCE - 1 : 0]m0_waitrequest_q;
|
||||
if (SYNC_RESET == 0 ) begin // aysnc_reg0
|
||||
|
||||
always @ (posedge clk, posedge reset) begin
|
||||
if(reset) begin
|
||||
count <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if(m0_waitrequest) begin
|
||||
if(fifo_data_valid & (count < M0_WAITREQUEST_ALLOWANCE)) begin
|
||||
count <= count + 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
count <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // async_reg0
|
||||
else begin // sync_reg0
|
||||
always @ (posedge clk) begin
|
||||
if(internal_sclr) begin
|
||||
count <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if(m0_waitrequest) begin
|
||||
if(fifo_data_valid & (count < M0_WAITREQUEST_ALLOWANCE)) begin
|
||||
count <= count + 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
count <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // sync_reg0
|
||||
|
||||
|
||||
if (SYNC_RESET == 0) begin // async_reg1
|
||||
if(DIFF_WAITREQ == 1) begin
|
||||
always @ (posedge clk, posedge reset) begin
|
||||
if(reset) begin
|
||||
m0_waitrequest_q <= m0_waitrequest;
|
||||
end
|
||||
else begin
|
||||
m0_waitrequest_q <= m0_waitrequest;
|
||||
end
|
||||
end
|
||||
end
|
||||
else if(DIFF_WAITREQ >= 2) begin
|
||||
always @ (posedge clk, posedge reset) begin
|
||||
if(reset) begin
|
||||
m0_waitrequest_q <= m0_waitrequest;
|
||||
end
|
||||
else begin
|
||||
m0_waitrequest_q <= {m0_waitrequest_q[DIFF_WAITREQ - 2 : 0], m0_waitrequest};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end // async_reg1
|
||||
else begin //sync_reg1
|
||||
if(DIFF_WAITREQ == 1) begin
|
||||
always @ (posedge clk) begin
|
||||
if(internal_sclr) begin
|
||||
m0_waitrequest_q <= m0_waitrequest;
|
||||
end
|
||||
else begin
|
||||
m0_waitrequest_q <= m0_waitrequest;
|
||||
end
|
||||
end
|
||||
end
|
||||
else if(DIFF_WAITREQ >= 2) begin
|
||||
always @ (posedge clk) begin
|
||||
if(internal_sclr) begin
|
||||
m0_waitrequest_q <= m0_waitrequest;
|
||||
end
|
||||
else begin
|
||||
m0_waitrequest_q <= {m0_waitrequest_q[DIFF_WAITREQ - 2 : 0], m0_waitrequest};
|
||||
end
|
||||
end
|
||||
end
|
||||
end // sync_reg1
|
||||
|
||||
assign m0_valid = fifo_data_valid & (~m0_waitrequest | (count < M0_WAITREQUEST_ALLOWANCE));
|
||||
assign fifo_pop = m0_valid;
|
||||
assign s0_waitrequest = m0_waitrequest | (|m0_waitrequest_q);
|
||||
|
||||
altera_avalon_sc_fifo # (
|
||||
.SYMBOLS_PER_BEAT (1),
|
||||
.BITS_PER_SYMBOL (PAYLOAD_W),
|
||||
// set min fifo depth =2 to avoid 1 deep SC FIFO issues
|
||||
.FIFO_DEPTH ((S0_WAITREQUEST_ALLOWANCE-M0_WAITREQUEST_ALLOWANCE == 1)? 2 : S0_WAITREQUEST_ALLOWANCE - M0_WAITREQUEST_ALLOWANCE),
|
||||
.EMPTY_LATENCY (0), // Lookahead
|
||||
.USE_FILL_LEVEL (0),
|
||||
.USE_MEMORY_BLOCKS (0),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) adapter_fifo (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.in_data (s0_payload),
|
||||
.in_valid (s0_valid), // Write
|
||||
.in_startofpacket (1'b0),
|
||||
.in_endofpacket (1'b0),
|
||||
.in_empty (1'b0),
|
||||
.in_error (1'b0),
|
||||
.in_channel (1'b0),
|
||||
.in_ready (),
|
||||
|
||||
.out_data (m0_payload),
|
||||
.out_valid (fifo_data_valid),
|
||||
.out_startofpacket(),
|
||||
.out_endofpacket (),
|
||||
.out_empty (),
|
||||
.out_error (),
|
||||
.out_channel (),
|
||||
|
||||
.out_ready (fifo_pop) // Read
|
||||
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "G5I3YpoCXBJB615bV2r2gMjlqLnNMBjlz2IHpbFJcrIwatpnQBq0w6xgRawbwcYhtT8Bi7pW+71GhRzEnCQuQre2+enKubtY0F7Li98guTCkKwcqYqAMbCsAKNYuoV1MCy37Y0IFMQqSuFjec6QHj+m+L1hSx7OW0pZtmbnEVr6mG3FWyYPyobrPnEk5U9j/t9f5YWIrLfdwixx/s3z+Rxz6WBaR9gZefEC5zBeQpuFWsH9iPtku9Pi6KhtuH0861XuLOoFxauUbRIsqPNRVsDOPf2I/5eMDyWcToJ2Z7LMfFKK8hY/oU5G5Mew0zXVW64nGyMSAjdx8ilt1JbKhys980EhEunL5Kpx+3Bm4lXZucvWlAuj3gyGj91sqIErvLYOZQEEePIluyTDfjRAAMmg/HBpLJb3I4eJyJQLIDVo73/BGRbF7OzqW/or3RPS96pzIwq/15CkxD+8KyCmmcmi1nxDhz9jFpCsCbNrodKyJvn8HE292MV+LIaG/J/tcJqB/n6m9gAOYYfGM/qAdOBj+WG5fax3BWyQg8zN26y0rMhr/8elx7IZORQYAm3pQH4Jg/60q9lf+x09zBznuvry0K/S07mB3t27fcbnpp8fdKM2MeJunTLADjrzQOZ+UUYrTOBImqKf7Df5mfrRPL1WhNBB5jWmvFWWf55r83Or5kNL5ksZvvDL6R0eq/+9JOPgt7+3VmahD4LciJnrFp7GFrqF1SP4VK93Yc9pZHhT3lKkEINZZokqKwr5GdVHwE4Gif3UgPYh9wBBSFIBcxIFMr8LqupqLNcAuHDCMx8rzPZtQyB6TvSqRdIxKP1a9Wuny5k06NCqQO42YX2zPGdMQEWpawgwpTDvhzrEw2MdvhWfGIgVJ4Qzl/c9mk/9vtnrbfD7PPMFWV4S7ZqDNQOXDO+4sZi6ze0bQY/lz4h8AvtVUPWSvOaaHRVx/uPFPhdAnOqIv0KK6VfvvUH6/m+wQ3jEawPCMVAzR43b8pkExbHTTyX3V8LXY5nBykvuI"
|
||||
`endif
|
||||
+509
@@ -0,0 +1,509 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------
|
||||
// Avalon-MM pipeline bridge
|
||||
//
|
||||
// Optionally registers Avalon-MM command and response signals
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
module pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i
|
||||
#(
|
||||
parameter DATA_WIDTH = 32,
|
||||
parameter SYMBOL_WIDTH = 8,
|
||||
parameter RESPONSE_WIDTH = 2,
|
||||
parameter HDL_ADDR_WIDTH = 10,
|
||||
parameter BURSTCOUNT_WIDTH = 1,
|
||||
|
||||
parameter PIPELINE_COMMAND = 1,
|
||||
parameter PIPELINE_RESPONSE = 1,
|
||||
parameter SYNC_RESET = 0,
|
||||
parameter USE_WRITERESPONSE = 0,
|
||||
|
||||
parameter S0_WAITREQUEST_ALLOWANCE = 0,
|
||||
parameter M0_WAITREQUEST_ALLOWANCE = 0,
|
||||
|
||||
// --------------------------------------
|
||||
// Derived parameters
|
||||
// --------------------------------------
|
||||
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
output s0_waitrequest,
|
||||
output [DATA_WIDTH-1:0] s0_readdata,
|
||||
output s0_readdatavalid,
|
||||
output s0_writeresponsevalid,
|
||||
output [RESPONSE_WIDTH-1:0] s0_response,
|
||||
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
|
||||
input [DATA_WIDTH-1:0] s0_writedata,
|
||||
input [HDL_ADDR_WIDTH-1:0] s0_address,
|
||||
input s0_write,
|
||||
input s0_read,
|
||||
input [BYTEEN_WIDTH-1:0] s0_byteenable,
|
||||
input s0_debugaccess,
|
||||
|
||||
input m0_waitrequest,
|
||||
input [DATA_WIDTH-1:0] m0_readdata,
|
||||
input m0_readdatavalid,
|
||||
input m0_writeresponsevalid,
|
||||
input [RESPONSE_WIDTH-1:0] m0_response,
|
||||
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
|
||||
output [DATA_WIDTH-1:0] m0_writedata,
|
||||
output [HDL_ADDR_WIDTH-1:0] m0_address,
|
||||
output m0_write,
|
||||
output m0_read,
|
||||
output [BYTEEN_WIDTH-1:0] m0_byteenable,
|
||||
output m0_debugaccess
|
||||
);
|
||||
// --------------------------------------
|
||||
// Registers & signals
|
||||
// --------------------------------------
|
||||
reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount;
|
||||
reg [DATA_WIDTH-1:0] cmd_writedata;
|
||||
reg [HDL_ADDR_WIDTH-1:0] cmd_address;
|
||||
reg cmd_write;
|
||||
reg cmd_read;
|
||||
reg [BYTEEN_WIDTH-1:0] cmd_byteenable;
|
||||
wire cmd_waitrequest;
|
||||
reg cmd_debugaccess;
|
||||
|
||||
reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount;
|
||||
reg [DATA_WIDTH-1:0] wr_writedata;
|
||||
reg [HDL_ADDR_WIDTH-1:0] wr_address;
|
||||
reg wr_write;
|
||||
reg wr_read;
|
||||
reg [BYTEEN_WIDTH-1:0] wr_byteenable;
|
||||
reg wr_debugaccess;
|
||||
|
||||
reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount;
|
||||
reg [DATA_WIDTH-1:0] wr_reg_writedata;
|
||||
reg [HDL_ADDR_WIDTH-1:0] wr_reg_address;
|
||||
reg wr_reg_write;
|
||||
reg wr_reg_read;
|
||||
reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable;
|
||||
reg wr_reg_waitrequest;
|
||||
reg wr_reg_debugaccess;
|
||||
|
||||
reg use_reg;
|
||||
wire wait_rise;
|
||||
|
||||
reg [DATA_WIDTH-1:0] rsp_readdata;
|
||||
reg rsp_readdatavalid;
|
||||
reg [RESPONSE_WIDTH-1:0] rsp_response;
|
||||
|
||||
reg rsp_writeresponsevalid;
|
||||
|
||||
wire [BURSTCOUNT_WIDTH-1:0] burst_reset_val;
|
||||
|
||||
//Connections with wait request adaptor
|
||||
wire s0_waitrequest_from_adaptor;
|
||||
wire [DATA_WIDTH-1:0] s0_readdata_from_adaptor;
|
||||
wire s0_readdatavalid_from_adaptor;
|
||||
wire s0_writeresponsevalid_from_adaptor;
|
||||
wire [RESPONSE_WIDTH-1:0] s0_response_from_adaptor;
|
||||
|
||||
wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount_from_adaptor;
|
||||
wire [DATA_WIDTH-1:0] m0_writedata_from_adaptor;
|
||||
wire [HDL_ADDR_WIDTH-1:0] m0_address_from_adaptor;
|
||||
wire m0_write_from_adaptor;
|
||||
wire m0_read_from_adaptor;
|
||||
wire [BYTEEN_WIDTH-1:0] m0_byteenable_from_adaptor;
|
||||
wire m0_debugaccess_from_adaptor;
|
||||
|
||||
generate
|
||||
if (BURSTCOUNT_WIDTH > 1) begin
|
||||
assign burst_reset_val = {{(BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
|
||||
end else begin
|
||||
assign burst_reset_val = 1'b1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// generating sync reset
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin // rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// This instance manages waitrequest allowance feature
|
||||
|
||||
altera_merlin_waitrequest_adapter #(
|
||||
|
||||
.UAV_ADDRESS_W (HDL_ADDR_WIDTH),
|
||||
.UAV_DATA_W (DATA_WIDTH),
|
||||
.UAV_BURSTCOUNT_W (BURSTCOUNT_WIDTH),
|
||||
.UAV_BYTEENABLE_W (BYTEEN_WIDTH),
|
||||
|
||||
// Optional
|
||||
.USE_WRITERESPONSE (1),
|
||||
.USE_READRESPONSE (1),
|
||||
|
||||
.S0_WAITREQUEST_ALLOWANCE (S0_WAITREQUEST_ALLOWANCE),
|
||||
.M0_WAITREQUEST_ALLOWANCE (M0_WAITREQUEST_ALLOWANCE),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
|
||||
) waitrequest_adapter (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
||||
// Universal Avalon Slave
|
||||
// Inputs
|
||||
.s0_write (s0_write),
|
||||
.s0_read (s0_read),
|
||||
.s0_address (s0_address),
|
||||
.s0_burstcount (s0_burstcount),
|
||||
.s0_byteenable (s0_byteenable),
|
||||
.s0_writedata (s0_writedata),
|
||||
.s0_lock (1'b0),
|
||||
.s0_debugaccess (s0_debugaccess),
|
||||
|
||||
//output
|
||||
.s0_readdata (s0_readdata_from_adaptor),
|
||||
.s0_readdatavalid (s0_readdatavalid_from_adaptor),
|
||||
.s0_waitrequest (s0_waitrequest_from_adaptor),
|
||||
.s0_response (s0_response_from_adaptor),
|
||||
.s0_writeresponsevalid (s0_writeresponsevalid_from_adaptor),
|
||||
|
||||
// Universal Avalon Master
|
||||
// Output
|
||||
.m0_write (m0_write_from_adaptor),
|
||||
.m0_read (m0_read_from_adaptor),
|
||||
.m0_address (m0_address_from_adaptor),
|
||||
.m0_burstcount (m0_burstcount_from_adaptor),
|
||||
.m0_byteenable (m0_byteenable_from_adaptor),
|
||||
.m0_writedata (m0_writedata_from_adaptor),
|
||||
.m0_lock (),
|
||||
.m0_debugaccess (m0_debugaccess_from_adaptor),
|
||||
|
||||
|
||||
//Inputs
|
||||
.m0_readdata (m0_readdata),
|
||||
.m0_readdatavalid (m0_readdatavalid),
|
||||
.m0_waitrequest (m0_waitrequest),
|
||||
.m0_response (m0_response),
|
||||
.m0_writeresponsevalid (m0_writeresponsevalid)
|
||||
);
|
||||
|
||||
// --------------------------------------
|
||||
// Command pipeline
|
||||
//
|
||||
// Registers all command signals, including waitrequest
|
||||
// --------------------------------------
|
||||
generate if (PIPELINE_COMMAND == 1) begin
|
||||
|
||||
// --------------------------------------
|
||||
// Waitrequest Pipeline Stage
|
||||
//
|
||||
// Output waitrequest is delayed by one cycle, which means
|
||||
// that a master will see waitrequest assertions one cycle
|
||||
// too late.
|
||||
//
|
||||
// Solution: buffer the command when waitrequest transitions
|
||||
// from low->high. As an optimization, we can safely assume
|
||||
// waitrequest is low by default because downstream logic
|
||||
// in the bridge ensures this.
|
||||
//
|
||||
// Note: this implementation buffers idle cycles should
|
||||
// waitrequest transition on such cycles. This is a potential
|
||||
// cause for throughput loss, but ye olde pipeline bridge did
|
||||
// the same for years and no one complained. Not buffering idle
|
||||
// cycles costs logic on the waitrequest path.
|
||||
// --------------------------------------
|
||||
assign s0_waitrequest = wr_reg_waitrequest;
|
||||
assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (wait_rise) begin
|
||||
wr_reg_writedata <= m0_writedata_from_adaptor ;
|
||||
wr_reg_byteenable <= m0_byteenable_from_adaptor ;
|
||||
wr_reg_address <= m0_address_from_adaptor ;
|
||||
end
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin // async_reg0
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
wr_reg_waitrequest <= 1'b1;
|
||||
// --------------------------------------
|
||||
// Bit of trickiness here, deserving of a long comment.
|
||||
//
|
||||
// On the first cycle after reset, the pass-through
|
||||
// must not be used or downstream logic may sample
|
||||
// the same command twice because of the delay in
|
||||
// transmitting a falling waitrequest.
|
||||
//
|
||||
// Using the registered command works on the condition
|
||||
// that downstream logic deasserts waitrequest
|
||||
// immediately after reset, which is true of the
|
||||
// next stage in this bridge.
|
||||
// --------------------------------------
|
||||
use_reg <= 1'b1;
|
||||
wr_reg_burstcount <= burst_reset_val;
|
||||
wr_reg_write <= 1'b0;
|
||||
wr_reg_read <= 1'b0;
|
||||
wr_reg_debugaccess <= 1'b0;
|
||||
end else begin
|
||||
wr_reg_waitrequest <= cmd_waitrequest;
|
||||
|
||||
if (wait_rise) begin
|
||||
wr_reg_write <= m0_write_from_adaptor ;
|
||||
wr_reg_read <= m0_read_from_adaptor ;
|
||||
wr_reg_burstcount <= m0_burstcount_from_adaptor ;
|
||||
wr_reg_debugaccess <= m0_debugaccess_from_adaptor ;
|
||||
end
|
||||
|
||||
// stop using the buffer when waitrequest is low
|
||||
if (~cmd_waitrequest)
|
||||
use_reg <= 1'b0;
|
||||
else if (wait_rise) begin
|
||||
use_reg <= 1'b1;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
end else begin // end aysnc_reg0
|
||||
// sync_reset
|
||||
always @(posedge clk) begin
|
||||
if (internal_sclr) begin
|
||||
wr_reg_waitrequest <= 1'b1;
|
||||
// --------------------------------------
|
||||
// Bit of trickiness here, deserving of a long comment.
|
||||
//
|
||||
// On the first cycle after reset, the pass-through
|
||||
// must not be used or downstream logic may sample
|
||||
// the same command twice because of the delay in
|
||||
// transmitting a falling waitrequest.
|
||||
//
|
||||
// Using the registered command works on the condition
|
||||
// that downstream logic deasserts waitrequest
|
||||
// immediately after reset, which is true of the
|
||||
// next stage in this bridge.
|
||||
// --------------------------------------
|
||||
use_reg <= 1'b1;
|
||||
|
||||
wr_reg_burstcount <= burst_reset_val;
|
||||
wr_reg_write <= 1'b0;
|
||||
wr_reg_read <= 1'b0;
|
||||
wr_reg_debugaccess <= 1'b0;
|
||||
end else begin
|
||||
wr_reg_waitrequest <= cmd_waitrequest;
|
||||
|
||||
if (wait_rise) begin
|
||||
wr_reg_write <= m0_write_from_adaptor ;
|
||||
wr_reg_read <= m0_read_from_adaptor ;
|
||||
wr_reg_burstcount <= m0_burstcount_from_adaptor ;
|
||||
wr_reg_debugaccess <= m0_debugaccess_from_adaptor ;
|
||||
end
|
||||
|
||||
// stop using the buffer when waitrequest is low
|
||||
if (~cmd_waitrequest)
|
||||
use_reg <= 1'b0;
|
||||
else if (wait_rise) begin
|
||||
use_reg <= 1'b1;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
end // if sync_reset
|
||||
|
||||
always @* begin
|
||||
wr_burstcount = m0_burstcount_from_adaptor ;
|
||||
wr_writedata = m0_writedata_from_adaptor ;
|
||||
wr_address = m0_address_from_adaptor ;
|
||||
wr_write = m0_write_from_adaptor ;
|
||||
wr_read = m0_read_from_adaptor ;
|
||||
wr_byteenable = m0_byteenable_from_adaptor ;
|
||||
wr_debugaccess = m0_debugaccess_from_adaptor ;
|
||||
|
||||
if (use_reg) begin
|
||||
wr_burstcount = wr_reg_burstcount;
|
||||
wr_writedata = wr_reg_writedata;
|
||||
wr_address = wr_reg_address;
|
||||
wr_write = wr_reg_write;
|
||||
wr_read = wr_reg_read;
|
||||
wr_byteenable = wr_reg_byteenable;
|
||||
wr_debugaccess = wr_reg_debugaccess;
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------
|
||||
// Master-Slave Signal Pipeline Stage
|
||||
//
|
||||
// One notable detail is that cmd_waitrequest is deasserted
|
||||
// when this stage is idle. This allows us to make logic
|
||||
// optimizations in the waitrequest pipeline stage.
|
||||
//
|
||||
// Also note that cmd_waitrequest is deasserted during reset,
|
||||
// which is not spec-compliant, but is ok for an internal
|
||||
// signal.
|
||||
// --------------------------------------
|
||||
wire no_command;
|
||||
assign no_command = ~(cmd_read || cmd_write);
|
||||
assign cmd_waitrequest = s0_waitrequest_from_adaptor & ~no_command;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~cmd_waitrequest) begin
|
||||
cmd_writedata <= wr_writedata;
|
||||
cmd_byteenable <= wr_byteenable;
|
||||
cmd_address <= wr_address;
|
||||
end
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin // async_reg1
|
||||
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
cmd_burstcount <= burst_reset_val; //1'b1;
|
||||
cmd_write <= 1'b0;
|
||||
cmd_read <= 1'b0;
|
||||
cmd_debugaccess <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (~cmd_waitrequest) begin
|
||||
cmd_write <= wr_write;
|
||||
cmd_read <= wr_read;
|
||||
cmd_burstcount <= wr_burstcount;
|
||||
cmd_debugaccess <= wr_debugaccess;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end else begin // aysnc_reg1
|
||||
|
||||
always @(posedge clk) begin //sync_reg1
|
||||
if (internal_sclr) begin
|
||||
cmd_burstcount <= burst_reset_val; //1'b1;
|
||||
cmd_write <= 1'b0;
|
||||
cmd_read <= 1'b0;
|
||||
cmd_debugaccess <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (~cmd_waitrequest) begin
|
||||
cmd_write <= wr_write;
|
||||
cmd_read <= wr_read;
|
||||
cmd_burstcount <= wr_burstcount;
|
||||
cmd_debugaccess <= wr_debugaccess;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // sync_reg1
|
||||
end // conditional command pipeline
|
||||
else begin
|
||||
|
||||
assign s0_waitrequest = s0_waitrequest_from_adaptor ;
|
||||
|
||||
always @* begin
|
||||
cmd_burstcount = m0_burstcount_from_adaptor ;
|
||||
cmd_writedata = m0_writedata_from_adaptor ;
|
||||
cmd_address = m0_address_from_adaptor ;
|
||||
cmd_write = m0_write_from_adaptor ;
|
||||
cmd_read = m0_read_from_adaptor ;
|
||||
cmd_byteenable = m0_byteenable_from_adaptor ;
|
||||
cmd_debugaccess = m0_debugaccess_from_adaptor ;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign m0_burstcount = cmd_burstcount;
|
||||
assign m0_writedata = cmd_writedata;
|
||||
assign m0_address = cmd_address;
|
||||
assign m0_write = cmd_write;
|
||||
assign m0_read = cmd_read;
|
||||
assign m0_byteenable = cmd_byteenable;
|
||||
assign m0_debugaccess = cmd_debugaccess;
|
||||
|
||||
// --------------------------------------
|
||||
// Response pipeline
|
||||
//
|
||||
// Registers all response signals
|
||||
// --------------------------------------
|
||||
generate if (PIPELINE_RESPONSE == 1) begin
|
||||
|
||||
always @(posedge clk) begin
|
||||
rsp_readdata <= m0_readdata;
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin // async_reg2
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
rsp_readdatavalid <= 1'b0;
|
||||
rsp_response <= 2'b00;
|
||||
rsp_writeresponsevalid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
rsp_readdatavalid <= s0_readdatavalid_from_adaptor ;
|
||||
rsp_response <= s0_response_from_adaptor ;
|
||||
rsp_writeresponsevalid <= s0_writeresponsevalid_from_adaptor ;
|
||||
end
|
||||
end
|
||||
end //async_reg2
|
||||
else begin // sync reg2
|
||||
always @(posedge clk) begin
|
||||
if (internal_sclr) begin
|
||||
rsp_readdatavalid <= 1'b0;
|
||||
rsp_response <= 2'b00;
|
||||
rsp_writeresponsevalid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
rsp_readdatavalid <= s0_readdatavalid_from_adaptor ;
|
||||
rsp_response <= s0_response_from_adaptor ;
|
||||
rsp_writeresponsevalid <= s0_writeresponsevalid_from_adaptor ;
|
||||
end
|
||||
end
|
||||
end // end sync_reg2
|
||||
|
||||
end // conditional response pipeline
|
||||
|
||||
else begin
|
||||
|
||||
always @* begin
|
||||
rsp_readdatavalid = s0_readdatavalid_from_adaptor ;
|
||||
rsp_readdata = s0_readdata_from_adaptor ;
|
||||
rsp_response = s0_response_from_adaptor ;
|
||||
rsp_writeresponsevalid = s0_writeresponsevalid_from_adaptor ;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign s0_readdatavalid = rsp_readdatavalid;
|
||||
assign s0_readdata = rsp_readdata;
|
||||
assign s0_response = rsp_response;
|
||||
|
||||
assign s0_writeresponsevalid = rsp_writeresponsevalid; //ensure port terminated responsibly in _hw.tcl, for this to work
|
||||
|
||||
// --------------------------------------
|
||||
// handle the writeresponsevalid o/p
|
||||
// if USE_WRITERESPONSE is not enabled, drive o/p to 0
|
||||
// to avoid "no driver" warning on o/p port
|
||||
// in case port not terminated responsibly in _hw.tcl
|
||||
// ---------------------------------------
|
||||
//generate
|
||||
// if (USE_WRITERESPONSE) begin
|
||||
// assign s0_writeresponsevalid = rsp_writeresponsevalid;
|
||||
// end else begin
|
||||
// assign s0_writeresponsevalid = 1'b0;
|
||||
// end
|
||||
//endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
component pb_cpu_0 is
|
||||
generic (
|
||||
DATA_WIDTH : integer := 32;
|
||||
SYMBOL_WIDTH : integer := 8;
|
||||
HDL_ADDR_WIDTH : integer := 17;
|
||||
BURSTCOUNT_WIDTH : integer := 1;
|
||||
PIPELINE_COMMAND : integer := 1;
|
||||
PIPELINE_RESPONSE : integer := 1;
|
||||
SYNC_RESET : integer := 0;
|
||||
USE_WRITERESPONSE : integer := 0;
|
||||
S0_WAITREQUEST_ALLOWANCE : integer := 0;
|
||||
M0_WAITREQUEST_ALLOWANCE : integer := 0
|
||||
);
|
||||
port (
|
||||
clk : in std_logic := 'X'; -- clk
|
||||
reset : in std_logic := 'X'; -- reset
|
||||
s0_waitrequest : out std_logic; -- waitrequest
|
||||
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
|
||||
s0_readdatavalid : out std_logic; -- readdatavalid
|
||||
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
|
||||
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
|
||||
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
|
||||
s0_write : in std_logic := 'X'; -- write
|
||||
s0_read : in std_logic := 'X'; -- read
|
||||
s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
|
||||
s0_debugaccess : in std_logic := 'X'; -- debugaccess
|
||||
m0_waitrequest : in std_logic := 'X'; -- waitrequest
|
||||
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
|
||||
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
|
||||
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
|
||||
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
|
||||
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
|
||||
m0_write : out std_logic; -- write
|
||||
m0_read : out std_logic; -- read
|
||||
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
|
||||
m0_debugaccess : out std_logic -- debugaccess
|
||||
);
|
||||
end component pb_cpu_0;
|
||||
|
||||
@@ -0,0 +1,214 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for pb_cpu_0</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">pb_cpu_0</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:49</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/>All Components
|
||||
<br/>  
|
||||
<a href="#module_altera_avalon_mm_bridge_inst"><b>altera_avalon_mm_bridge_inst</b>
|
||||
</a> altera_avalon_mm_bridge 20.1.0</span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
<td class="mastermodule" colspan="1">
|
||||
<a href="#module_altera_avalon_mm_bridge_inst"><b>altera_avalon_mm_bridge_inst</b>
|
||||
</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="masterlr"> m0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_altera_avalon_mm_bridge_inst"><b>altera_avalon_mm_bridge_inst</b>
|
||||
</a>
|
||||
</td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">s0 </td>
|
||||
<td class="empty"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_avalon_mm_bridge_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_avalon_mm_bridge_inst</h2>altera_avalon_mm_bridge v20.1.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">DATA_WIDTH</td>
|
||||
<td class="parametervalue">32</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">SYMBOL_WIDTH</td>
|
||||
<td class="parametervalue">8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">ADDRESS_WIDTH</td>
|
||||
<td class="parametervalue">20</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">USE_AUTO_ADDRESS_WIDTH</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">AUTO_ADDRESS_WIDTH</td>
|
||||
<td class="parametervalue">17</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">ADDRESS_UNITS</td>
|
||||
<td class="parametervalue">SYMBOLS</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MAX_BURST_SIZE</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MAX_PENDING_RESPONSES</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">MAX_PENDING_WRITES</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">LINEWRAPBURSTS</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PIPELINE_COMMAND</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">PIPELINE_RESPONSE</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">USE_RESPONSE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">SYNC_RESET</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">USE_WRITERESPONSE</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.01 seconds</td>
|
||||
<td class="r">rendering took 0.11 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,112 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">pb_cpu_0</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>pb_cpu_0</className>
|
||||
<version>1.0</version>
|
||||
<name>pb_cpu_0</name>
|
||||
<uniqueName>pb_cpu_0</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_avalon_mm_bridge_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>ADDRESS_UNITS</name>
|
||||
<value>SYMBOLS</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>ADDRESS_WIDTH</name>
|
||||
<value>20</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>AUTO_ADDRESS_WIDTH</name>
|
||||
<value>17</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>BURSTCOUNT_WIDTH</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>DATA_WIDTH</name>
|
||||
<value>32</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>HDL_ADDR_WIDTH</name>
|
||||
<value>17</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>LINEWRAPBURSTS</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>M0_WAITREQUEST_ALLOWANCE</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>MAX_BURST_SIZE</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>MAX_PENDING_RESPONSES</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>MAX_PENDING_WRITES</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>PIPELINE_COMMAND</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>PIPELINE_RESPONSE</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>S0_WAITREQUEST_ALLOWANCE</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>SYMBOL_WIDTH</name>
|
||||
<value>8</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>SYNC_RESET</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>SYSINFO_ADDR_WIDTH</name>
|
||||
<value>17</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>USE_AUTO_ADDRESS_WIDTH</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>USE_RESPONSE</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>USE_WRITERESPONSE</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_avalon_mm_bridge</className>
|
||||
<version>20.1.0</version>
|
||||
<name>altera_avalon_mm_bridge_inst</name>
|
||||
<uniqueName>pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>pb_cpu_0.altera_avalon_mm_bridge_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,43 @@
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_avalon_mm_bridge"
|
||||
set_global_assignment -library "pb_cpu_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "pb_cpu_0.sopcinfo"]
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name SLD_INFO "QSYS_NAME pb_cpu_0 HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "pb_cpu_0" -name MISC_FILE [file join $::quartus(qip_path) "pb_cpu_0.cmp"]
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "pb_cpu_0" -name MISC_FILE [file join $::quartus(qip_path) "../pb_cpu_0.ip"]
|
||||
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_NAME "cGJfY3B1XzBfYWx0ZXJhX2F2YWxvbl9tbV9icmlkZ2VfMjAxMF90ZXg1YTRp"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_DISPLAY_NAME "QXZhbG9uIE1lbW9yeSBNYXBwZWQgUGlwZWxpbmUgQnJpZGdlIElQ"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_VERSION "MjAuMS4w"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_DESCRIPTION "SW5zZXJ0cyBhIHJlZ2lzdGVyIHN0YWdlIGluIHRoZSBBdmFsb24gTWVtb3J5IE1hcHBlZCBjb21tYW5kIGFuZCByZXNwb25zZSBwYXRocy4gQWNjZXB0cyBjb21tYW5kcyBvbiBpdHMgQXZhbG9uIE1lbW9yeSBNYXBwZWQgc2xhdmUgcG9ydCBhbmQgcHJvcGFnYXRlcyB0aGVtIHRvIGl0cyBBdmFsb24gTWVtb3J5IE1hcHBlZCBtYXN0ZXIgcG9ydC4="
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0JyaWRnZXMgYW5kIEFkYXB0b3JzL01lbW9yeSBNYXBwZWQ="
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3pjbjE1MTM5ODcyODI5MzUuaHRtbCNtd2gxNDA5OTU4ODI4NzMy"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvZGFtL3d3dy9wcm9ncmFtbWFibGUvdXMvZW4vcGRmcy9saXRlcmF0dXJlL3VnL3VnLXFwcC1wbGF0Zm9ybS1kZXNpZ25lci5wZGY="
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL2hjbzE0MTY4MzYxNDU1NTUuaHRtbCNoY28xNDE2ODM2NjUzMjIx"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_COMPONENT_NAME "cGJfY3B1XzA="
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "pb_cpu_0" -library "pb_cpu_0" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "altera_avalon_mm_bridge_2010" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_mm_bridge_2010/synth/pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i.v"]
|
||||
set_global_assignment -library "altera_avalon_mm_bridge_2010" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_mm_bridge_2010/synth/altera_merlin_waitrequest_adapter.v"]
|
||||
set_global_assignment -library "altera_avalon_mm_bridge_2010" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_mm_bridge_2010/synth/altera_avalon_sc_fifo.v"]
|
||||
set_global_assignment -library "pb_cpu_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/pb_cpu_0.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_TOOL_NAME "altera_avalon_mm_bridge"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_TOOL_VERSION "20.1.0"
|
||||
set_global_assignment -entity "pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i" -library "altera_avalon_mm_bridge_2010" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,285 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:50"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5ED065BB32AE6SR0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_S0_CPU_INFO_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_M0_ADDRESS_MAP"
|
||||
type="AddressMap"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_M0_ADDRESS_WIDTH"
|
||||
type="AddressWidthType"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="reset" kind="reset" start="0">
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="synchronousEdges" value="DEASSERT" />
|
||||
<port name="reset" direction="input" role="reset" width="1" />
|
||||
</interface>
|
||||
<interface name="s0" kind="avalon" start="0">
|
||||
<property name="addressAlignment" value="DYNAMIC" />
|
||||
<property name="addressGroup" value="0" />
|
||||
<property name="addressSpan" value="131072" />
|
||||
<property name="addressUnits" value="SYMBOLS" />
|
||||
<property name="alwaysBurstMaxBurst" value="false" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bitsPerSymbol" value="8" />
|
||||
<property name="bridgedAddressOffset" value="0" />
|
||||
<property name="bridgesToMaster" value="pb_cpu_0.m0" />
|
||||
<property name="burstOnBurstBoundariesOnly" value="false" />
|
||||
<property name="burstcountUnits" value="WORDS" />
|
||||
<property name="constantBurstBehavior" value="false" />
|
||||
<property name="explicitAddressSpan" value="0" />
|
||||
<property name="holdTime" value="0" />
|
||||
<property name="interleaveBursts" value="false" />
|
||||
<property name="isBigEndian" value="false" />
|
||||
<property name="isFlash" value="false" />
|
||||
<property name="isMemoryDevice" value="false" />
|
||||
<property name="isNonVolatileStorage" value="false" />
|
||||
<property name="linewrapBursts" value="false" />
|
||||
<property name="maximumPendingReadTransactions" value="1" />
|
||||
<property name="maximumPendingWriteTransactions" value="0" />
|
||||
<property name="minimumReadLatency" value="1" />
|
||||
<property name="minimumResponseLatency" value="1" />
|
||||
<property name="minimumUninterruptedRunLength" value="1" />
|
||||
<property name="prSafe" value="false" />
|
||||
<property name="printableDevice" value="false" />
|
||||
<property name="readLatency" value="0" />
|
||||
<property name="readWaitStates" value="0" />
|
||||
<property name="readWaitTime" value="0" />
|
||||
<property name="registerIncomingSignals" value="false" />
|
||||
<property name="registerOutgoingSignals" value="false" />
|
||||
<property name="setupTime" value="0" />
|
||||
<property name="timingUnits" value="Cycles" />
|
||||
<property name="transparentBridge" value="false" />
|
||||
<property name="waitrequestAllowance" value="0" />
|
||||
<property name="waitrequestTimeout" value="1024" />
|
||||
<property name="wellBehavedWaitrequest" value="false" />
|
||||
<property name="writeLatency" value="0" />
|
||||
<property name="writeWaitStates" value="0" />
|
||||
<property name="writeWaitTime" value="0" />
|
||||
<property name="dfhFeatureGuid" value="0" />
|
||||
<property name="dfhGroupId" value="0" />
|
||||
<property name="dfhParameterId" value="" />
|
||||
<property name="dfhParameterName" value="" />
|
||||
<property name="dfhParameterVersion" value="" />
|
||||
<property name="dfhParameterData" value="" />
|
||||
<property name="dfhParameterDataLength" value="" />
|
||||
<property name="dfhFeatureMajorVersion" value="0" />
|
||||
<property name="dfhFeatureMinorVersion" value="0" />
|
||||
<property name="dfhFeatureId" value="35" />
|
||||
<property name="dfhFeatureType" value="3" />
|
||||
<port name="s0_waitrequest" direction="output" role="waitrequest" width="1" />
|
||||
<port name="s0_readdata" direction="output" role="readdata" width="32" />
|
||||
<port
|
||||
name="s0_readdatavalid"
|
||||
direction="output"
|
||||
role="readdatavalid"
|
||||
width="1" />
|
||||
<port name="s0_burstcount" direction="input" role="burstcount" width="1" />
|
||||
<port name="s0_writedata" direction="input" role="writedata" width="32" />
|
||||
<port name="s0_address" direction="input" role="address" width="17" />
|
||||
<port name="s0_write" direction="input" role="write" width="1" />
|
||||
<port name="s0_read" direction="input" role="read" width="1" />
|
||||
<port name="s0_byteenable" direction="input" role="byteenable" width="4" />
|
||||
<port name="s0_debugaccess" direction="input" role="debugaccess" width="1" />
|
||||
</interface>
|
||||
<interface name="m0" kind="avalon" start="1">
|
||||
<property name="adaptsTo" value="" />
|
||||
<property name="addressGroup" value="0" />
|
||||
<property name="addressUnits" value="SYMBOLS" />
|
||||
<property name="alwaysBurstMaxBurst" value="false" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bitsPerSymbol" value="8" />
|
||||
<property name="burstOnBurstBoundariesOnly" value="false" />
|
||||
<property name="burstcountUnits" value="WORDS" />
|
||||
<property name="constantBurstBehavior" value="false" />
|
||||
<property name="dBSBigEndian" value="false" />
|
||||
<property name="doStreamReads" value="false" />
|
||||
<property name="doStreamWrites" value="false" />
|
||||
<property name="holdTime" value="0" />
|
||||
<property name="interleaveBursts" value="false" />
|
||||
<property name="isAsynchronous" value="false" />
|
||||
<property name="isBigEndian" value="false" />
|
||||
<property name="isReadable" value="false" />
|
||||
<property name="isWriteable" value="false" />
|
||||
<property name="linewrapBursts" value="false" />
|
||||
<property name="maxAddressWidth" value="32" />
|
||||
<property name="maximumPendingReadTransactions" value="0" />
|
||||
<property name="maximumPendingWriteTransactions" value="0" />
|
||||
<property name="minimumReadLatency" value="1" />
|
||||
<property name="minimumResponseLatency" value="1" />
|
||||
<property name="prSafe" value="false" />
|
||||
<property name="readLatency" value="0" />
|
||||
<property name="readWaitTime" value="1" />
|
||||
<property name="registerIncomingSignals" value="false" />
|
||||
<property name="registerOutgoingSignals" value="false" />
|
||||
<property name="setupTime" value="0" />
|
||||
<property name="timingUnits" value="Cycles" />
|
||||
<property name="waitrequestAllowance" value="0" />
|
||||
<property name="waitrequestTimeout" value="1024" />
|
||||
<property name="writeWaitTime" value="0" />
|
||||
<property name="enableConcurrentSubordinateAccess" value="0" />
|
||||
<property name="optimizedReadsWithBE" value="0" />
|
||||
<port name="m0_waitrequest" direction="input" role="waitrequest" width="1" />
|
||||
<port name="m0_readdata" direction="input" role="readdata" width="32" />
|
||||
<port
|
||||
name="m0_readdatavalid"
|
||||
direction="input"
|
||||
role="readdatavalid"
|
||||
width="1" />
|
||||
<port name="m0_burstcount" direction="output" role="burstcount" width="1" />
|
||||
<port name="m0_writedata" direction="output" role="writedata" width="32" />
|
||||
<port name="m0_address" direction="output" role="address" width="17" />
|
||||
<port name="m0_write" direction="output" role="write" width="1" />
|
||||
<port name="m0_read" direction="output" role="read" width="1" />
|
||||
<port name="m0_byteenable" direction="output" role="byteenable" width="4" />
|
||||
<port name="m0_debugaccess" direction="output" role="debugaccess" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="pb_cpu_0" version="1.0" name="pb_cpu_0">
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_M0_ADDRESS_MAP" value="" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_M0_ADDRESS_WIDTH" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<parameter name="AUTO_S0_CPU_INFO_ID" value="" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/synth/pb_cpu_0.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/synth/pb_cpu_0.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Info" culprit="pb_cpu_0">"Generating: pb_cpu_0"</message>
|
||||
<message level="Info" culprit="pb_cpu_0">"Generating: pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
kind="altera_avalon_mm_bridge"
|
||||
version="20.1.0"
|
||||
name="pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i">
|
||||
<parameter name="MAX_BURST_SIZE" value="1" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/altera_avalon_mm_bridge_2010/synth/pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i.v"
|
||||
attributes="" />
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/altera_avalon_mm_bridge_2010/synth/altera_merlin_waitrequest_adapter.v"
|
||||
attributes="" />
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/altera_avalon_mm_bridge_2010/synth/altera_avalon_sc_fifo.v"
|
||||
attributes="" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/altera_avalon_mm_bridge_2010/synth/pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i.v"
|
||||
attributes="" />
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/altera_avalon_mm_bridge_2010/synth/altera_merlin_waitrequest_adapter.v"
|
||||
attributes="" />
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0/altera_avalon_mm_bridge_2010/synth/altera_avalon_sc_fifo.v"
|
||||
attributes="" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="pb_cpu_0" as="altera_avalon_mm_bridge_inst" />
|
||||
<messages>
|
||||
<message level="Info" culprit="pb_cpu_0">"Generating: pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,37 @@
|
||||
module pb_cpu_0 #(
|
||||
parameter DATA_WIDTH = 32,
|
||||
parameter SYMBOL_WIDTH = 8,
|
||||
parameter HDL_ADDR_WIDTH = 17,
|
||||
parameter BURSTCOUNT_WIDTH = 1,
|
||||
parameter PIPELINE_COMMAND = 1,
|
||||
parameter PIPELINE_RESPONSE = 1,
|
||||
parameter SYNC_RESET = 0,
|
||||
parameter USE_WRITERESPONSE = 0,
|
||||
parameter S0_WAITREQUEST_ALLOWANCE = 0,
|
||||
parameter M0_WAITREQUEST_ALLOWANCE = 0
|
||||
) (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset, // reset.reset
|
||||
output wire s0_waitrequest, // s0.waitrequest, Wait request to Avalon Memory Mapped Host, indicates agent is not ready
|
||||
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata, Read Data output from Avalon Memory Mapped Agent
|
||||
output wire s0_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
|
||||
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount, Indicates number of burst transfers in each burst
|
||||
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
|
||||
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address, Address output from Avalon Memory Mapped Host
|
||||
input wire s0_write, // .write, Write command from Avalon Memory Mapped Host
|
||||
input wire s0_read, // .read, Read command from Avalon Memory Mapped Host
|
||||
input wire [3:0] s0_byteenable, // .byteenable, Indicates valid read/write data location
|
||||
input wire s0_debugaccess, // .debugaccess
|
||||
input wire m0_waitrequest, // m0.waitrequest, Wait request from Avalon Memory Mapped Agent, indicates agent is not ready
|
||||
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata, Read Data input to Avalon Memory Mapped Host
|
||||
input wire m0_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
|
||||
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount, Indicates number of burst transfers in each burst
|
||||
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
|
||||
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address, Address output from Avalon Memory Mapped Host
|
||||
output wire m0_write, // .write, Write command from Avalon Memory Mapped Host
|
||||
output wire m0_read, // .read, Read command from Avalon Memory Mapped Host
|
||||
output wire [3:0] m0_byteenable, // .byteenable, Indicates valid read/write data location
|
||||
output wire m0_debugaccess // .debugaccess
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: pb_cpu_0: "Transforming system: pb_cpu_0"
|
||||
Info: pb_cpu_0: "Naming system components in system: pb_cpu_0"
|
||||
Info: pb_cpu_0: "Processing generation queue"
|
||||
Info: pb_cpu_0: "Generating: pb_cpu_0"
|
||||
Info: pb_cpu_0: "Generating: pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i"
|
||||
Info: pb_cpu_0: Done "pb_cpu_0" with 2 modules, 4 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,10 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: pb_cpu_0: "Transforming system: pb_cpu_0"
|
||||
Info: pb_cpu_0: "Naming system components in system: pb_cpu_0"
|
||||
Info: pb_cpu_0: "Processing generation queue"
|
||||
Info: pb_cpu_0: "Generating: pb_cpu_0"
|
||||
Info: pb_cpu_0: "Generating: pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i"
|
||||
Info: pb_cpu_0: Done "pb_cpu_0" with 2 modules, 4 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,36 @@
|
||||
pb_cpu_0 #(
|
||||
.DATA_WIDTH (INTEGER_VALUE_FOR_DATA_WIDTH),
|
||||
.SYMBOL_WIDTH (INTEGER_VALUE_FOR_SYMBOL_WIDTH),
|
||||
.HDL_ADDR_WIDTH (INTEGER_VALUE_FOR_HDL_ADDR_WIDTH),
|
||||
.BURSTCOUNT_WIDTH (INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH),
|
||||
.PIPELINE_COMMAND (INTEGER_VALUE_FOR_PIPELINE_COMMAND),
|
||||
.PIPELINE_RESPONSE (INTEGER_VALUE_FOR_PIPELINE_RESPONSE),
|
||||
.SYNC_RESET (INTEGER_VALUE_FOR_SYNC_RESET),
|
||||
.USE_WRITERESPONSE (INTEGER_VALUE_FOR_USE_WRITERESPONSE),
|
||||
.S0_WAITREQUEST_ALLOWANCE (INTEGER_VALUE_FOR_S0_WAITREQUEST_ALLOWANCE),
|
||||
.M0_WAITREQUEST_ALLOWANCE (INTEGER_VALUE_FOR_M0_WAITREQUEST_ALLOWANCE)
|
||||
) u0 (
|
||||
.clk (_connected_to_clk_), // input, width = 1, clk.clk
|
||||
.reset (_connected_to_reset_), // input, width = 1, reset.reset
|
||||
.s0_waitrequest (_connected_to_s0_waitrequest_), // output, width = 1, s0.waitrequest
|
||||
.s0_readdata (_connected_to_s0_readdata_), // output, width = DATA_WIDTH, .readdata
|
||||
.s0_readdatavalid (_connected_to_s0_readdatavalid_), // output, width = 1, .readdatavalid
|
||||
.s0_burstcount (_connected_to_s0_burstcount_), // input, width = BURSTCOUNT_WIDTH, .burstcount
|
||||
.s0_writedata (_connected_to_s0_writedata_), // input, width = DATA_WIDTH, .writedata
|
||||
.s0_address (_connected_to_s0_address_), // input, width = HDL_ADDR_WIDTH, .address
|
||||
.s0_write (_connected_to_s0_write_), // input, width = 1, .write
|
||||
.s0_read (_connected_to_s0_read_), // input, width = 1, .read
|
||||
.s0_byteenable (_connected_to_s0_byteenable_), // input, width = 4, .byteenable
|
||||
.s0_debugaccess (_connected_to_s0_debugaccess_), // input, width = 1, .debugaccess
|
||||
.m0_waitrequest (_connected_to_m0_waitrequest_), // input, width = 1, m0.waitrequest
|
||||
.m0_readdata (_connected_to_m0_readdata_), // input, width = DATA_WIDTH, .readdata
|
||||
.m0_readdatavalid (_connected_to_m0_readdatavalid_), // input, width = 1, .readdatavalid
|
||||
.m0_burstcount (_connected_to_m0_burstcount_), // output, width = BURSTCOUNT_WIDTH, .burstcount
|
||||
.m0_writedata (_connected_to_m0_writedata_), // output, width = DATA_WIDTH, .writedata
|
||||
.m0_address (_connected_to_m0_address_), // output, width = HDL_ADDR_WIDTH, .address
|
||||
.m0_write (_connected_to_m0_write_), // output, width = 1, .write
|
||||
.m0_read (_connected_to_m0_read_), // output, width = 1, .read
|
||||
.m0_byteenable (_connected_to_m0_byteenable_), // output, width = 4, .byteenable
|
||||
.m0_debugaccess (_connected_to_m0_debugaccess_) // output, width = 1, .debugaccess
|
||||
);
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
component pb_cpu_0 is
|
||||
generic (
|
||||
DATA_WIDTH : integer := 32;
|
||||
SYMBOL_WIDTH : integer := 8;
|
||||
HDL_ADDR_WIDTH : integer := 17;
|
||||
BURSTCOUNT_WIDTH : integer := 1;
|
||||
PIPELINE_COMMAND : integer := 1;
|
||||
PIPELINE_RESPONSE : integer := 1;
|
||||
SYNC_RESET : integer := 0;
|
||||
USE_WRITERESPONSE : integer := 0;
|
||||
S0_WAITREQUEST_ALLOWANCE : integer := 0;
|
||||
M0_WAITREQUEST_ALLOWANCE : integer := 0
|
||||
);
|
||||
port (
|
||||
clk : in std_logic := 'X'; -- clk
|
||||
reset : in std_logic := 'X'; -- reset
|
||||
s0_waitrequest : out std_logic; -- waitrequest
|
||||
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
|
||||
s0_readdatavalid : out std_logic; -- readdatavalid
|
||||
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
|
||||
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
|
||||
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
|
||||
s0_write : in std_logic := 'X'; -- write
|
||||
s0_read : in std_logic := 'X'; -- read
|
||||
s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
|
||||
s0_debugaccess : in std_logic := 'X'; -- debugaccess
|
||||
m0_waitrequest : in std_logic := 'X'; -- waitrequest
|
||||
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
|
||||
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
|
||||
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
|
||||
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
|
||||
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
|
||||
m0_write : out std_logic; -- write
|
||||
m0_read : out std_logic; -- read
|
||||
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
|
||||
m0_debugaccess : out std_logic -- debugaccess
|
||||
);
|
||||
end component pb_cpu_0;
|
||||
|
||||
u0 : component pb_cpu_0
|
||||
generic map (
|
||||
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
|
||||
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
|
||||
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
|
||||
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
|
||||
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
|
||||
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE,
|
||||
SYNC_RESET => INTEGER_VALUE_FOR_SYNC_RESET,
|
||||
USE_WRITERESPONSE => INTEGER_VALUE_FOR_USE_WRITERESPONSE,
|
||||
S0_WAITREQUEST_ALLOWANCE => INTEGER_VALUE_FOR_S0_WAITREQUEST_ALLOWANCE,
|
||||
M0_WAITREQUEST_ALLOWANCE => INTEGER_VALUE_FOR_M0_WAITREQUEST_ALLOWANCE
|
||||
)
|
||||
port map (
|
||||
clk => CONNECTED_TO_clk, -- clk.clk
|
||||
reset => CONNECTED_TO_reset, -- reset.reset
|
||||
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
|
||||
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
|
||||
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
|
||||
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
|
||||
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
|
||||
s0_address => CONNECTED_TO_s0_address, -- .address
|
||||
s0_write => CONNECTED_TO_s0_write, -- .write
|
||||
s0_read => CONNECTED_TO_s0_read, -- .read
|
||||
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
|
||||
s0_debugaccess => CONNECTED_TO_s0_debugaccess, -- .debugaccess
|
||||
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
|
||||
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
|
||||
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
|
||||
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
|
||||
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
|
||||
m0_address => CONNECTED_TO_m0_address, -- .address
|
||||
m0_write => CONNECTED_TO_m0_write, -- .write
|
||||
m0_read => CONNECTED_TO_m0_read, -- .read
|
||||
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
|
||||
m0_debugaccess => CONNECTED_TO_m0_debugaccess -- .debugaccess
|
||||
);
|
||||
|
||||
@@ -0,0 +1,82 @@
|
||||
// pb_cpu_0.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pb_cpu_0 #(
|
||||
parameter DATA_WIDTH = 32,
|
||||
parameter SYMBOL_WIDTH = 8,
|
||||
parameter HDL_ADDR_WIDTH = 17,
|
||||
parameter BURSTCOUNT_WIDTH = 1,
|
||||
parameter PIPELINE_COMMAND = 1,
|
||||
parameter PIPELINE_RESPONSE = 1,
|
||||
parameter SYNC_RESET = 0,
|
||||
parameter USE_WRITERESPONSE = 0,
|
||||
parameter S0_WAITREQUEST_ALLOWANCE = 0,
|
||||
parameter M0_WAITREQUEST_ALLOWANCE = 0
|
||||
) (
|
||||
input wire clk, // clk.clk
|
||||
input wire reset, // reset.reset
|
||||
output wire s0_waitrequest, // s0.waitrequest, Wait request to Avalon Memory Mapped Host, indicates agent is not ready
|
||||
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata, Read Data output from Avalon Memory Mapped Agent
|
||||
output wire s0_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
|
||||
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount, Indicates number of burst transfers in each burst
|
||||
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
|
||||
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address, Address output from Avalon Memory Mapped Host
|
||||
input wire s0_write, // .write, Write command from Avalon Memory Mapped Host
|
||||
input wire s0_read, // .read, Read command from Avalon Memory Mapped Host
|
||||
input wire [3:0] s0_byteenable, // .byteenable, Indicates valid read/write data location
|
||||
input wire s0_debugaccess, // .debugaccess
|
||||
input wire m0_waitrequest, // m0.waitrequest, Wait request from Avalon Memory Mapped Agent, indicates agent is not ready
|
||||
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata, Read Data input to Avalon Memory Mapped Host
|
||||
input wire m0_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
|
||||
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount, Indicates number of burst transfers in each burst
|
||||
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
|
||||
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address, Address output from Avalon Memory Mapped Host
|
||||
output wire m0_write, // .write, Write command from Avalon Memory Mapped Host
|
||||
output wire m0_read, // .read, Read command from Avalon Memory Mapped Host
|
||||
output wire [3:0] m0_byteenable, // .byteenable, Indicates valid read/write data location
|
||||
output wire m0_debugaccess // .debugaccess
|
||||
);
|
||||
|
||||
pb_cpu_0_altera_avalon_mm_bridge_2010_tex5a4i #(
|
||||
.DATA_WIDTH (DATA_WIDTH),
|
||||
.SYMBOL_WIDTH (SYMBOL_WIDTH),
|
||||
.HDL_ADDR_WIDTH (HDL_ADDR_WIDTH),
|
||||
.BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
|
||||
.PIPELINE_COMMAND (PIPELINE_COMMAND),
|
||||
.PIPELINE_RESPONSE (PIPELINE_RESPONSE),
|
||||
.SYNC_RESET (SYNC_RESET),
|
||||
.USE_WRITERESPONSE (USE_WRITERESPONSE),
|
||||
.S0_WAITREQUEST_ALLOWANCE (S0_WAITREQUEST_ALLOWANCE),
|
||||
.M0_WAITREQUEST_ALLOWANCE (M0_WAITREQUEST_ALLOWANCE)
|
||||
) altera_avalon_mm_bridge_inst (
|
||||
.clk (clk), // input, width = 1, clk.clk
|
||||
.reset (reset), // input, width = 1, reset.reset
|
||||
.s0_waitrequest (s0_waitrequest), // output, width = 1, s0.waitrequest
|
||||
.s0_readdata (s0_readdata), // output, width = DATA_WIDTH, .readdata
|
||||
.s0_readdatavalid (s0_readdatavalid), // output, width = 1, .readdatavalid
|
||||
.s0_burstcount (s0_burstcount), // input, width = BURSTCOUNT_WIDTH, .burstcount
|
||||
.s0_writedata (s0_writedata), // input, width = DATA_WIDTH, .writedata
|
||||
.s0_address (s0_address), // input, width = HDL_ADDR_WIDTH, .address
|
||||
.s0_write (s0_write), // input, width = 1, .write
|
||||
.s0_read (s0_read), // input, width = 1, .read
|
||||
.s0_byteenable (s0_byteenable), // input, width = 4, .byteenable
|
||||
.s0_debugaccess (s0_debugaccess), // input, width = 1, .debugaccess
|
||||
.m0_waitrequest (m0_waitrequest), // input, width = 1, m0.waitrequest
|
||||
.m0_readdata (m0_readdata), // input, width = DATA_WIDTH, .readdata
|
||||
.m0_readdatavalid (m0_readdatavalid), // input, width = 1, .readdatavalid
|
||||
.m0_burstcount (m0_burstcount), // output, width = BURSTCOUNT_WIDTH, .burstcount
|
||||
.m0_writedata (m0_writedata), // output, width = DATA_WIDTH, .writedata
|
||||
.m0_address (m0_address), // output, width = HDL_ADDR_WIDTH, .address
|
||||
.m0_write (m0_write), // output, width = 1, .write
|
||||
.m0_read (m0_read), // output, width = 1, .read
|
||||
.m0_byteenable (m0_byteenable), // output, width = 4, .byteenable
|
||||
.m0_debugaccess (m0_debugaccess), // output, width = 1, .debugaccess
|
||||
.s0_response (), // (terminated),
|
||||
.s0_writeresponsevalid (), // (terminated),
|
||||
.m0_response (2'b00), // (terminated),
|
||||
.m0_writeresponsevalid (1'b0) // (terminated),
|
||||
);
|
||||
|
||||
endmodule
|
||||
+365
@@ -0,0 +1,365 @@
|
||||
<?xml version="1.0" ?>
|
||||
<!--Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.-->
|
||||
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>periph_clk</ipxact:library>
|
||||
<ipxact:name>altera_clock_bridge_inst</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
<ipxact:busInterfaces>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="clock" version="25.1"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="25.1"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>clk</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:slave></ipxact:slave>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="clockRate" type="longint">
|
||||
<ipxact:name>clockRate</ipxact:name>
|
||||
<ipxact:displayName>Clock rate</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="externallyDriven" type="bit">
|
||||
<ipxact:name>externallyDriven</ipxact:name>
|
||||
<ipxact:displayName>Externally driven</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="ptfSchematicName" type="string">
|
||||
<ipxact:name>ptfSchematicName</ipxact:name>
|
||||
<ipxact:displayName>PTF schematic name</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="clock" version="25.1"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="25.1"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>clk</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:master></ipxact:master>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedDirectClock" type="string">
|
||||
<ipxact:name>associatedDirectClock</ipxact:name>
|
||||
<ipxact:displayName>Associated direct clock</ipxact:displayName>
|
||||
<ipxact:value>in_clk</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="clockRate" type="longint">
|
||||
<ipxact:name>clockRate</ipxact:name>
|
||||
<ipxact:displayName>Clock rate</ipxact:displayName>
|
||||
<ipxact:value>100000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="clockRateKnown" type="bit">
|
||||
<ipxact:name>clockRateKnown</ipxact:name>
|
||||
<ipxact:displayName>Clock rate known</ipxact:displayName>
|
||||
<ipxact:value>true</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="externallyDriven" type="bit">
|
||||
<ipxact:name>externallyDriven</ipxact:name>
|
||||
<ipxact:displayName>Externally driven</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="ptfSchematicName" type="string">
|
||||
<ipxact:name>ptfSchematicName</ipxact:name>
|
||||
<ipxact:displayName>PTF schematic name</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
</ipxact:busInterfaces>
|
||||
<ipxact:model>
|
||||
<ipxact:views>
|
||||
<ipxact:view>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
|
||||
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
|
||||
</ipxact:view>
|
||||
</ipxact:views>
|
||||
<ipxact:instantiations>
|
||||
<ipxact:componentInstantiation>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:moduleName>altera_clock_bridge</ipxact:moduleName>
|
||||
<ipxact:fileSetRef>
|
||||
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
|
||||
</ipxact:fileSetRef>
|
||||
</ipxact:componentInstantiation>
|
||||
</ipxact:instantiations>
|
||||
<ipxact:ports>
|
||||
<ipxact:port>
|
||||
<ipxact:name>in_clk</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>in</ipxact:direction>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
<ipxact:port>
|
||||
<ipxact:name>out_clk</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>out</ipxact:direction>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
</ipxact:ports>
|
||||
</ipxact:model>
|
||||
<ipxact:vendorExtensions>
|
||||
<altera:entity_info>
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>periph_clk</ipxact:library>
|
||||
<ipxact:name>altera_clock_bridge</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
</altera:entity_info>
|
||||
<altera:altera_module_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="DERIVED_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>DERIVED_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Derived clock rate</ipxact:displayName>
|
||||
<ipxact:value>100000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="EXPLICIT_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>EXPLICIT_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Explicit clock rate</ipxact:displayName>
|
||||
<ipxact:value>100000000</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="NUM_CLOCK_OUTPUTS" type="int">
|
||||
<ipxact:name>NUM_CLOCK_OUTPUTS</ipxact:name>
|
||||
<ipxact:displayName>Number of Clock Outputs</ipxact:displayName>
|
||||
<ipxact:value>1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_module_parameters>
|
||||
<altera:altera_system_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="board" type="string">
|
||||
<ipxact:name>board</ipxact:name>
|
||||
<ipxact:displayName>Board</ipxact:displayName>
|
||||
<ipxact:value>default</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="device" type="string">
|
||||
<ipxact:name>device</ipxact:name>
|
||||
<ipxact:displayName>Device</ipxact:displayName>
|
||||
<ipxact:value>A5ED065BB32AE6SR0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceFamily" type="string">
|
||||
<ipxact:name>deviceFamily</ipxact:name>
|
||||
<ipxact:displayName>Device family</ipxact:displayName>
|
||||
<ipxact:value>Agilex 5</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
|
||||
<ipxact:name>deviceSpeedGrade</ipxact:name>
|
||||
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
|
||||
<ipxact:value>6</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="generationId" type="int">
|
||||
<ipxact:name>generationId</ipxact:name>
|
||||
<ipxact:displayName>Generation Id</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="bonusData" type="string">
|
||||
<ipxact:name>bonusData</ipxact:name>
|
||||
<ipxact:displayName>bonusData</ipxact:displayName>
|
||||
<ipxact:value>bonusData
|
||||
{
|
||||
element altera_clock_bridge_inst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
|
||||
<ipxact:name>hideFromIPCatalog</ipxact:name>
|
||||
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
|
||||
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
|
||||
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
|
||||
<ipxact:value><boundaryDefinition>
|
||||
<interfaces>
|
||||
<interface>
|
||||
<name>in_clk</name>
|
||||
<type>clock</type>
|
||||
<isStart>false</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>in_clk</name>
|
||||
<role>clk</role>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>clockRate</key>
|
||||
<value>0</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>externallyDriven</key>
|
||||
<value>false</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>ptfSchematicName</key>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface>
|
||||
<name>out_clk</name>
|
||||
<type>clock</type>
|
||||
<isStart>true</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>out_clk</name>
|
||||
<role>clk</role>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedDirectClock</key>
|
||||
<value>in_clk</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>clockRate</key>
|
||||
<value>100000000</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>clockRateKnown</key>
|
||||
<value>true</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>externallyDriven</key>
|
||||
<value>false</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>ptfSchematicName</key>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</boundaryDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="systemInfos" type="string">
|
||||
<ipxact:name>systemInfos</ipxact:name>
|
||||
<ipxact:displayName>systemInfos</ipxact:displayName>
|
||||
<ipxact:value><systemInfosDefinition>
|
||||
<connPtSystemInfos>
|
||||
<entry>
|
||||
<key>in_clk</key>
|
||||
<value>
|
||||
<connectionPointName>in_clk</connectionPointName>
|
||||
<suppliedSystemInfos>
|
||||
<entry>
|
||||
<key>CLOCK_RATE</key>
|
||||
<value>100000000</value>
|
||||
</entry>
|
||||
</suppliedSystemInfos>
|
||||
<consumedSystemInfos/>
|
||||
</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>out_clk</key>
|
||||
<value>
|
||||
<connectionPointName>out_clk</connectionPointName>
|
||||
<suppliedSystemInfos/>
|
||||
<consumedSystemInfos>
|
||||
<entry>
|
||||
<key>CLOCK_RATE</key>
|
||||
<value>100000000</value>
|
||||
</entry>
|
||||
</consumedSystemInfos>
|
||||
</value>
|
||||
</entry>
|
||||
</connPtSystemInfos>
|
||||
</systemInfosDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="dflBitArray" type="string">
|
||||
<ipxact:name>dflBitArray</ipxact:name>
|
||||
<ipxact:displayName>dflBitArray</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="cpuInfo" type="string">
|
||||
<ipxact:name>cpuInfo</ipxact:name>
|
||||
<ipxact:displayName>cpuInfo</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_system_parameters>
|
||||
<altera:altera_interface_boundary>
|
||||
<altera:interface_mapping altera:name="in_clk" altera:internal="altera_clock_bridge_inst.in_clk" altera:type="clock" altera:dir="end">
|
||||
<altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
<altera:interface_mapping altera:name="out_clk" altera:internal="altera_clock_bridge_inst.out_clk" altera:type="clock" altera:dir="start">
|
||||
<altera:port_mapping altera:name="out_clk" altera:internal="out_clk"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
</altera:altera_interface_boundary>
|
||||
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
||||
<altera:altera_has_errors>false</altera:altera_has_errors>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:component>
|
||||
@@ -0,0 +1,7 @@
|
||||
component periph_clk is
|
||||
port (
|
||||
in_clk : in std_logic := 'X'; -- clk
|
||||
out_clk : out std_logic -- clk
|
||||
);
|
||||
end component periph_clk;
|
||||
|
||||
@@ -0,0 +1,145 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for periph_clk</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">periph_clk</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:50</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_clock_bridge_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_clock_bridge_inst</h2>altera_clock_bridge v19.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">DERIVED_CLOCK_RATE</td>
|
||||
<td class="parametervalue">100000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EXPLICIT_CLOCK_RATE</td>
|
||||
<td class="parametervalue">100000000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_CLOCK_OUTPUTS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">periph_clk</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>periph_clk</className>
|
||||
<version>1.0</version>
|
||||
<name>periph_clk</name>
|
||||
<uniqueName>periph_clk</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_clock_bridge_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>DERIVED_CLOCK_RATE</name>
|
||||
<value>100000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>EXPLICIT_CLOCK_RATE</name>
|
||||
<value>100000000</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>NUM_CLOCK_OUTPUTS</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_clock_bridge</className>
|
||||
<version>19.2.0</version>
|
||||
<name>altera_clock_bridge_inst</name>
|
||||
<uniqueName>periph_clk_altera_clock_bridge_1920_njakcna</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>periph_clk.altera_clock_bridge_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,29 @@
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_clock_bridge"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name OCS_IP_FILE [file join $::quartus(qip_path) "../periph_clk.ip"]
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name OCS_IP_TYPE "altera_clock_bridge"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name OCS_IP_VERSION "19.2.0"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name OCS_IP_HASH "njakcna"
|
||||
set_global_assignment -library "periph_clk" -name SOPCINFO_FILE [file join $::quartus(qip_path) "periph_clk.sopcinfo"]
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name SLD_INFO "QSYS_NAME periph_clk HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "periph_clk" -name MISC_FILE [file join $::quartus(qip_path) "periph_clk.cmp"]
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "periph_clk" -name MISC_FILE [file join $::quartus(qip_path) "../periph_clk.ip"]
|
||||
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_COMPONENT_NAME "cGVyaXBoX2Nsaw=="
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "periph_clk" -library "periph_clk" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "periph_clk" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/periph_clk.v"]
|
||||
|
||||
@@ -0,0 +1,316 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="periph_clk" kind="periph_clk" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
|
||||
<!-- 2026.05.11.21:03:50 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
|
||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE">
|
||||
<type>java.lang.Long</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altera_clock_bridge_inst"
|
||||
kind="altera_clock_bridge"
|
||||
version="19.2.0"
|
||||
path="altera_clock_bridge_inst"
|
||||
className="altera_clock_bridge">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="DERIVED_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>100000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>in_clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="EXPLICIT_CLOCK_RATE">
|
||||
<type>long</type>
|
||||
<value>100000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUM_CLOCK_OUTPUTS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="in_clk" kind="clock_sink" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>java.lang.Boolean</type>
|
||||
<value>true</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>java.lang.Long</type>
|
||||
<value>100000000</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>in_clk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock_source" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedDirectClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>in_clk</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRate">
|
||||
<type>long</type>
|
||||
<value>100000000</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="clockRateKnown">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>true</isStart>
|
||||
<port>
|
||||
<name>out_clk</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_clock_bridge</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>Clock Bridge IP</displayName>
|
||||
<version>19.2.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Input</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_source</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Output</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<reportVersion>26.1 110</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
@@ -0,0 +1,104 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:50"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5ED065BB32AE6SR0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_IN_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="in_clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="in_clk" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="out_clk" kind="clock" start="1">
|
||||
<property name="associatedDirectClock" value="in_clk" />
|
||||
<property name="clockRate" value="100000000" />
|
||||
<property name="clockRateKnown" value="true" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="out_clk" direction="output" role="clk" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="periph_clk" version="1.0" name="periph_clk">
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_IN_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<parameter name="AUTO_IN_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk/synth/periph_clk.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk/synth/periph_clk.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<messages>
|
||||
<message level="Info" culprit="periph_clk">"Generating: periph_clk"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,6 @@
|
||||
module periph_clk (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: periph_clk: "Transforming system: periph_clk"
|
||||
Info: periph_clk: "Naming system components in system: periph_clk"
|
||||
Info: periph_clk: "Processing generation queue"
|
||||
Info: periph_clk: "Generating: periph_clk"
|
||||
Info: periph_clk: Done "periph_clk" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: periph_clk: "Transforming system: periph_clk"
|
||||
Info: periph_clk: "Naming system components in system: periph_clk"
|
||||
Info: periph_clk: "Processing generation queue"
|
||||
Info: periph_clk: "Generating: periph_clk"
|
||||
Info: periph_clk: Done "periph_clk" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,5 @@
|
||||
periph_clk u0 (
|
||||
.in_clk (_connected_to_in_clk_), // input, width = 1, in_clk.clk
|
||||
.out_clk (_connected_to_out_clk_) // output, width = 1, out_clk.clk
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
component periph_clk is
|
||||
port (
|
||||
in_clk : in std_logic := 'X'; -- clk
|
||||
out_clk : out std_logic -- clk
|
||||
);
|
||||
end component periph_clk;
|
||||
|
||||
u0 : component periph_clk
|
||||
port map (
|
||||
in_clk => CONNECTED_TO_in_clk, -- in_clk.clk
|
||||
out_clk => CONNECTED_TO_out_clk -- out_clk.clk
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
// periph_clk.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module periph_clk (
|
||||
input wire in_clk, // in_clk.clk, Clock Input
|
||||
output wire out_clk // out_clk.clk, Clock Output
|
||||
);
|
||||
|
||||
assign out_clk = in_clk;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,336 @@
|
||||
<?xml version="1.0" ?>
|
||||
<!--Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.-->
|
||||
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>periph_rst_in</ipxact:library>
|
||||
<ipxact:name>altera_reset_bridge_inst</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
<ipxact:busInterfaces>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>in_reset</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="reset" version="25.1"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="25.1"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>reset_n</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>in_reset_n</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:slave></ipxact:slave>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedClock" type="string">
|
||||
<ipxact:name>associatedClock</ipxact:name>
|
||||
<ipxact:displayName>Associated clock</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="synchronousEdges" type="string">
|
||||
<ipxact:name>synchronousEdges</ipxact:name>
|
||||
<ipxact:displayName>Synchronous edges</ipxact:displayName>
|
||||
<ipxact:value>NONE</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
<ipxact:busInterface>
|
||||
<ipxact:name>out_reset</ipxact:name>
|
||||
<ipxact:busType vendor="intel" library="intel" name="reset" version="25.1"></ipxact:busType>
|
||||
<ipxact:abstractionTypes>
|
||||
<ipxact:abstractionType>
|
||||
<ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="25.1"></ipxact:abstractionRef>
|
||||
<ipxact:portMaps>
|
||||
<ipxact:portMap>
|
||||
<ipxact:logicalPort>
|
||||
<ipxact:name>reset_n</ipxact:name>
|
||||
</ipxact:logicalPort>
|
||||
<ipxact:physicalPort>
|
||||
<ipxact:name>out_reset_n</ipxact:name>
|
||||
</ipxact:physicalPort>
|
||||
</ipxact:portMap>
|
||||
</ipxact:portMaps>
|
||||
</ipxact:abstractionType>
|
||||
</ipxact:abstractionTypes>
|
||||
<ipxact:master></ipxact:master>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="associatedClock" type="string">
|
||||
<ipxact:name>associatedClock</ipxact:name>
|
||||
<ipxact:displayName>Associated clock</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="associatedDirectReset" type="string">
|
||||
<ipxact:name>associatedDirectReset</ipxact:name>
|
||||
<ipxact:displayName>Associated direct reset</ipxact:displayName>
|
||||
<ipxact:value>in_reset</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="associatedResetSinks" type="string">
|
||||
<ipxact:name>associatedResetSinks</ipxact:name>
|
||||
<ipxact:displayName>Associated reset sinks</ipxact:displayName>
|
||||
<ipxact:value>in_reset</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="synchronousEdges" type="string">
|
||||
<ipxact:name>synchronousEdges</ipxact:name>
|
||||
<ipxact:displayName>Synchronous edges</ipxact:displayName>
|
||||
<ipxact:value>NONE</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</ipxact:busInterface>
|
||||
</ipxact:busInterfaces>
|
||||
<ipxact:model>
|
||||
<ipxact:views>
|
||||
<ipxact:view>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
|
||||
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
|
||||
</ipxact:view>
|
||||
</ipxact:views>
|
||||
<ipxact:instantiations>
|
||||
<ipxact:componentInstantiation>
|
||||
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
|
||||
<ipxact:moduleName>altera_reset_bridge</ipxact:moduleName>
|
||||
<ipxact:fileSetRef>
|
||||
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
|
||||
</ipxact:fileSetRef>
|
||||
</ipxact:componentInstantiation>
|
||||
</ipxact:instantiations>
|
||||
<ipxact:ports>
|
||||
<ipxact:port>
|
||||
<ipxact:name>in_reset_n</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>in</ipxact:direction>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
<ipxact:port>
|
||||
<ipxact:name>out_reset_n</ipxact:name>
|
||||
<ipxact:wire>
|
||||
<ipxact:direction>out</ipxact:direction>
|
||||
<ipxact:wireTypeDefs>
|
||||
<ipxact:wireTypeDef>
|
||||
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
|
||||
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
|
||||
</ipxact:wireTypeDef>
|
||||
</ipxact:wireTypeDefs>
|
||||
</ipxact:wire>
|
||||
</ipxact:port>
|
||||
</ipxact:ports>
|
||||
</ipxact:model>
|
||||
<ipxact:vendorExtensions>
|
||||
<altera:entity_info>
|
||||
<ipxact:vendor>Intel Corporation</ipxact:vendor>
|
||||
<ipxact:library>periph_rst_in</ipxact:library>
|
||||
<ipxact:name>altera_reset_bridge</ipxact:name>
|
||||
<ipxact:version>19.2.0</ipxact:version>
|
||||
</altera:entity_info>
|
||||
<altera:altera_module_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="ACTIVE_LOW_RESET" type="int">
|
||||
<ipxact:name>ACTIVE_LOW_RESET</ipxact:name>
|
||||
<ipxact:displayName>Active low reset</ipxact:displayName>
|
||||
<ipxact:value>1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="SYNCHRONOUS_EDGES" type="string">
|
||||
<ipxact:name>SYNCHRONOUS_EDGES</ipxact:name>
|
||||
<ipxact:displayName>Input Synchronous edges</ipxact:displayName>
|
||||
<ipxact:value>none</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="NUM_RESET_OUTPUTS" type="int">
|
||||
<ipxact:name>NUM_RESET_OUTPUTS</ipxact:name>
|
||||
<ipxact:displayName>Number of reset outputs</ipxact:displayName>
|
||||
<ipxact:value>1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="USE_RESET_REQUEST" type="int">
|
||||
<ipxact:name>USE_RESET_REQUEST</ipxact:name>
|
||||
<ipxact:displayName>Use reset request signal</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="SYNC_RESET" type="int">
|
||||
<ipxact:name>SYNC_RESET</ipxact:name>
|
||||
<ipxact:displayName>Use synchronous resets</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="AUTO_CLK_CLOCK_RATE" type="longint">
|
||||
<ipxact:name>AUTO_CLK_CLOCK_RATE</ipxact:name>
|
||||
<ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
|
||||
<ipxact:value>-1</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_module_parameters>
|
||||
<altera:altera_system_parameters>
|
||||
<ipxact:parameters>
|
||||
<ipxact:parameter parameterId="board" type="string">
|
||||
<ipxact:name>board</ipxact:name>
|
||||
<ipxact:displayName>Board</ipxact:displayName>
|
||||
<ipxact:value>default</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="device" type="string">
|
||||
<ipxact:name>device</ipxact:name>
|
||||
<ipxact:displayName>Device</ipxact:displayName>
|
||||
<ipxact:value>A5ED065BB32AE6SR0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceFamily" type="string">
|
||||
<ipxact:name>deviceFamily</ipxact:name>
|
||||
<ipxact:displayName>Device family</ipxact:displayName>
|
||||
<ipxact:value>Agilex 5</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
|
||||
<ipxact:name>deviceSpeedGrade</ipxact:name>
|
||||
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
|
||||
<ipxact:value>6</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="generationId" type="int">
|
||||
<ipxact:name>generationId</ipxact:name>
|
||||
<ipxact:displayName>Generation Id</ipxact:displayName>
|
||||
<ipxact:value>0</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="bonusData" type="string">
|
||||
<ipxact:name>bonusData</ipxact:name>
|
||||
<ipxact:displayName>bonusData</ipxact:displayName>
|
||||
<ipxact:value>bonusData
|
||||
{
|
||||
element altera_reset_bridge_inst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
|
||||
<ipxact:name>hideFromIPCatalog</ipxact:name>
|
||||
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
|
||||
<ipxact:value>false</ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
|
||||
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
|
||||
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
|
||||
<ipxact:value><boundaryDefinition>
|
||||
<interfaces>
|
||||
<interface>
|
||||
<name>in_reset</name>
|
||||
<type>reset</type>
|
||||
<isStart>false</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>in_reset_n</name>
|
||||
<role>reset_n</role>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedClock</key>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>synchronousEdges</key>
|
||||
<value>NONE</value>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface>
|
||||
<name>out_reset</name>
|
||||
<type>reset</type>
|
||||
<isStart>true</isStart>
|
||||
<ports>
|
||||
<port>
|
||||
<name>out_reset_n</name>
|
||||
<role>reset_n</role>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<lowerBound>0</lowerBound>
|
||||
<vhdlType>STD_LOGIC</vhdlType>
|
||||
<terminationValue>0</terminationValue>
|
||||
</port>
|
||||
</ports>
|
||||
<assignments>
|
||||
<assignmentValueMap/>
|
||||
</assignments>
|
||||
<parameters>
|
||||
<parameterValueMap>
|
||||
<entry>
|
||||
<key>associatedClock</key>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>associatedDirectReset</key>
|
||||
<value>in_reset</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>associatedResetSinks</key>
|
||||
<value>in_reset</value>
|
||||
</entry>
|
||||
<entry>
|
||||
<key>synchronousEdges</key>
|
||||
<value>NONE</value>
|
||||
</entry>
|
||||
</parameterValueMap>
|
||||
</parameters>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</boundaryDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="systemInfos" type="string">
|
||||
<ipxact:name>systemInfos</ipxact:name>
|
||||
<ipxact:displayName>systemInfos</ipxact:displayName>
|
||||
<ipxact:value><systemInfosDefinition>
|
||||
<connPtSystemInfos/>
|
||||
</systemInfosDefinition></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="dflBitArray" type="string">
|
||||
<ipxact:name>dflBitArray</ipxact:name>
|
||||
<ipxact:displayName>dflBitArray</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
<ipxact:parameter parameterId="cpuInfo" type="string">
|
||||
<ipxact:name>cpuInfo</ipxact:name>
|
||||
<ipxact:displayName>cpuInfo</ipxact:displayName>
|
||||
<ipxact:value></ipxact:value>
|
||||
</ipxact:parameter>
|
||||
</ipxact:parameters>
|
||||
</altera:altera_system_parameters>
|
||||
<altera:altera_interface_boundary>
|
||||
<altera:interface_mapping altera:name="clk" altera:internal="altera_reset_bridge_inst.clk"></altera:interface_mapping>
|
||||
<altera:interface_mapping altera:name="in_reset" altera:internal="altera_reset_bridge_inst.in_reset" altera:type="reset" altera:dir="end">
|
||||
<altera:port_mapping altera:name="in_reset_n" altera:internal="in_reset_n"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
<altera:interface_mapping altera:name="out_reset" altera:internal="altera_reset_bridge_inst.out_reset" altera:type="reset" altera:dir="start">
|
||||
<altera:port_mapping altera:name="out_reset_n" altera:internal="out_reset_n"></altera:port_mapping>
|
||||
</altera:interface_mapping>
|
||||
</altera:altera_interface_boundary>
|
||||
<altera:altera_has_warnings>false</altera:altera_has_warnings>
|
||||
<altera:altera_has_errors>false</altera:altera_has_errors>
|
||||
</ipxact:vendorExtensions>
|
||||
</ipxact:component>
|
||||
@@ -0,0 +1,7 @@
|
||||
component periph_rst_in is
|
||||
port (
|
||||
in_reset_n : in std_logic := 'X'; -- reset_n
|
||||
out_reset_n : out std_logic -- reset_n
|
||||
);
|
||||
end component periph_rst_in;
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for periph_rst_in</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">periph_rst_in</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:51</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_reset_bridge_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_reset_bridge_inst</h2>altera_reset_bridge v19.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">ACTIVE_LOW_RESET</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">SYNCHRONOUS_EDGES</td>
|
||||
<td class="parametervalue">none</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">O_SYNCHRONOUS_EDGES</td>
|
||||
<td class="parametervalue">none</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUM_RESET_OUTPUTS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">USE_RESET_REQUEST</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">SYNC_RESET</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.00 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,56 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">periph_rst_in</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>periph_rst_in</className>
|
||||
<version>1.0</version>
|
||||
<name>periph_rst_in</name>
|
||||
<uniqueName>periph_rst_in</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_reset_bridge_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>ACTIVE_LOW_RESET</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>NUM_RESET_OUTPUTS</name>
|
||||
<value>1</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>O_SYNCHRONOUS_EDGES</name>
|
||||
<value>none</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>SYNCHRONOUS_EDGES</name>
|
||||
<value>none</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>SYNC_RESET</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>USE_RESET_REQUEST</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_reset_bridge</className>
|
||||
<version>19.2.0</version>
|
||||
<name>altera_reset_bridge_inst</name>
|
||||
<uniqueName>periph_rst_in_altera_reset_bridge_1920_xf2264i</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>periph_rst_in.altera_reset_bridge_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,29 @@
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_reset_bridge"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name OCS_IP_FILE [file join $::quartus(qip_path) "../periph_rst_in.ip"]
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name OCS_IP_TYPE "altera_reset_bridge"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name OCS_IP_VERSION "19.2.0"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name OCS_IP_HASH "xf2264i"
|
||||
set_global_assignment -library "periph_rst_in" -name SOPCINFO_FILE [file join $::quartus(qip_path) "periph_rst_in.sopcinfo"]
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name SLD_INFO "QSYS_NAME periph_rst_in HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "periph_rst_in" -name MISC_FILE [file join $::quartus(qip_path) "periph_rst_in.cmp"]
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "periph_rst_in" -name MISC_FILE [file join $::quartus(qip_path) "../periph_rst_in.ip"]
|
||||
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_COMPONENT_NAME "cGVyaXBoX3JzdF9pbg=="
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "periph_rst_in" -library "periph_rst_in" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "periph_rst_in" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/periph_rst_in.v"]
|
||||
|
||||
@@ -0,0 +1,294 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="periph_rst_in" kind="periph_rst_in" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
|
||||
<!-- 2026.05.11.21:03:52 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
|
||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altera_reset_bridge_inst"
|
||||
kind="altera_reset_bridge"
|
||||
version="19.2.0"
|
||||
path="altera_reset_bridge_inst"
|
||||
className="altera_reset_bridge">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="ACTIVE_LOW_RESET">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="SYNCHRONOUS_EDGES">
|
||||
<type>java.lang.String</type>
|
||||
<value>none</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="O_SYNCHRONOUS_EDGES">
|
||||
<type>java.lang.String</type>
|
||||
<value>none</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUM_RESET_OUTPUTS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="USE_RESET_REQUEST">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="SYNC_RESET">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE">
|
||||
<type>java.lang.Long</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="in_reset" kind="reset_sink" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>NONE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>in_reset_n</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>reset_n</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="out_reset" kind="reset_source" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedDirectReset">
|
||||
<type>java.lang.String</type>
|
||||
<value>in_reset</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedResetSinks">
|
||||
<type>[Ljava.lang.String;</type>
|
||||
<value>in_reset</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>NONE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<span>0</span>
|
||||
<isStart>true</isStart>
|
||||
<port>
|
||||
<name>out_reset_n</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>reset_n</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_reset_bridge</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>Reset Bridge IP</displayName>
|
||||
<version>19.2.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>reset_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Reset Input</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>reset_source</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Reset Output</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<reportVersion>26.1 110</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
@@ -0,0 +1,81 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:52"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5ED065BB32AE6SR0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="6"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="in_reset" kind="reset" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="synchronousEdges" value="NONE" />
|
||||
<port name="in_reset_n" direction="input" role="reset_n" width="1" />
|
||||
</interface>
|
||||
<interface name="out_reset" kind="reset" start="1">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedDirectReset" value="in_reset" />
|
||||
<property name="associatedResetSinks" value="in_reset" />
|
||||
<property name="synchronousEdges" value="NONE" />
|
||||
<port name="out_reset_n" direction="output" role="reset_n" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="periph_rst_in" version="1.0" name="periph_rst_in">
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in/synth/periph_rst_in.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in/synth/periph_rst_in.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<messages>
|
||||
<message level="Info" culprit="periph_rst_in">"Generating: periph_rst_in"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,6 @@
|
||||
module periph_rst_in (
|
||||
input wire in_reset_n, // in_reset.reset_n, Reset Input
|
||||
output wire out_reset_n // out_reset.reset_n, Reset Output
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: periph_rst_in: "Transforming system: periph_rst_in"
|
||||
Info: periph_rst_in: "Naming system components in system: periph_rst_in"
|
||||
Info: periph_rst_in: "Processing generation queue"
|
||||
Info: periph_rst_in: "Generating: periph_rst_in"
|
||||
Info: periph_rst_in: Done "periph_rst_in" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: periph_rst_in: "Transforming system: periph_rst_in"
|
||||
Info: periph_rst_in: "Naming system components in system: periph_rst_in"
|
||||
Info: periph_rst_in: "Processing generation queue"
|
||||
Info: periph_rst_in: "Generating: periph_rst_in"
|
||||
Info: periph_rst_in: Done "periph_rst_in" with 1 modules, 1 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,5 @@
|
||||
periph_rst_in u0 (
|
||||
.in_reset_n (_connected_to_in_reset_n_), // input, width = 1, in_reset.reset_n
|
||||
.out_reset_n (_connected_to_out_reset_n_) // output, width = 1, out_reset.reset_n
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
component periph_rst_in is
|
||||
port (
|
||||
in_reset_n : in std_logic := 'X'; -- reset_n
|
||||
out_reset_n : out std_logic -- reset_n
|
||||
);
|
||||
end component periph_rst_in;
|
||||
|
||||
u0 : component periph_rst_in
|
||||
port map (
|
||||
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
|
||||
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
|
||||
);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
// periph_rst_in.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module periph_rst_in (
|
||||
input wire in_reset_n, // in_reset.reset_n, Reset Input
|
||||
output wire out_reset_n // out_reset.reset_n, Reset Output
|
||||
);
|
||||
|
||||
assign out_reset_n = in_reset_n;
|
||||
|
||||
endmodule
|
||||
+1039
File diff suppressed because it is too large
Load Diff
+51
@@ -0,0 +1,51 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synthesis translate_off
|
||||
`timescale 1ns / 1ps
|
||||
// synthesis translate_on
|
||||
|
||||
// turn off superfluous verilog processor warnings
|
||||
// altera message_level Level1
|
||||
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
||||
|
||||
module altera_avalon_sysid_qsys #(
|
||||
parameter USE_MANUAL_ID = 1,
|
||||
parameter MANUAL_ID = 1,
|
||||
parameter HASH_ID = 1,
|
||||
parameter TIMESTAMP = 1
|
||||
)(
|
||||
// inputs:
|
||||
address,
|
||||
clock,
|
||||
reset_n,
|
||||
|
||||
// outputs:
|
||||
readdata
|
||||
)
|
||||
;
|
||||
|
||||
output [ 31: 0] readdata;
|
||||
input address;
|
||||
input clock;
|
||||
input reset_n;
|
||||
|
||||
wire [ 31: 0] readdata /* synthesis keep */;
|
||||
|
||||
//control_slave, which is an e_avalon_slave
|
||||
assign readdata = address ? TIMESTAMP : ( USE_MANUAL_ID ? MANUAL_ID : HASH_ID );
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "fs3MoWBgHCF39POOsRTSk9Of235Syebg6gnxSRl1C3eH9/q9SvVYcuvHV6n+ciNcw1ZgnLUuBtqkgc5BFhhjFnxbTVeuzHhPTudkRx35Y+NfPOUkDAugUZPKer0wXL9pRAwH3byzjlgXB2SHOxqIBOiiFdHFMWEzFqqitQSeTR0XsgNSEUtkjewHkaIdmB+gUPZtp91aSbp/tszSUSGSEr2Yzzd/T421QZLUt8TjkSAX3MiQzLCld5uc3gusaASxJs8EiAqtYMG8WvSbz+XbYuGuQ2BxoSO4PQReiAxvTYahcR/B7r5Hb25X20wxnje6FXwJLddEfpRCXQewdtHHOV8C8p3u8JJGR/hmRrH2nvkNtUdlSgIWeux0NHfYnd64bzu3Y+/2IWgGgYSKvSj5yIFz+5stifj0nJDt+OeF7mCTZMmYCHeFIIB3MGzW0i0d6zVOmZsKUXRMfhKSwyak5qvQ4vTdo+4kf/B/aUUX1i06puA8GMo2qxUDRbdF6DikdeRFV0zetxOvQBdapdyAm72WQmH9WkKnQUnbtBAqktPybox5syEUX6br/91mObR7PwMaYeHSipwiEVGkNEazGsgfiZfhzTeaEYC4ScHRG9nyFsZ71G93NQiYNV0UEaJ8jetWsmiEzG6HB45K5Syt92jAz1qZSCSRUO394886nPPPHGmqx6BLgYWylmZtFEyhLBjV6ltEHdejtAd50hN1cHEOnW811j2TfgU17EARwWukr6NVpEXyd5sDScpo3WaWbYdalFRhgVH2dRGe1cFTKHBV2Lh56GzLFM6VUm0n0bk7Ksli+ah7Lpk7fwzrACVh+UsjK0zxjEXMROzjKeKm+ZMdHFUnnBDjE/NnJBgs83sdJW3gZLkjTnevn1jumrmCYQtucdMSueNkkSjlmRTkkEozvKJcjm/WV38+W6yBPpRUZ4w72K3/plbJqSCp6uURb3ldgksghBQziyGsSuME/FTf1QxFk/6TwM+uvjJsCsSpqpuQdoyinGD+tHEVSLqh"
|
||||
`endif
|
||||
@@ -0,0 +1,27 @@
|
||||
// sysid.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module sysid #(
|
||||
parameter MANUAL_ID = -1395275010
|
||||
) (
|
||||
input wire clock, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
output wire [31:0] readdata, // control_slave.readdata
|
||||
input wire address // .address
|
||||
);
|
||||
|
||||
altera_avalon_sysid_qsys #(
|
||||
.TIMESTAMP (0),
|
||||
.USE_MANUAL_ID (1),
|
||||
.MANUAL_ID (MANUAL_ID),
|
||||
.HASH_ID (0)
|
||||
) altera_avalon_sysid_qsys_inst (
|
||||
.clock (clock), // input, width = 1, clk.clk
|
||||
.reset_n (reset_n), // input, width = 1, reset.reset_n
|
||||
.readdata (readdata), // output, width = 32, control_slave.readdata
|
||||
.address (address) // input, width = 1, .address
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,12 @@
|
||||
component sysid is
|
||||
generic (
|
||||
MANUAL_ID : integer := -1395275010
|
||||
);
|
||||
port (
|
||||
clock : in std_logic := 'X'; -- clk
|
||||
reset_n : in std_logic := 'X'; -- reset_n
|
||||
readdata : out std_logic_vector(31 downto 0); -- readdata
|
||||
address : in std_logic := 'X' -- address
|
||||
);
|
||||
end component sysid;
|
||||
|
||||
@@ -0,0 +1,164 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for sysid</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">sysid</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:03:49</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/>All Components
|
||||
<br/>  
|
||||
<a href="#module_altera_avalon_sysid_qsys_inst"><b>altera_avalon_sysid_qsys_inst</b>
|
||||
</a> altera_avalon_sysid_qsys 20.0.0</span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slavemodule"> 
|
||||
<a href="#module_altera_avalon_sysid_qsys_inst"><b>altera_avalon_sysid_qsys_inst</b>
|
||||
</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="slaveb">control_slave </td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altera_avalon_sysid_qsys_inst"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altera_avalon_sysid_qsys_inst</h2>altera_avalon_sysid_qsys v20.0.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">USE_LIVE_TIMESTAMP</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">USE_MANUAL_ID</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">id</td>
|
||||
<td class="parametervalue">-1395275010</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">ID</td>
|
||||
<td class="parametervalue">-1395275010</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.07 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,61 @@
|
||||
<?xml version="1.0" ?>
|
||||
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
|
||||
<instanceKey xsi:type="xs:string">sysid</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters></parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>sysid</className>
|
||||
<version>1.0</version>
|
||||
<name>sysid</name>
|
||||
<uniqueName>sysid</uniqueName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
</instanceData>
|
||||
<children>
|
||||
<node>
|
||||
<instanceKey xsi:type="xs:string">altera_avalon_sysid_qsys_inst</instanceKey>
|
||||
<instanceData xsi:type="data">
|
||||
<parameters>
|
||||
<parameter>
|
||||
<name>HASH_ID</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>HASH_INT</name>
|
||||
<value></value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>MANUAL_ID</name>
|
||||
<value>-1395275010</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>TIMESTAMP</name>
|
||||
<value>0</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>USE_LIVE_TIMESTAMP</name>
|
||||
<value>false</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>USE_MANUAL_ID</name>
|
||||
<value>true</value>
|
||||
</parameter>
|
||||
<parameter>
|
||||
<name>id</name>
|
||||
<value>-1395275010</value>
|
||||
</parameter>
|
||||
</parameters>
|
||||
<interconnectAssignments></interconnectAssignments>
|
||||
<className>altera_avalon_sysid_qsys</className>
|
||||
<version>20.0.0</version>
|
||||
<name>altera_avalon_sysid_qsys_inst</name>
|
||||
<uniqueName>altera_avalon_sysid_qsys</uniqueName>
|
||||
<fixedName>altera_avalon_sysid_qsys</fixedName>
|
||||
<nonce>0</nonce>
|
||||
<incidentConnections></incidentConnections>
|
||||
<path>sysid.altera_avalon_sysid_qsys_inst</path>
|
||||
</instanceData>
|
||||
<children></children>
|
||||
</node>
|
||||
</children>
|
||||
</node>
|
||||
@@ -0,0 +1,40 @@
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_TOOL_VENDOR_NAME "Altera"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_avalon_sysid_qsys"
|
||||
set_global_assignment -library "sysid" -name SOPCINFO_FILE [file join $::quartus(qip_path) "sysid.sopcinfo"]
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name SLD_INFO "QSYS_NAME sysid HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "sysid" -name MISC_FILE [file join $::quartus(qip_path) "sysid.cmp"]
|
||||
set_global_assignment -library "sysid" -name SLD_FILE [file join $::quartus(qip_path) "sysid.regmap"]
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "sysid" -name MISC_FILE [file join $::quartus(qip_path) "../sysid.ip"]
|
||||
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_NAME "YWx0ZXJhX2F2YWxvbl9zeXNpZF9xc3lz"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_DISPLAY_NAME "U3lzdGVtIElEIFBlcmlwaGVyYWwgSVA="
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_VERSION "MjAuMC4w"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL1NpbXVsYXRpb247IERlYnVnIGFuZCBWZXJpZmljYXRpb24vRGVidWcgYW5kIFBlcmZvcm1hbmNl"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3N5c3RlbS1pZC1wZXJpcGhlcmFsLWNvcmUuaHRtbA=="
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzY4MzEzMC9jdXJyZW50L3N5c3RlbS1pZC1jb3JlLXJldmlzaW9uLWhpc3RvcnkuaHRtbA=="
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_COMPONENT_NAME "c3lzaWQ="
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
|
||||
set_global_assignment -entity "sysid" -library "sysid" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
|
||||
set_global_assignment -library "altera_avalon_sysid_qsys_2000" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_sysid_qsys_2000/synth/altera_avalon_sysid_qsys.v"]
|
||||
set_global_assignment -library "sysid" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/sysid.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_TOOL_NAME "altera_avalon_sysid_qsys"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_TOOL_VERSION "20.0.0"
|
||||
set_global_assignment -entity "altera_avalon_sysid_qsys" -library "altera_avalon_sysid_qsys_2000" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
|
||||
<name>sysid</name>
|
||||
<peripherals>
|
||||
<peripheral>
|
||||
<name>sysid_control_slave_altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>8</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>ID</name>
|
||||
<displayName>System ID</displayName>
|
||||
<description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-only</access>
|
||||
<resetValue>${sysid_id_value}</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>id</name>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>TIMESTAMP</name>
|
||||
<displayName>Time stamp</displayName>
|
||||
<description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-only</access>
|
||||
<resetValue>${sysid_timestamp_value}</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>timestamp</name>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
<peripheral>
|
||||
<name>sysid_altera_avalon_sysid_qsys_inst_control_slave_altera_avalon_sysid</name><baseAddress>0x00000000</baseAddress>
|
||||
<addressBlock>
|
||||
<offset>0x0</offset>
|
||||
<size>8</size>
|
||||
<usage>registers</usage>
|
||||
</addressBlock>
|
||||
<registers>
|
||||
<register>
|
||||
<name>ID</name>
|
||||
<displayName>System ID</displayName>
|
||||
<description>A unique 32-bit value that is based on the contents of the QSys system. The id is similar to a check-sum value; QSys systems with different components, different configuration options, or both, produce different id values.</description>
|
||||
<addressOffset>0x0</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-only</access>
|
||||
<resetValue>${sysid_id_value}</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>id</name>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
<register>
|
||||
<name>TIMESTAMP</name>
|
||||
<displayName>Time stamp</displayName>
|
||||
<description>A unique 32-bit value that is based on the system generation time. The value is equivalent to the number of seconds after Jan. 1, 1970.</description>
|
||||
<addressOffset>0x4</addressOffset>
|
||||
<size>32</size>
|
||||
<access>read-only</access>
|
||||
<resetValue>${sysid_timestamp_value}</resetValue>
|
||||
<resetMask>0xffffffff</resetMask>
|
||||
<fields>
|
||||
<field><name>timestamp</name>
|
||||
<bitOffset>0x0</bitOffset>
|
||||
<bitWidth>32</bitWidth>
|
||||
<access>read-only</access>
|
||||
</field>
|
||||
</fields>
|
||||
</register>
|
||||
</registers>
|
||||
</peripheral>
|
||||
</peripherals>
|
||||
</device>
|
||||
@@ -0,0 +1,825 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="sysid" kind="sysid" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
|
||||
<!-- 2026.05.11.21:03:49 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>A5EB013BB23BE4SCS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>4</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_BOARD">
|
||||
<type>java.lang.String</type>
|
||||
<value>default</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>BOARD</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE">
|
||||
<type>java.lang.Long</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_RATE</sysinfo_type>
|
||||
<sysinfo_arg>clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>-1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
|
||||
<sysinfo_arg>clk</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="AUTO_CONTROL_SLAVE_CPU_INFO_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
||||
<sysinfo_arg>control_slave</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Agilex 5</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altera_avalon_sysid_qsys_inst"
|
||||
kind="altera_avalon_sysid_qsys"
|
||||
version="20.0.0"
|
||||
entity="altera_avalon_sysid_qsys"
|
||||
library="altera_avalon_sysid_qsys_2000"
|
||||
path="altera_avalon_sysid_qsys_inst"
|
||||
hpath="altera_avalon_sysid_qsys_inst"
|
||||
className="altera_avalon_sysid_qsys">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.CMacro.ID</name>
|
||||
<value>-1395275010</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.compatible</name>
|
||||
<value>altr,sysid-1.0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.group</name>
|
||||
<value>sysid</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.name</name>
|
||||
<value>sysid</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.params.id</name>
|
||||
<value>-1395275010</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.vendor</name>
|
||||
<value>altr</value>
|
||||
</assignment>
|
||||
<parameter name="TIMESTAMP">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="USE_LIVE_TIMESTAMP">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="USE_MANUAL_ID">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="id">
|
||||
<type>int</type>
|
||||
<value>-1395275010</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="MANUAL_ID">
|
||||
<type>int</type>
|
||||
<value>-1395275010</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="HASH_INT">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>CPU_INFO_ID</sysinfo_type>
|
||||
<sysinfo_arg>control_slave</sysinfo_arg>
|
||||
</parameter>
|
||||
<parameter name="HASH_ID">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>true</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="clk" kind="clock_sink" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="externallyDriven">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ptfSchematicName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>clock</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>clock</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>clk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="reset" kind="reset_sink" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clk</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="synchronousEdges">
|
||||
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
|
||||
<value>DEASSERT</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>reset</type>
|
||||
<span>0</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>reset_n</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>reset_n</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="control_slave" kind="avalon_slave" version="26.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isMemoryDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isNonVolatileStorage</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.configuration.isPrintableDevice</name>
|
||||
<value>0</value>
|
||||
</assignment>
|
||||
<parameter name="addressAlignment">
|
||||
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
|
||||
<value>DYNAMIC</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressGroup">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>8</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="addressUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="alwaysBurstMaxBurst">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value>clk</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value>reset</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bitsPerSymbol">
|
||||
<type>int</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgedAddressOffset">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="bridgesToMaster">
|
||||
<type>com.altera.entityinterfaces.IConnectionPoint</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstOnBurstBoundariesOnly">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="burstcountUnits">
|
||||
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
|
||||
<value>WORDS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="constantBurstBehavior">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="explicitAddressSpan">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="holdTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="interleaveBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isBigEndian">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isFlash">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isMemoryDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="isNonVolatileStorage">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="linewrapBursts">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingReadTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maximumPendingWriteTransactions">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="minimumReadLatency">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="minimumResponseLatency">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="minimumUninterruptedRunLength">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="prSafe">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="printableDevice">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readLatency">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitStates">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="readWaitTime">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerIncomingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="registerOutgoingSignals">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="setupTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="timingUnits">
|
||||
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
|
||||
<value>Cycles</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="transparentBridge">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="waitrequestAllowance">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="waitrequestTimeout">
|
||||
<type>int</type>
|
||||
<value>1024</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="wellBehavedWaitrequest">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeLatency">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitStates">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="writeWaitTime">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhFeatureGuid">
|
||||
<type>java.math.BigInteger</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhGroupId">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhParameterId">
|
||||
<type>[Ljava.lang.Integer;</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhParameterName">
|
||||
<type>[Ljava.lang.String;</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhParameterVersion">
|
||||
<type>[Ljava.lang.Integer;</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhParameterData">
|
||||
<type>[Ljava.lang.String;</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhParameterDataLength">
|
||||
<type>[Ljava.lang.Integer;</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhFeatureMajorVersion">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhFeatureMinorVersion">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhFeatureId">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>35</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="dfhFeatureType">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>3</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>avalon</type>
|
||||
<span>8</span>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>readdata</name>
|
||||
<direction>Output</direction>
|
||||
<width>32</width>
|
||||
<role>readdata</role>
|
||||
</port>
|
||||
<port>
|
||||
<name>address</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>address</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_avalon_sysid_qsys</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>System ID Peripheral IP</displayName>
|
||||
<version>20.0.0</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>clock_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Clock Input</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>reset_sink</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Reset Input</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>avalon_slave</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Avalon Memory Mapped Agent</displayName>
|
||||
<version>26.1</version>
|
||||
</plugin>
|
||||
<reportVersion>26.1 110</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
@@ -0,0 +1,199 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2026.05.11.21:03:49"
|
||||
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Agilex 5"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="A5EB013BB23BE4SR1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="4"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_BOARD"
|
||||
type="String"
|
||||
defaultValue="default"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_RATE"
|
||||
type="Long"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_CLOCK_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CLK_RESET_DOMAIN"
|
||||
type="Integer"
|
||||
defaultValue="-1"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_CONTROL_SLAVE_CPU_INFO_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="clk" kind="clock" start="0">
|
||||
<property name="clockRate" value="0" />
|
||||
<property name="externallyDriven" value="false" />
|
||||
<property name="ptfSchematicName" value="" />
|
||||
<port name="clock" direction="input" role="clk" width="1" />
|
||||
</interface>
|
||||
<interface name="reset" kind="reset" start="0">
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="synchronousEdges" value="DEASSERT" />
|
||||
<port name="reset_n" direction="input" role="reset_n" width="1" />
|
||||
</interface>
|
||||
<interface name="control_slave" kind="avalon" start="0">
|
||||
<property name="addressAlignment" value="DYNAMIC" />
|
||||
<property name="addressGroup" value="0" />
|
||||
<property name="addressSpan" value="8" />
|
||||
<property name="addressUnits" value="WORDS" />
|
||||
<property name="alwaysBurstMaxBurst" value="false" />
|
||||
<property name="associatedClock" value="clk" />
|
||||
<property name="associatedReset" value="reset" />
|
||||
<property name="bitsPerSymbol" value="8" />
|
||||
<property name="bridgedAddressOffset" value="0" />
|
||||
<property name="bridgesToMaster" value="" />
|
||||
<property name="burstOnBurstBoundariesOnly" value="false" />
|
||||
<property name="burstcountUnits" value="WORDS" />
|
||||
<property name="constantBurstBehavior" value="false" />
|
||||
<property name="explicitAddressSpan" value="0" />
|
||||
<property name="holdTime" value="0" />
|
||||
<property name="interleaveBursts" value="false" />
|
||||
<property name="isBigEndian" value="false" />
|
||||
<property name="isFlash" value="false" />
|
||||
<property name="isMemoryDevice" value="false" />
|
||||
<property name="isNonVolatileStorage" value="false" />
|
||||
<property name="linewrapBursts" value="false" />
|
||||
<property name="maximumPendingReadTransactions" value="0" />
|
||||
<property name="maximumPendingWriteTransactions" value="0" />
|
||||
<property name="minimumReadLatency" value="1" />
|
||||
<property name="minimumResponseLatency" value="1" />
|
||||
<property name="minimumUninterruptedRunLength" value="1" />
|
||||
<property name="prSafe" value="false" />
|
||||
<property name="printableDevice" value="false" />
|
||||
<property name="readLatency" value="0" />
|
||||
<property name="readWaitStates" value="1" />
|
||||
<property name="readWaitTime" value="1" />
|
||||
<property name="registerIncomingSignals" value="false" />
|
||||
<property name="registerOutgoingSignals" value="false" />
|
||||
<property name="setupTime" value="0" />
|
||||
<property name="timingUnits" value="Cycles" />
|
||||
<property name="transparentBridge" value="false" />
|
||||
<property name="waitrequestAllowance" value="0" />
|
||||
<property name="waitrequestTimeout" value="1024" />
|
||||
<property name="wellBehavedWaitrequest" value="false" />
|
||||
<property name="writeLatency" value="0" />
|
||||
<property name="writeWaitStates" value="0" />
|
||||
<property name="writeWaitTime" value="0" />
|
||||
<property name="dfhFeatureGuid" value="0" />
|
||||
<property name="dfhGroupId" value="0" />
|
||||
<property name="dfhParameterId" value="" />
|
||||
<property name="dfhParameterName" value="" />
|
||||
<property name="dfhParameterVersion" value="" />
|
||||
<property name="dfhParameterData" value="" />
|
||||
<property name="dfhParameterDataLength" value="" />
|
||||
<property name="dfhFeatureMajorVersion" value="0" />
|
||||
<property name="dfhFeatureMinorVersion" value="0" />
|
||||
<property name="dfhFeatureId" value="35" />
|
||||
<property name="dfhFeatureType" value="3" />
|
||||
<port name="readdata" direction="output" role="readdata" width="32" />
|
||||
<port name="address" direction="input" role="address" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity kind="sysid" version="1.0" name="sysid">
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
|
||||
<parameter name="AUTO_BOARD" value="default" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_CONTROL_SLAVE_CPU_INFO_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid/synth/sysid.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid/synth/sysid.v"
|
||||
attributes="CONTAINS_INLINE_CONFIGURATION" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid.ip" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Info" culprit="sysid">"Generating: sysid"</message>
|
||||
<message level="Info" culprit="sysid">"Generating: altera_avalon_sysid_qsys"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
kind="altera_avalon_sysid_qsys"
|
||||
version="20.0.0"
|
||||
name="altera_avalon_sysid_qsys">
|
||||
<parameter name="HASH_INT" value="" />
|
||||
<parameter name="USE_LIVE_TIMESTAMP" value="false" />
|
||||
<parameter name="HASH_ID" value="0" />
|
||||
<parameter name="USE_MANUAL_ID" value="true" />
|
||||
<parameter name="TIMESTAMP" value="0" />
|
||||
<parameter name="id" value="-1395275010" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid/altera_avalon_sysid_qsys_2000/synth/altera_avalon_sysid_qsys.v"
|
||||
attributes="TOP_LEVEL_FILE" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid/altera_avalon_sysid_qsys_2000/synth/altera_avalon_sysid_qsys.v"
|
||||
attributes="TOP_LEVEL_FILE" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="sysid" as="altera_avalon_sysid_qsys_inst" />
|
||||
<messages>
|
||||
<message level="Info" culprit="sysid">"Generating: altera_avalon_sysid_qsys"</message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
@@ -0,0 +1,10 @@
|
||||
module sysid #(
|
||||
parameter MANUAL_ID = -1395275010
|
||||
) (
|
||||
input wire clock, // clk.clk
|
||||
input wire reset_n, // reset.reset_n
|
||||
output wire [31:0] readdata, // control_slave.readdata
|
||||
input wire address // .address
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: sysid.altera_avalon_sysid_qsys_inst: Live Timestamp is turned off. Timestamp is fixed to 0
|
||||
Info: sysid.altera_avalon_sysid_qsys_inst: Edit the System ID parameter to provide a unique ID
|
||||
Info: sysid: "Transforming system: sysid"
|
||||
Info: sysid: "Naming system components in system: sysid"
|
||||
Info: sysid: "Processing generation queue"
|
||||
Info: sysid: "Generating: sysid"
|
||||
Info: sysid: "Generating: altera_avalon_sysid_qsys"
|
||||
Info: sysid: Done "sysid" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
@@ -0,0 +1,12 @@
|
||||
Info: Generated by version: 25.3.1 build 100
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/sysid --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Info: sysid.altera_avalon_sysid_qsys_inst: Live Timestamp is turned off. Timestamp is fixed to 0
|
||||
Info: sysid.altera_avalon_sysid_qsys_inst: Edit the System ID parameter to provide a unique ID
|
||||
Info: sysid: "Transforming system: sysid"
|
||||
Info: sysid: "Naming system components in system: sysid"
|
||||
Info: sysid: "Processing generation queue"
|
||||
Info: sysid: "Generating: sysid"
|
||||
Info: sysid: "Generating: altera_avalon_sysid_qsys"
|
||||
Info: sysid: Done "sysid" with 2 modules, 2 files
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user