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Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

Browse Source 
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-06-29 20:10:50 -04:00
commit ec82764bef
2462 changed files with 2174303 additions and 0 deletions
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qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate.sv
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// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// +-----------------------------------------------------------
// | Nadder LSM GPO
// +-----------------------------------------------------------
`timescale 1 ns / 1 ns
module intel_user_rst_clkgate(
output logic ninit_done
);
localparam USER_RESET_DELAY = 20;
altera_agilex_config_reset_release_endpoint config_reset_release_endpoint(
.conf_reset(ninit_done)
);
endmodule
qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate_agilex.sdc
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# (C) 2001-2026 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files from any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera IP License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
#Create base clock with 100 MHz targetted for internal clocks if paths listed below found in the design
#Agilex
#auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|agilexconfigreset|user_reset|sdm_gpo_out_user_reset~internal_ctrl_clock.reg
set intrl_ctrl_reg_count 0
set intrl_ctrl_reg_collection [get_registers -nowarn "auto_fab*\|*\|*sdm_gpo_out_user_reset~internal_ctrl_clock.reg"]
set intrl_ctrl_reg_count [ get_collection_size $intrl_ctrl_reg_collection ]
if {$intrl_ctrl_reg_count > 0 && ![get_collection_size [get_clocks -nowarn {internal_clk}]]} {
create_clock -name internal_clk -period 10.000 -waveform {0.000 5.000} { auto_fab*|*|*sdm_gpo_out_user_reset~internal_ctrl_clock.reg }
set_clock_groups -asynchronous -group [get_clocks {internal_clk}]
set intrl_clock_count [get_collection_size [get_clocks internal_clk]]
}
qsys/ip/qsys_top/user_rst_clkgate_0/synth/user_rst_clkgate_0.v
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// user_rst_clkgate_0.v
// Generated using ACDS version 26.1 110
`timescale 1 ps / 1 ps
module user_rst_clkgate_0 (
output wire ninit_done // ninit_done.ninit_done
);
intel_user_rst_clkgate intel_user_rst_clkgate_inst (
.ninit_done (ninit_done) // output, width = 1, ninit_done.ninit_done
);
endmodule
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0.cmp
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component user_rst_clkgate_0 is
port (
ninit_done : out std_logic -- ninit_done
);
end component user_rst_clkgate_0;
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0.html
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>datasheet for user_rst_clkgate_0</title>
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table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
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table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
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</head>
<body>
<table class="topTitle">
<tr>
<td class="l">user_rst_clkgate_0</td>
<td class="r">
<br/>
<br/>
</td>
</tr>
</table>
<table class="blueBar">
<tr>
<td class="l">2026.05.11.21:03:48</td>
<td class="r">Datasheet</td>
</tr>
</table>
<div style="width:100% ; height:10px"> </div>
<div class="label">Overview</div>
<div class="greydiv">
<div style="display:inline-block ; text-align:left">
<table class="connectionboxes">
<tr style="height:6px">
<td></td>
</tr>
</table>
</div><span style="display:inline-block ; width:28px"> </span>
<div style="display:inline-block ; text-align:left"><span>
<br/></span>
</div>
</div>
<div style="width:100% ; height:10px"> </div>
<div class="label">Memory Map</div>
<table class="mmap">
<tr>
<td class="empty" rowspan="2"></td>
</tr>
</table>
<a name="module_intel_user_rst_clkgate_inst"> </a>
<div>
<hr/>
<h2>intel_user_rst_clkgate_inst</h2>intel_user_rst_clkgate v1.0.1
<br/>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">outputType</td>
<td class="parametervalue">Conduit Interface</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>(none)</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.04 seconds</td>
</tr>
</table>
</body>
</html>
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0.qgsynthc
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<?xml version="1.0" ?>
<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
<instanceKey xsi:type="xs:string">user_rst_clkgate_0</instanceKey>
<instanceData xsi:type="data">
<parameters></parameters>
<interconnectAssignments></interconnectAssignments>
<className>user_rst_clkgate_0</className>
<version>1.0</version>
<name>user_rst_clkgate_0</name>
<uniqueName>user_rst_clkgate_0</uniqueName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
</instanceData>
<children>
<node>
<instanceKey xsi:type="xs:string">intel_user_rst_clkgate_inst</instanceKey>
<instanceData xsi:type="data">
<parameters>
<parameter>
<name>DEVICE_FAMILY</name>
<value>Agilex 5</value>
</parameter>
<parameter>
<name>outputType</name>
<value>Conduit Interface</value>
</parameter>
</parameters>
<interconnectAssignments></interconnectAssignments>
<className>intel_user_rst_clkgate</className>
<version>1.0.1</version>
<name>intel_user_rst_clkgate_inst</name>
<uniqueName>intel_user_rst_clkgate</uniqueName>
<fixedName>intel_user_rst_clkgate</fixedName>
<nonce>0</nonce>
<incidentConnections></incidentConnections>
<path>user_rst_clkgate_0.intel_user_rst_clkgate_inst</path>
</instanceData>
<children></children>
</node>
</children>
</node>
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0.qip
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set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_VERSION "26.1"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOOL_VENDOR_NAME "Altera"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TOP_LEVEL_COMPONENT_NAME "intel_user_rst_clkgate"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name PRE_COMPILED_MODULE "ON"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_FILE [file join $::quartus(qip_path) "../user_rst_clkgate_0.ip"]
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_TYPE "intel_user_rst_clkgate"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_VERSION "1.0.1"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name OCS_IP_HASH "nvr4dnq"
set_global_assignment -library "user_rst_clkgate_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "user_rst_clkgate_0.sopcinfo"]
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name SLD_INFO "QSYS_NAME user_rst_clkgate_0 HAS_SOPCINFO 1 GENERATION_ID 0"
set_global_assignment -library "user_rst_clkgate_0" -name MISC_FILE [file join $::quartus(qip_path) "user_rst_clkgate_0.cmp"]
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "user_rst_clkgate_0" -name MISC_FILE [file join $::quartus(qip_path) "../user_rst_clkgate_0.ip"]
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_NAME "aW50ZWxfdXNlcl9yc3RfY2xrZ2F0ZQ=="
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_DISPLAY_NAME "UmVzZXQgUmVsZWFzZSBJUA=="
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_VERSION "MS4wLjE="
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_DESCRIPTION "VGhpcyBJUCBvdXRwdXRzIG5JTklUX0RPTkUgYWZ0ZXIgZmluaXNoaW5nIGRldmljZSBpbml0YWxpemF0aW9uLiBVc2VyIG1vZGUgaW5pdGlhbGl6YXRpb24gY2FuIGJlZ2luIGFzIHNvb24gYXMgdGhlIG5JTklUX0RPTkUgc2lnbmFsIGFzc2VydHMu"
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0NvbmZpZ3VyYXRpb24gYW5kIFByb2dyYW1taW5n"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_NAME "dXNlcl9yc3RfY2xrZ2F0ZV8w"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_AUTHOR "QWx0ZXJh"
set_global_assignment -entity "user_rst_clkgate_0" -library "user_rst_clkgate_0" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -library "intel_user_rst_clkgate_101" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate.sv"]
set_instance_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name SDC_ENTITY_FILE [file join $::quartus(qip_path) "intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate_agilex.sdc"] -no_sdc_promotion -no_auto_inst_discovery
set_global_assignment -library "user_rst_clkgate_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/user_rst_clkgate_0.v"]
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_TOOL_NAME "intel_user_rst_clkgate"
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_TOOL_VERSION "1.0.1"
set_global_assignment -entity "intel_user_rst_clkgate" -library "intel_user_rst_clkgate_101" -name IP_TOOL_ENV "QsysPrimePro"
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0.sopcinfo
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<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport
name="user_rst_clkgate_0"
kind="user_rst_clkgate_0"
version="1.0"
fabric="QSYS">
<!-- Format version 26.1 110 (Future versions may contain additional information.) -->
<!-- 2026.05.11.21:03:49 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>GENERATION_ID</sysinfo_type>
</parameter>
<parameter name="AUTO_UNIQUE_ID">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>UNIQUE_ID</sysinfo_type>
</parameter>
<parameter name="AUTO_DEVICE_FAMILY">
<type>java.lang.String</type>
<value>Agilex 5</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
</parameter>
<parameter name="AUTO_DEVICE">
<type>java.lang.String</type>
<value>A5EB013BB23BE4SCS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE</sysinfo_type>
</parameter>
<parameter name="AUTO_DEVICE_SPEEDGRADE">
<type>java.lang.String</type>
<value>4</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
</parameter>
<parameter name="AUTO_BOARD">
<type>java.lang.String</type>
<value>default</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>BOARD</sysinfo_type>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>Agilex 5</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<module
name="intel_user_rst_clkgate_inst"
kind="intel_user_rst_clkgate"
version="1.0.1"
entity="intel_user_rst_clkgate"
library="intel_user_rst_clkgate_101"
path="intel_user_rst_clkgate_inst"
hpath="intel_user_rst_clkgate_inst"
className="intel_user_rst_clkgate">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<parameter name="outputType">
<type>java.lang.String</type>
<value>Conduit Interface</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="DEVICE_FAMILY">
<type>java.lang.String</type>
<value>Agilex 5</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="ninit_done" kind="conduit_end" version="26.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="prSafe">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>conduit</type>
<span>0</span>
<isStart>false</isStart>
<port>
<name>ninit_done</name>
<direction>Output</direction>
<width>1</width>
<role>ninit_done</role>
</port>
</interface>
</module>
<plugin>
<instanceCount>1</instanceCount>
<name>intel_user_rst_clkgate</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Reset Release IP</displayName>
<version>1.0.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<version>26.1</version>
</plugin>
<reportVersion>26.1 110</reportVersion>
<uniqueIdentifier></uniqueIdentifier>
</EnsembleReport>
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0.xml
+113
View File
@@ -0,0 +1,113 @@
<?xml version="1.0" encoding="UTF-8"?>
<deploy
date="2026.05.11.21:03:49"
outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/">
<perimeter>
<parameter
name="AUTO_GENERATION_ID"
type="Integer"
defaultValue="0"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_UNIQUE_ID"
type="String"
defaultValue=""
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_FAMILY"
type="String"
defaultValue="Agilex 5"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE"
type="String"
defaultValue="A5EB013BB23BE4SCS"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_DEVICE_SPEEDGRADE"
type="String"
defaultValue="6"
onHdl="0"
affectsHdl="1" />
<parameter
name="AUTO_BOARD"
type="String"
defaultValue="default"
onHdl="0"
affectsHdl="1" />
<interface name="ninit_done" kind="conduit" start="0">
<property name="associatedClock" value="" />
<property name="associatedReset" value="" />
<property name="prSafe" value="false" />
<port name="ninit_done" direction="output" role="ninit_done" width="1" />
</interface>
</perimeter>
<entity kind="user_rst_clkgate_0" version="1.0" name="user_rst_clkgate_0">
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
<parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
<parameter name="AUTO_BOARD" value="default" />
<parameter name="AUTO_UNIQUE_ID" value="" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
<generatedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/synth/user_rst_clkgate_0.v"
attributes="CONTAINS_INLINE_CONFIGURATION" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/synth/user_rst_clkgate_0.v"
attributes="CONTAINS_INLINE_CONFIGURATION" />
</childGeneratedFiles>
<sourceFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0.ip" />
</sourceFiles>
<childSourceFiles>
<file
path="/opt/altera_pro/26.1/ip/altera/pgm/intel_user_rst_clkgate/intel_user_rst_clkgate_hw.tcl" />
</childSourceFiles>
<messages>
<message level="Info" culprit="user_rst_clkgate_0">"Generating: user_rst_clkgate_0"</message>
<message level="Info" culprit="user_rst_clkgate_0">"Generating: intel_user_rst_clkgate"</message>
<message level="Info" culprit="intel_user_rst_clkgate_inst">generating top-level entity intel_user_rst_clkgate</message>
</messages>
</entity>
<entity
kind="intel_user_rst_clkgate"
version="1.0.1"
name="intel_user_rst_clkgate">
<parameter name="DEVICE_FAMILY" value="Agilex 5" />
<parameter name="outputType" value="Conduit Interface" />
<generatedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate.sv"
attributes="TOP_LEVEL_FILE" />
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate_agilex.sdc"
attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
</generatedFiles>
<childGeneratedFiles>
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate.sv"
attributes="TOP_LEVEL_FILE" />
<file
path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0/intel_user_rst_clkgate_101/synth/intel_user_rst_clkgate_agilex.sdc"
attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
</childGeneratedFiles>
<sourceFiles>
<file
path="/opt/altera_pro/26.1/ip/altera/pgm/intel_user_rst_clkgate/intel_user_rst_clkgate_hw.tcl" />
</sourceFiles>
<childSourceFiles/>
<instantiator instantiator="user_rst_clkgate_0" as="intel_user_rst_clkgate_inst" />
<messages>
<message level="Info" culprit="user_rst_clkgate_0">"Generating: intel_user_rst_clkgate"</message>
<message level="Info" culprit="intel_user_rst_clkgate_inst">generating top-level entity intel_user_rst_clkgate</message>
</messages>
</entity>
</deploy>
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0_bb.v
+5
View File
@@ -0,0 +1,5 @@
module user_rst_clkgate_0 (
output wire ninit_done // ninit_done.ninit_done
);
endmodule
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0_generation.rpt
+12
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@@ -0,0 +1,12 @@
Info: Generated by version: 26.1 build 110
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: user_rst_clkgate_0.intel_user_rst_clkgate_inst: You are using the Reset Release IP called intel_user_rst_clkgate which is now no longer active in IP catalog. Please use the Reset Release IP named altera_s10_user_rst_clkgate.
Info: user_rst_clkgate_0: "Transforming system: user_rst_clkgate_0"
Info: user_rst_clkgate_0: "Naming system components in system: user_rst_clkgate_0"
Info: user_rst_clkgate_0: "Processing generation queue"
Info: user_rst_clkgate_0: "Generating: user_rst_clkgate_0"
Info: user_rst_clkgate_0: "Generating: intel_user_rst_clkgate"
Info: intel_user_rst_clkgate_inst: generating top-level entity intel_user_rst_clkgate
Info: user_rst_clkgate_0: Done "user_rst_clkgate_0" with 2 modules, 3 files
Info: Finished: Create HDL design files for synthesis
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0_generation_previous.rpt
+12
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@@ -0,0 +1,12 @@
Info: Generated by version: 25.3.1 build 100
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/ip/qsys_top/user_rst_clkgate_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: user_rst_clkgate_0.intel_user_rst_clkgate_inst: You are using the Reset Release IP called intel_user_rst_clkgate which is now no longer active in IP catalog. Please use the Reset Release IP named altera_s10_user_rst_clkgate.
Info: user_rst_clkgate_0: "Transforming system: user_rst_clkgate_0"
Info: user_rst_clkgate_0: "Naming system components in system: user_rst_clkgate_0"
Info: user_rst_clkgate_0: "Processing generation queue"
Info: user_rst_clkgate_0: "Generating: user_rst_clkgate_0"
Info: user_rst_clkgate_0: "Generating: intel_user_rst_clkgate"
Info: intel_user_rst_clkgate_inst: generating top-level entity intel_user_rst_clkgate
Info: user_rst_clkgate_0: Done "user_rst_clkgate_0" with 2 modules, 3 files
Info: Finished: Create HDL design files for synthesis
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0_inst.v
+4
View File
@@ -0,0 +1,4 @@
user_rst_clkgate_0 u0 (
.ninit_done (_connected_to_ninit_done_) // output, width = 1, ninit_done.ninit_done
);
qsys/ip/qsys_top/user_rst_clkgate_0/user_rst_clkgate_0_inst.vhd
+11
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@@ -0,0 +1,11 @@
component user_rst_clkgate_0 is
port (
ninit_done : out std_logic -- ninit_done
);
end component user_rst_clkgate_0;
u0 : component user_rst_clkgate_0
port map (
ninit_done => CONNECTED_TO_ninit_done -- ninit_done.ninit_done
);