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Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

Browse Source 
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-06-29 20:10:50 -04:00
commit ec82764bef
2462 changed files with 2174303 additions and 0 deletions
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qsys/ip/qsys_top/clk_100/clk_100.qip
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set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_VERSION "26.1"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_clock_bridge"
set_global_assignment -entity "clk_100" -library "clk_100" -name PRE_COMPILED_MODULE "ON"
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_FILE [file join $::quartus(qip_path) "../clk_100.ip"]
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_TYPE "altera_clock_bridge"
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_VERSION "19.2.0"
set_global_assignment -entity "clk_100" -library "clk_100" -name OCS_IP_HASH "njakcna"
set_global_assignment -library "clk_100" -name SOPCINFO_FILE [file join $::quartus(qip_path) "clk_100.sopcinfo"]
set_global_assignment -entity "clk_100" -library "clk_100" -name SLD_INFO "QSYS_NAME clk_100 HAS_SOPCINFO 1 GENERATION_ID 0"
set_global_assignment -library "clk_100" -name MISC_FILE [file join $::quartus(qip_path) "clk_100.cmp"]
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "clk_100" -name MISC_FILE [file join $::quartus(qip_path) "../clk_100.ip"]
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_NAME "Y2xrXzEwMA=="
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "clk_100" -library "clk_100" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -library "clk_100" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/clk_100.v"]