Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2026 Altera Corporation. All rights reserved.
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
the Altera IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Altera and sold by Altera or its authorized distributors. Please
|
||||
refer to the Altera Software License Subscription Agreements
|
||||
on the Quartus Prime software download page.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 440 2064)
|
||||
(text "emif_io96b_hps" (rect 169 0 232 12)(font "SansSerif" (font_size 11)))
|
||||
(text "inst" (rect 8 2048 20 2060)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 126)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_awaddr[26..0]" (rect 0 0 120 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_awaddr[26..0]" (rect 4 115 178 126)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 126)(pt 170 126)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 151)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_awvalid" (rect 0 0 95 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_awvalid" (rect 4 140 142 151)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 151)(pt 170 151)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 201)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_araddr[26..0]" (rect 0 0 118 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_araddr[26..0]" (rect 4 190 178 201)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 201)(pt 170 201)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 226)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_arvalid" (rect 0 0 93 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_arvalid" (rect 4 215 142 226)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 226)(pt 170 226)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 276)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_wdata[31..0]" (rect 0 0 113 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_wdata[31..0]" (rect 4 265 172 276)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 276)(pt 170 276)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 301)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_wvalid" (rect 0 0 90 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_wvalid" (rect 4 290 136 301)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 301)(pt 170 301)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 426)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_rready" (rect 0 0 94 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_rready" (rect 4 415 136 426)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 426)(pt 170 426)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 501)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_bready" (rect 0 0 95 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_bready" (rect 4 490 136 501)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 501)(pt 170 501)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 526)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_awprot[2..0]" (rect 0 0 113 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_awprot[2..0]" (rect 4 515 172 526)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 526)(pt 170 526)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 551)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_arprot[2..0]" (rect 0 0 110 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_arprot[2..0]" (rect 4 540 172 551)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 551)(pt 170 551)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 576)
|
||||
(input)
|
||||
(text "s0_noc_axi4lite_wstrb[3..0]" (rect 0 0 108 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_wstrb[3..0]" (rect 4 565 166 576)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 576)(pt 170 576)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 601)
|
||||
(input)
|
||||
(text "s0_axi4_awaddr[39..0]" (rect 0 0 90 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awaddr[39..0]" (rect 4 590 130 601)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 601)(pt 170 601)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 626)
|
||||
(input)
|
||||
(text "s0_axi4_awburst[1..0]" (rect 0 0 87 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awburst[1..0]" (rect 4 615 130 626)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 626)(pt 170 626)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 651)
|
||||
(input)
|
||||
(text "s0_axi4_awid[6..0]" (rect 0 0 74 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awid[6..0]" (rect 4 640 112 651)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 651)(pt 170 651)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 676)
|
||||
(input)
|
||||
(text "s0_axi4_awlen[7..0]" (rect 0 0 79 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awlen[7..0]" (rect 4 665 118 676)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 676)(pt 170 676)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 701)
|
||||
(input)
|
||||
(text "s0_axi4_awlock" (rect 0 0 63 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awlock" (rect 4 690 88 701)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 701)(pt 170 701)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 726)
|
||||
(input)
|
||||
(text "s0_axi4_awqos[3..0]" (rect 0 0 82 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awqos[3..0]" (rect 4 715 118 726)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 726)(pt 170 726)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 751)
|
||||
(input)
|
||||
(text "s0_axi4_awsize[2..0]" (rect 0 0 82 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awsize[2..0]" (rect 4 740 124 751)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 751)(pt 170 751)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 776)
|
||||
(input)
|
||||
(text "s0_axi4_awvalid" (rect 0 0 66 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awvalid" (rect 4 765 94 776)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 776)(pt 170 776)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 801)
|
||||
(input)
|
||||
(text "s0_axi4_awuser[13..0]" (rect 0 0 89 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awuser[13..0]" (rect 4 790 130 801)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 801)(pt 170 801)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 826)
|
||||
(input)
|
||||
(text "s0_axi4_awprot[2..0]" (rect 0 0 83 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awprot[2..0]" (rect 4 815 124 826)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 826)(pt 170 826)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 876)
|
||||
(input)
|
||||
(text "s0_axi4_araddr[39..0]" (rect 0 0 88 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_araddr[39..0]" (rect 4 865 130 876)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 876)(pt 170 876)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 901)
|
||||
(input)
|
||||
(text "s0_axi4_arburst[1..0]" (rect 0 0 84 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arburst[1..0]" (rect 4 890 130 901)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 901)(pt 170 901)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 926)
|
||||
(input)
|
||||
(text "s0_axi4_arid[6..0]" (rect 0 0 71 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arid[6..0]" (rect 4 915 112 926)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 926)(pt 170 926)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 951)
|
||||
(input)
|
||||
(text "s0_axi4_arlen[7..0]" (rect 0 0 76 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arlen[7..0]" (rect 4 940 118 951)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 951)(pt 170 951)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 976)
|
||||
(input)
|
||||
(text "s0_axi4_arlock" (rect 0 0 61 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arlock" (rect 4 965 88 976)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 976)(pt 170 976)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 1001)
|
||||
(input)
|
||||
(text "s0_axi4_arqos[3..0]" (rect 0 0 80 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arqos[3..0]" (rect 4 990 118 1001)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1001)(pt 170 1001)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1026)
|
||||
(input)
|
||||
(text "s0_axi4_arsize[2..0]" (rect 0 0 80 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arsize[2..0]" (rect 4 1015 124 1026)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1026)(pt 170 1026)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1051)
|
||||
(input)
|
||||
(text "s0_axi4_arvalid" (rect 0 0 63 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arvalid" (rect 4 1040 94 1051)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1051)(pt 170 1051)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 1076)
|
||||
(input)
|
||||
(text "s0_axi4_aruser[13..0]" (rect 0 0 87 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_aruser[13..0]" (rect 4 1065 130 1076)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1076)(pt 170 1076)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1101)
|
||||
(input)
|
||||
(text "s0_axi4_arprot[2..0]" (rect 0 0 81 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arprot[2..0]" (rect 4 1090 124 1101)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1101)(pt 170 1101)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1151)
|
||||
(input)
|
||||
(text "s0_axi4_wdata[255..0]" (rect 0 0 89 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_wdata[255..0]" (rect 4 1140 130 1151)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1151)(pt 170 1151)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1176)
|
||||
(input)
|
||||
(text "s0_axi4_wstrb[31..0]" (rect 0 0 82 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_wstrb[31..0]" (rect 4 1165 124 1176)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1176)(pt 170 1176)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1201)
|
||||
(input)
|
||||
(text "s0_axi4_wlast" (rect 0 0 56 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_wlast" (rect 4 1190 82 1201)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1201)(pt 170 1201)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 1226)
|
||||
(input)
|
||||
(text "s0_axi4_wvalid" (rect 0 0 61 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_wvalid" (rect 4 1215 88 1226)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1226)(pt 170 1226)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 1276)
|
||||
(input)
|
||||
(text "s0_axi4_bready" (rect 0 0 66 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_bready" (rect 4 1265 88 1276)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1276)(pt 170 1276)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 1376)
|
||||
(input)
|
||||
(text "s0_axi4_rready" (rect 0 0 64 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_rready" (rect 4 1365 88 1376)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1376)(pt 170 1376)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 1576)
|
||||
(input)
|
||||
(text "s0_axi4_wuser[31..0]" (rect 0 0 84 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_wuser[31..0]" (rect 4 1565 124 1576)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1576)(pt 170 1576)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1976)
|
||||
(input)
|
||||
(text "oct_rzqin_0" (rect 0 0 46 12)(font "SansSerif" (font_size 8)))
|
||||
(text "oct_rzqin_0" (rect 4 1965 70 1976)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1976)(pt 170 1976)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 2026)
|
||||
(input)
|
||||
(text "ref_clk" (rect 0 0 28 12)(font "SansSerif" (font_size 8)))
|
||||
(text "ref_clk" (rect 4 2015 46 2026)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 2026)(pt 170 2026)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 76)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_clock" (rect 0 0 87 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_clock" (rect 4 65 130 76)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 101)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_reset_n" (rect 0 0 97 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_reset_n" (rect 4 90 142 101)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_awready" (rect 0 0 101 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_awready" (rect 4 165 142 176)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 251)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_arready" (rect 0 0 99 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_arready" (rect 4 240 142 251)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 326)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_wready" (rect 0 0 96 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_wready" (rect 4 315 136 326)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 351)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_rresp[1..0]" (rect 0 0 107 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_rresp[1..0]" (rect 4 340 166 351)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 376)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_rdata[31..0]" (rect 0 0 110 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_rdata[31..0]" (rect 4 365 172 376)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 401)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_rvalid" (rect 0 0 88 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_rvalid" (rect 4 390 136 401)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 451)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_bresp[1..0]" (rect 0 0 108 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_bresp[1..0]" (rect 4 440 166 451)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 476)
|
||||
(output)
|
||||
(text "s0_noc_axi4lite_bvalid" (rect 0 0 89 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_noc_axi4lite_bvalid" (rect 4 465 136 476)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 851)
|
||||
(output)
|
||||
(text "s0_axi4_awready" (rect 0 0 71 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_awready" (rect 4 840 94 851)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1126)
|
||||
(output)
|
||||
(text "s0_axi4_arready" (rect 0 0 69 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_arready" (rect 4 1115 94 1126)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1251)
|
||||
(output)
|
||||
(text "s0_axi4_wready" (rect 0 0 67 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_wready" (rect 4 1240 88 1251)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1301)
|
||||
(output)
|
||||
(text "s0_axi4_bid[6..0]" (rect 0 0 68 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_bid[6..0]" (rect 4 1290 106 1301)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1326)
|
||||
(output)
|
||||
(text "s0_axi4_bresp[1..0]" (rect 0 0 79 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_bresp[1..0]" (rect 4 1315 118 1326)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1351)
|
||||
(output)
|
||||
(text "s0_axi4_bvalid" (rect 0 0 60 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_bvalid" (rect 4 1340 88 1351)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1401)
|
||||
(output)
|
||||
(text "s0_axi4_rdata[255..0]" (rect 0 0 87 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_rdata[255..0]" (rect 4 1390 130 1401)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1426)
|
||||
(output)
|
||||
(text "s0_axi4_rid[6..0]" (rect 0 0 67 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_rid[6..0]" (rect 4 1415 106 1426)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1451)
|
||||
(output)
|
||||
(text "s0_axi4_rlast" (rect 0 0 54 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_rlast" (rect 4 1440 82 1451)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1476)
|
||||
(output)
|
||||
(text "s0_axi4_rresp[1..0]" (rect 0 0 77 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_rresp[1..0]" (rect 4 1465 118 1476)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1501)
|
||||
(output)
|
||||
(text "s0_axi4_rvalid" (rect 0 0 59 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_rvalid" (rect 4 1490 88 1501)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1526)
|
||||
(output)
|
||||
(text "noc_aclk_0" (rect 0 0 46 12)(font "SansSerif" (font_size 8)))
|
||||
(text "noc_aclk_0" (rect 4 1515 64 1526)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1551)
|
||||
(output)
|
||||
(text "noc_rst_n_0" (rect 0 0 51 12)(font "SansSerif" (font_size 8)))
|
||||
(text "noc_rst_n_0" (rect 4 1540 70 1551)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1601)
|
||||
(output)
|
||||
(text "s0_axi4_ruser[31..0]" (rect 0 0 82 12)(font "SansSerif" (font_size 8)))
|
||||
(text "s0_axi4_ruser[31..0]" (rect 4 1590 124 1601)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1651)
|
||||
(output)
|
||||
(text "mem_0_cs" (rect 0 0 47 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_cs" (rect 4 1640 52 1651)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1676)
|
||||
(output)
|
||||
(text "mem_0_ca[5..0]" (rect 0 0 67 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_ca[5..0]" (rect 4 1665 88 1676)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1701)
|
||||
(output)
|
||||
(text "mem_0_cke" (rect 0 0 51 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_cke" (rect 4 1690 58 1701)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1851)
|
||||
(output)
|
||||
(text "mem_0_ck_t" (rect 0 0 55 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_ck_t" (rect 4 1840 64 1851)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1876)
|
||||
(output)
|
||||
(text "mem_0_ck_c" (rect 0 0 57 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_ck_c" (rect 4 1865 64 1876)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1926)
|
||||
(output)
|
||||
(text "mem_0_reset_n" (rect 0 0 68 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_reset_n" (rect 4 1915 82 1926)(font "SansSerif" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 0 1726)
|
||||
(bidir)
|
||||
(text "mem_0_dq[31..0]" (rect 0 0 70 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dq[31..0]" (rect 4 1715 94 1726)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1726)(pt 170 1726)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1751)
|
||||
(bidir)
|
||||
(text "mem_0_dqs_t[3..0]" (rect 0 0 80 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dqs_t[3..0]" (rect 4 1740 106 1751)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1751)(pt 170 1751)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1776)
|
||||
(bidir)
|
||||
(text "mem_0_dqs_c[3..0]" (rect 0 0 82 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dqs_c[3..0]" (rect 4 1765 106 1776)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1776)(pt 170 1776)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 1801)
|
||||
(bidir)
|
||||
(text "mem_0_dmi[3..0]" (rect 0 0 71 12)(font "SansSerif" (font_size 8)))
|
||||
(text "mem_0_dmi[3..0]" (rect 4 1790 94 1801)(font "SansSerif" (font_size 8)))
|
||||
(line (pt 0 1801)(pt 170 1801)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "io96b0_to_hps" (rect 85 46 248 105)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "ch0_axil_clk" (rect 175 71 422 152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_reset_n" (rect 175 96 446 202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_awaddr" (rect 175 121 440 252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_awvalid" (rect 175 146 446 302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_awready" (rect 175 171 446 352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_araddr" (rect 175 196 440 402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_arvalid" (rect 175 221 446 452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_arready" (rect 175 246 446 502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_wdata" (rect 175 271 434 552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_wvalid" (rect 175 296 440 602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_wready" (rect 175 321 440 652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_rresp" (rect 175 346 434 702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_rdata" (rect 175 371 434 752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_rvalid" (rect 175 396 440 802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_rready" (rect 175 421 440 852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_bresp" (rect 175 446 434 902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_bvalid" (rect 175 471 440 952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_bready" (rect 175 496 440 1002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_awprot" (rect 175 521 440 1052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_arprot" (rect 175 546 440 1102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ch0_axil_wstrb" (rect 175 571 434 1152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awaddr" (rect 175 596 440 1202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awburst" (rect 175 621 446 1252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awid" (rect 175 646 428 1302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awlen" (rect 175 671 434 1352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awlock" (rect 175 696 440 1402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awqos" (rect 175 721 434 1452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awsize" (rect 175 746 440 1502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awvalid" (rect 175 771 446 1552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awuser" (rect 175 796 440 1602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awprot" (rect 175 821 440 1652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_awready" (rect 175 846 446 1702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_araddr" (rect 175 871 440 1752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arburst" (rect 175 896 446 1802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arid" (rect 175 921 428 1852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arlen" (rect 175 946 434 1902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arlock" (rect 175 971 440 1952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arqos" (rect 175 996 434 2002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arsize" (rect 175 1021 440 2052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arvalid" (rect 175 1046 446 2102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_aruser" (rect 175 1071 440 2152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arprot" (rect 175 1096 440 2202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_arready" (rect 175 1121 446 2252)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_wdata" (rect 175 1146 434 2302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_wstrb" (rect 175 1171 434 2352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_wlast" (rect 175 1196 434 2402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_wvalid" (rect 175 1221 440 2452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_wready" (rect 175 1246 440 2502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_bready" (rect 175 1271 440 2552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_bid" (rect 175 1296 422 2602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_bresp" (rect 175 1321 434 2652)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_bvalid" (rect 175 1346 440 2702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_rready" (rect 175 1371 440 2752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_rdata" (rect 175 1396 434 2802)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_rid" (rect 175 1421 422 2852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_rlast" (rect 175 1446 434 2902)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_rresp" (rect 175 1471 434 2952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_rvalid" (rect 175 1496 440 3002)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_clk" (rect 175 1521 422 3052)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_reset_n" (rect 175 1546 446 3102)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_wuser" (rect 175 1571 434 3152)(font "SansSerif" (color 0 0 0)))
|
||||
(text "axi4_ch0_ruser" (rect 175 1596 434 3202)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_0" (rect 127 1621 284 3255)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_cs" (rect 175 1646 386 3302)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ca" (rect 175 1671 386 3352)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_cke" (rect 175 1696 392 3402)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dq" (rect 175 1721 386 3452)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dqs_t" (rect 175 1746 404 3502)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dqs_c" (rect 175 1771 404 3552)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_dmi" (rect 175 1796 392 3602)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ck_0" (rect 106 1821 260 3655)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_ck_t" (rect 175 1846 398 3702)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_ck_c" (rect 175 1871 398 3752)(font "SansSerif" (color 0 0 0)))
|
||||
(text "mem_reset_n" (rect 89 1896 244 3805)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "mem_reset_n" (rect 175 1921 416 3852)(font "SansSerif" (color 0 0 0)))
|
||||
(text "oct_0" (rect 139 1946 308 3905)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "oct_rzqin" (rect 175 1971 404 3952)(font "SansSerif" (color 0 0 0)))
|
||||
(text "ref_clk" (rect 130 1996 302 4005)(font "SansSerif" (color 128 0 0)(font_size 9)))
|
||||
(text "clk" (rect 175 2021 368 4052)(font "SansSerif" (color 0 0 0)))
|
||||
(text " emif_io96b_hps " (rect 371 2051 838 4112)(font "SansSerif" ))
|
||||
(line (pt 170 34)(pt 272 34)(line_width 1))
|
||||
(line (pt 272 34)(pt 272 2051)(line_width 1))
|
||||
(line (pt 170 2051)(pt 272 2051)(line_width 1))
|
||||
(line (pt 170 34)(pt 170 2051)(line_width 1))
|
||||
(line (pt 440 76)(pt 170 76)(line_width 1))
|
||||
(line (pt 440 101)(pt 170 101)(line_width 1))
|
||||
(line (pt 440 176)(pt 170 176)(line_width 1))
|
||||
(line (pt 440 251)(pt 170 251)(line_width 1))
|
||||
(line (pt 440 326)(pt 170 326)(line_width 1))
|
||||
(line (pt 440 351)(pt 170 351)(line_width 3))
|
||||
(line (pt 440 376)(pt 170 376)(line_width 3))
|
||||
(line (pt 440 401)(pt 170 401)(line_width 1))
|
||||
(line (pt 440 451)(pt 170 451)(line_width 3))
|
||||
(line (pt 440 476)(pt 170 476)(line_width 1))
|
||||
(line (pt 440 851)(pt 170 851)(line_width 1))
|
||||
(line (pt 440 1126)(pt 170 1126)(line_width 1))
|
||||
(line (pt 440 1251)(pt 170 1251)(line_width 1))
|
||||
(line (pt 440 1301)(pt 170 1301)(line_width 3))
|
||||
(line (pt 440 1326)(pt 170 1326)(line_width 3))
|
||||
(line (pt 440 1351)(pt 170 1351)(line_width 1))
|
||||
(line (pt 440 1401)(pt 170 1401)(line_width 3))
|
||||
(line (pt 440 1426)(pt 170 1426)(line_width 3))
|
||||
(line (pt 440 1451)(pt 170 1451)(line_width 1))
|
||||
(line (pt 440 1476)(pt 170 1476)(line_width 3))
|
||||
(line (pt 440 1501)(pt 170 1501)(line_width 1))
|
||||
(line (pt 440 1526)(pt 170 1526)(line_width 1))
|
||||
(line (pt 440 1551)(pt 170 1551)(line_width 1))
|
||||
(line (pt 440 1601)(pt 170 1601)(line_width 3))
|
||||
(line (pt 171 55)(pt 171 1605)(line_width 1))
|
||||
(line (pt 172 55)(pt 172 1605)(line_width 1))
|
||||
(line (pt 440 1651)(pt 170 1651)(line_width 1))
|
||||
(line (pt 440 1676)(pt 170 1676)(line_width 3))
|
||||
(line (pt 440 1701)(pt 170 1701)(line_width 1))
|
||||
(line (pt 171 1630)(pt 171 1805)(line_width 1))
|
||||
(line (pt 172 1630)(pt 172 1805)(line_width 1))
|
||||
(line (pt 440 1851)(pt 170 1851)(line_width 1))
|
||||
(line (pt 440 1876)(pt 170 1876)(line_width 1))
|
||||
(line (pt 171 1830)(pt 171 1880)(line_width 1))
|
||||
(line (pt 172 1830)(pt 172 1880)(line_width 1))
|
||||
(line (pt 440 1926)(pt 170 1926)(line_width 1))
|
||||
(line (pt 171 1905)(pt 171 1930)(line_width 1))
|
||||
(line (pt 172 1905)(pt 172 1930)(line_width 1))
|
||||
(line (pt 171 1955)(pt 171 1980)(line_width 1))
|
||||
(line (pt 172 1955)(pt 172 1980)(line_width 1))
|
||||
(line (pt 171 2005)(pt 171 2030)(line_width 1))
|
||||
(line (pt 172 2005)(pt 172 2030)(line_width 1))
|
||||
(line (pt 0 0)(pt 440 0)(line_width 1))
|
||||
(line (pt 440 0)(pt 440 2068)(line_width 1))
|
||||
(line (pt 0 2068)(pt 440 2068)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 2068)(line_width 1))
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,79 @@
|
||||
component emif_io96b_hps is
|
||||
port (
|
||||
s0_noc_axi4lite_clock : out std_logic; -- ch0_axil_clk
|
||||
s0_noc_axi4lite_reset_n : out std_logic; -- ch0_axil_reset_n
|
||||
s0_noc_axi4lite_awaddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- ch0_axil_awaddr
|
||||
s0_noc_axi4lite_awvalid : in std_logic := 'X'; -- ch0_axil_awvalid
|
||||
s0_noc_axi4lite_awready : out std_logic; -- ch0_axil_awready
|
||||
s0_noc_axi4lite_araddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- ch0_axil_araddr
|
||||
s0_noc_axi4lite_arvalid : in std_logic := 'X'; -- ch0_axil_arvalid
|
||||
s0_noc_axi4lite_arready : out std_logic; -- ch0_axil_arready
|
||||
s0_noc_axi4lite_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- ch0_axil_wdata
|
||||
s0_noc_axi4lite_wvalid : in std_logic := 'X'; -- ch0_axil_wvalid
|
||||
s0_noc_axi4lite_wready : out std_logic; -- ch0_axil_wready
|
||||
s0_noc_axi4lite_rresp : out std_logic_vector(1 downto 0); -- ch0_axil_rresp
|
||||
s0_noc_axi4lite_rdata : out std_logic_vector(31 downto 0); -- ch0_axil_rdata
|
||||
s0_noc_axi4lite_rvalid : out std_logic; -- ch0_axil_rvalid
|
||||
s0_noc_axi4lite_rready : in std_logic := 'X'; -- ch0_axil_rready
|
||||
s0_noc_axi4lite_bresp : out std_logic_vector(1 downto 0); -- ch0_axil_bresp
|
||||
s0_noc_axi4lite_bvalid : out std_logic; -- ch0_axil_bvalid
|
||||
s0_noc_axi4lite_bready : in std_logic := 'X'; -- ch0_axil_bready
|
||||
s0_noc_axi4lite_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- ch0_axil_awprot
|
||||
s0_noc_axi4lite_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- ch0_axil_arprot
|
||||
s0_noc_axi4lite_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- ch0_axil_wstrb
|
||||
s0_axi4_awaddr : in std_logic_vector(39 downto 0) := (others => 'X'); -- axi4_ch0_awaddr
|
||||
s0_axi4_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- axi4_ch0_awburst
|
||||
s0_axi4_awid : in std_logic_vector(6 downto 0) := (others => 'X'); -- axi4_ch0_awid
|
||||
s0_axi4_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- axi4_ch0_awlen
|
||||
s0_axi4_awlock : in std_logic := 'X'; -- axi4_ch0_awlock
|
||||
s0_axi4_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- axi4_ch0_awqos
|
||||
s0_axi4_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_awsize
|
||||
s0_axi4_awvalid : in std_logic := 'X'; -- axi4_ch0_awvalid
|
||||
s0_axi4_awuser : in std_logic_vector(13 downto 0) := (others => 'X'); -- axi4_ch0_awuser
|
||||
s0_axi4_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_awprot
|
||||
s0_axi4_awready : out std_logic; -- axi4_ch0_awready
|
||||
s0_axi4_araddr : in std_logic_vector(39 downto 0) := (others => 'X'); -- axi4_ch0_araddr
|
||||
s0_axi4_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- axi4_ch0_arburst
|
||||
s0_axi4_arid : in std_logic_vector(6 downto 0) := (others => 'X'); -- axi4_ch0_arid
|
||||
s0_axi4_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- axi4_ch0_arlen
|
||||
s0_axi4_arlock : in std_logic := 'X'; -- axi4_ch0_arlock
|
||||
s0_axi4_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- axi4_ch0_arqos
|
||||
s0_axi4_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_arsize
|
||||
s0_axi4_arvalid : in std_logic := 'X'; -- axi4_ch0_arvalid
|
||||
s0_axi4_aruser : in std_logic_vector(13 downto 0) := (others => 'X'); -- axi4_ch0_aruser
|
||||
s0_axi4_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_arprot
|
||||
s0_axi4_arready : out std_logic; -- axi4_ch0_arready
|
||||
s0_axi4_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- axi4_ch0_wdata
|
||||
s0_axi4_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- axi4_ch0_wstrb
|
||||
s0_axi4_wlast : in std_logic := 'X'; -- axi4_ch0_wlast
|
||||
s0_axi4_wvalid : in std_logic := 'X'; -- axi4_ch0_wvalid
|
||||
s0_axi4_wready : out std_logic; -- axi4_ch0_wready
|
||||
s0_axi4_bready : in std_logic := 'X'; -- axi4_ch0_bready
|
||||
s0_axi4_bid : out std_logic_vector(6 downto 0); -- axi4_ch0_bid
|
||||
s0_axi4_bresp : out std_logic_vector(1 downto 0); -- axi4_ch0_bresp
|
||||
s0_axi4_bvalid : out std_logic; -- axi4_ch0_bvalid
|
||||
s0_axi4_rready : in std_logic := 'X'; -- axi4_ch0_rready
|
||||
s0_axi4_rdata : out std_logic_vector(255 downto 0); -- axi4_ch0_rdata
|
||||
s0_axi4_rid : out std_logic_vector(6 downto 0); -- axi4_ch0_rid
|
||||
s0_axi4_rlast : out std_logic; -- axi4_ch0_rlast
|
||||
s0_axi4_rresp : out std_logic_vector(1 downto 0); -- axi4_ch0_rresp
|
||||
s0_axi4_rvalid : out std_logic; -- axi4_ch0_rvalid
|
||||
noc_aclk_0 : out std_logic; -- axi4_ch0_clk
|
||||
noc_rst_n_0 : out std_logic; -- axi4_ch0_reset_n
|
||||
s0_axi4_wuser : in std_logic_vector(31 downto 0) := (others => 'X'); -- axi4_ch0_wuser
|
||||
s0_axi4_ruser : out std_logic_vector(31 downto 0); -- axi4_ch0_ruser
|
||||
mem_0_cs : out std_logic_vector(0 downto 0); -- mem_cs
|
||||
mem_0_ca : out std_logic_vector(5 downto 0); -- mem_ca
|
||||
mem_0_cke : out std_logic_vector(0 downto 0); -- mem_cke
|
||||
mem_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
|
||||
mem_0_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
|
||||
mem_0_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
|
||||
mem_0_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
|
||||
mem_0_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
|
||||
mem_0_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
|
||||
mem_0_reset_n : out std_logic; -- mem_reset_n
|
||||
oct_rzqin_0 : in std_logic := 'X'; -- oct_rzqin
|
||||
ref_clk : in std_logic := 'X' -- clk
|
||||
);
|
||||
end component emif_io96b_hps;
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
# system info emif_io96b_hps on 2026.04.08.10:53:37
|
||||
system_info:
|
||||
name,value
|
||||
DEVICE,A5EB013BB23BE4SCS
|
||||
DEVICE_FAMILY,Agilex 5
|
||||
GENERATION_ID,0
|
||||
#
|
||||
#
|
||||
# Files generated for emif_io96b_hps on 2026.04.08.10:53:37
|
||||
files:
|
||||
filepath,kind,attributes,module,is_top
|
||||
sim/emif_io96b_hps.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,emif_io96b_hps,true
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.sopcinfo,OTHER,,emif_io96b_hps_emif_io96b_hps_420_dyxenzq,false
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.sopcinfo,OTHER,,emif_io96b_hps_emif_io96b_hps_420_dyxenzq,false
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.sopcinfo,OTHER,,emif_io96b_hps_emif_io96b_hps_420_dyxenzq,false
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.sopcinfo,OTHER,,emif_io96b_hps_emif_io96b_hps_420_dyxenzq,false
|
||||
#
|
||||
# Map from instance-path to kind of module
|
||||
instances:
|
||||
instancePath,module
|
||||
emif_io96b_hps.emif_io96b_hps,emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
|
@@ -0,0 +1,145 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for emif_io96b_hps</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">emif_io96b_hps</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.05.11.21:04:08</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_emif_io96b_hps"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>emif_io96b_hps</h2>emif_io96b_hps v4.2.0
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">EMIF_PROTOCOL</td>
|
||||
<td class="parametervalue">LPDDR4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EMIF_TOPOLOGY</td>
|
||||
<td class="parametervalue">1x32</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">EMIF_REF_CLK_SHARING</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,67 @@
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TOOL_NAME "QsysPrimePro"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TOOL_VERSION "26.1"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TOOL_VENDOR_NAME "Altera Corporation"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TOP_LEVEL_COMPONENT_NAME "emif_io96b_hps"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name PRE_COMPILED_MODULE "ON"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name OCS_IP_FILE [file join $::quartus(qip_path) "../emif_io96b_hps.ip"]
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name OCS_IP_TYPE "emif_io96b_hps"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name OCS_IP_VERSION "4.2.0"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name OCS_IP_HASH "dyxenzq"
|
||||
set_global_assignment -library "emif_io96b_hps" -name SOPCINFO_FILE [file join $::quartus(qip_path) "emif_io96b_hps.sopcinfo"]
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name SLD_INFO "QSYS_NAME emif_io96b_hps HAS_SOPCINFO 1 GENERATION_ID 0"
|
||||
set_global_assignment -library "emif_io96b_hps" -name MISC_FILE [file join $::quartus(qip_path) "emif_io96b_hps.cmp"]
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TARGETED_PART_TRAIT "part.DEVICE_TEMPERATURE_GRADE::EXTENDED"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TARGETED_PART_TRAIT "part.DEVICE_POWER_MODEL::STANDARD_POWER_FIXED"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TARGETED_PART_TRAIT "part.SUPPORTS_VID::0"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TARGETED_PART_TRAIT "part.DEVICE_IOBANK_REVISION::IO96B_REVB1"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_TARGETED_PART_TRAIT "BASE_DEVICE::SM4REVB"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "emif_io96b_hps" -name MISC_FILE [file join $::quartus(qip_path) "../emif_io96b_hps.ip"]
|
||||
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_NAME "ZW1pZl9pbzk2Yl9ocHNfZW1pZl9pbzk2Yl9ocHNfNDIwX2R5eGVuenE="
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_DISPLAY_NAME "RXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZXMgZm9yIEhQUyBJUA=="
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_VERSION "NC4yLjA="
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIEV4dGVybmFsIE1lbW9yeSBJbnRlcmZhY2VzIElQIGZvciBIYXJkIFByb2Nlc3NvciBTeXN0ZW0="
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvSGFyZCBQcm9jZXNzb3IgQ29tcG9uZW50cw=="
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzc3MjUzOC5odG1s"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzc3MjYzNS5odG1s"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzgxNzQ2Ny5odG1s"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL2RvY3MvcHJvZ3JhbW1hYmxlLzgxNzM5Ni5odG1s"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_COMPONENT_NAME "ZW1pZl9pbzk2Yl9ocHM="
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "emif_io96b_hps" -library "emif_io96b_hps" -name IP_COMPONENT_VERSION "MS4w"
|
||||
|
||||
set_instance_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IO_STANDARD "1.1V True Differential Signaling" -to "ref_clk"
|
||||
set_instance_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name INPUT_TERMINATION "DIFFERENTIAL" -to "ref_clk"
|
||||
set_instance_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name HPS_EMIF_BANK_LOCATION PRIMARY -to emif_0_lpddr4|emif_0_lpddr4|emif_arch_top|io0.calip_0|cal_0|cal_arch_0|u_iossm|iossm
|
||||
|
||||
set_instance_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name HPS_EMIF_BANK_LOCATION PRIMARY -to emif_0_lpddr4|emif_0_lpddr4|emif_arch_top|io0.calip_0|cal_0|gen_tniu.tniu|tniu|target_0.target_lite_inst_0
|
||||
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name HPS_ISW_EMIF "HPS_IO_NUM 1 HPS_IO_CONFIG 1x32 IO96B0_PLL 1 MEM_CHANNEL_CAPACITY_GBITS 8.0"
|
||||
|
||||
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name QIP_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qip"]
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.sopcinfo"]
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name QIP_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.qip"]
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.sopcinfo"]
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name QIP_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.qip"]
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.sopcinfo"]
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name SOURCE_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.sopcinfo"]
|
||||
set_global_assignment -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name QIP_FILE [file join $::quartus(qip_path) "emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.qip"]
|
||||
set_global_assignment -library "emif_io96b_hps" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/emif_io96b_hps.v"]
|
||||
|
||||
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_TOOL_NAME "emif_io96b_hps"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_TOOL_VERSION "4.2.0"
|
||||
set_global_assignment -entity "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -library "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" -name IP_TOOL_ENV "QsysPrimePro"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,28 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<simPackage>
|
||||
<file
|
||||
path="emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.sopcinfo"
|
||||
type="OTHER"
|
||||
library="emif_io96b_hps_emif_io96b_hps_420_dyxenzq" />
|
||||
<file
|
||||
path="emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.sopcinfo"
|
||||
type="OTHER"
|
||||
library="emif_io96b_hps_emif_io96b_hps_420_dyxenzq" />
|
||||
<file
|
||||
path="emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.sopcinfo"
|
||||
type="OTHER"
|
||||
library="emif_io96b_hps_emif_io96b_hps_420_dyxenzq" />
|
||||
<file
|
||||
path="emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.sopcinfo"
|
||||
type="OTHER"
|
||||
library="emif_io96b_hps_emif_io96b_hps_420_dyxenzq" />
|
||||
<file
|
||||
path="sim/emif_io96b_hps.v"
|
||||
type="VERILOG"
|
||||
library="emif_io96b_hps"
|
||||
hasInlineConfiguration="true"
|
||||
isSubsystemWrapper="true" />
|
||||
<topLevel name="emif_io96b_hps.emif_io96b_hps" />
|
||||
<deviceFamily name="agilex5" />
|
||||
<device name="A5EB013BB23BE4SCS" />
|
||||
</simPackage>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,78 @@
|
||||
module emif_io96b_hps (
|
||||
output wire s0_noc_axi4lite_clock, // io96b0_to_hps.ch0_axil_clk
|
||||
output wire s0_noc_axi4lite_reset_n, // .ch0_axil_reset_n
|
||||
input wire [26:0] s0_noc_axi4lite_awaddr, // .ch0_axil_awaddr
|
||||
input wire s0_noc_axi4lite_awvalid, // .ch0_axil_awvalid
|
||||
output wire s0_noc_axi4lite_awready, // .ch0_axil_awready
|
||||
input wire [26:0] s0_noc_axi4lite_araddr, // .ch0_axil_araddr
|
||||
input wire s0_noc_axi4lite_arvalid, // .ch0_axil_arvalid
|
||||
output wire s0_noc_axi4lite_arready, // .ch0_axil_arready
|
||||
input wire [31:0] s0_noc_axi4lite_wdata, // .ch0_axil_wdata
|
||||
input wire s0_noc_axi4lite_wvalid, // .ch0_axil_wvalid
|
||||
output wire s0_noc_axi4lite_wready, // .ch0_axil_wready
|
||||
output wire [1:0] s0_noc_axi4lite_rresp, // .ch0_axil_rresp
|
||||
output wire [31:0] s0_noc_axi4lite_rdata, // .ch0_axil_rdata
|
||||
output wire s0_noc_axi4lite_rvalid, // .ch0_axil_rvalid
|
||||
input wire s0_noc_axi4lite_rready, // .ch0_axil_rready
|
||||
output wire [1:0] s0_noc_axi4lite_bresp, // .ch0_axil_bresp
|
||||
output wire s0_noc_axi4lite_bvalid, // .ch0_axil_bvalid
|
||||
input wire s0_noc_axi4lite_bready, // .ch0_axil_bready
|
||||
input wire [2:0] s0_noc_axi4lite_awprot, // .ch0_axil_awprot
|
||||
input wire [2:0] s0_noc_axi4lite_arprot, // .ch0_axil_arprot
|
||||
input wire [3:0] s0_noc_axi4lite_wstrb, // .ch0_axil_wstrb
|
||||
input wire [39:0] s0_axi4_awaddr, // .axi4_ch0_awaddr
|
||||
input wire [1:0] s0_axi4_awburst, // .axi4_ch0_awburst
|
||||
input wire [6:0] s0_axi4_awid, // .axi4_ch0_awid
|
||||
input wire [7:0] s0_axi4_awlen, // .axi4_ch0_awlen
|
||||
input wire s0_axi4_awlock, // .axi4_ch0_awlock
|
||||
input wire [3:0] s0_axi4_awqos, // .axi4_ch0_awqos
|
||||
input wire [2:0] s0_axi4_awsize, // .axi4_ch0_awsize
|
||||
input wire s0_axi4_awvalid, // .axi4_ch0_awvalid
|
||||
input wire [13:0] s0_axi4_awuser, // .axi4_ch0_awuser
|
||||
input wire [2:0] s0_axi4_awprot, // .axi4_ch0_awprot
|
||||
output wire s0_axi4_awready, // .axi4_ch0_awready
|
||||
input wire [39:0] s0_axi4_araddr, // .axi4_ch0_araddr
|
||||
input wire [1:0] s0_axi4_arburst, // .axi4_ch0_arburst
|
||||
input wire [6:0] s0_axi4_arid, // .axi4_ch0_arid
|
||||
input wire [7:0] s0_axi4_arlen, // .axi4_ch0_arlen
|
||||
input wire s0_axi4_arlock, // .axi4_ch0_arlock
|
||||
input wire [3:0] s0_axi4_arqos, // .axi4_ch0_arqos
|
||||
input wire [2:0] s0_axi4_arsize, // .axi4_ch0_arsize
|
||||
input wire s0_axi4_arvalid, // .axi4_ch0_arvalid
|
||||
input wire [13:0] s0_axi4_aruser, // .axi4_ch0_aruser
|
||||
input wire [2:0] s0_axi4_arprot, // .axi4_ch0_arprot
|
||||
output wire s0_axi4_arready, // .axi4_ch0_arready
|
||||
input wire [255:0] s0_axi4_wdata, // .axi4_ch0_wdata
|
||||
input wire [31:0] s0_axi4_wstrb, // .axi4_ch0_wstrb
|
||||
input wire s0_axi4_wlast, // .axi4_ch0_wlast
|
||||
input wire s0_axi4_wvalid, // .axi4_ch0_wvalid
|
||||
output wire s0_axi4_wready, // .axi4_ch0_wready
|
||||
input wire s0_axi4_bready, // .axi4_ch0_bready
|
||||
output wire [6:0] s0_axi4_bid, // .axi4_ch0_bid
|
||||
output wire [1:0] s0_axi4_bresp, // .axi4_ch0_bresp
|
||||
output wire s0_axi4_bvalid, // .axi4_ch0_bvalid
|
||||
input wire s0_axi4_rready, // .axi4_ch0_rready
|
||||
output wire [255:0] s0_axi4_rdata, // .axi4_ch0_rdata
|
||||
output wire [6:0] s0_axi4_rid, // .axi4_ch0_rid
|
||||
output wire s0_axi4_rlast, // .axi4_ch0_rlast
|
||||
output wire [1:0] s0_axi4_rresp, // .axi4_ch0_rresp
|
||||
output wire s0_axi4_rvalid, // .axi4_ch0_rvalid
|
||||
output wire noc_aclk_0, // .axi4_ch0_clk
|
||||
output wire noc_rst_n_0, // .axi4_ch0_reset_n
|
||||
input wire [31:0] s0_axi4_wuser, // .axi4_ch0_wuser
|
||||
output wire [31:0] s0_axi4_ruser, // .axi4_ch0_ruser
|
||||
output wire [0:0] mem_0_cs, // mem_0.mem_cs
|
||||
output wire [5:0] mem_0_ca, // .mem_ca
|
||||
output wire [0:0] mem_0_cke, // .mem_cke
|
||||
inout wire [31:0] mem_0_dq, // .mem_dq
|
||||
inout wire [3:0] mem_0_dqs_t, // .mem_dqs_t
|
||||
inout wire [3:0] mem_0_dqs_c, // .mem_dqs_c
|
||||
inout wire [3:0] mem_0_dmi, // .mem_dmi
|
||||
output wire [0:0] mem_0_ck_t, // mem_ck_0.mem_ck_t
|
||||
output wire [0:0] mem_0_ck_c, // .mem_ck_c
|
||||
output wire mem_0_reset_n, // mem_reset_n.mem_reset_n
|
||||
input wire oct_rzqin_0, // oct_0.oct_rzqin
|
||||
input wire ref_clk // ref_clk.clk
|
||||
);
|
||||
endmodule
|
||||
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
component emif_io96b_hps_emif_io96b_hps_420_dyxenzq is
|
||||
port (
|
||||
s0_noc_axi4lite_clock : out std_logic; -- ch0_axil_clk
|
||||
s0_noc_axi4lite_reset_n : out std_logic; -- ch0_axil_reset_n
|
||||
s0_noc_axi4lite_awaddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- ch0_axil_awaddr
|
||||
s0_noc_axi4lite_awvalid : in std_logic := 'X'; -- ch0_axil_awvalid
|
||||
s0_noc_axi4lite_awready : out std_logic; -- ch0_axil_awready
|
||||
s0_noc_axi4lite_araddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- ch0_axil_araddr
|
||||
s0_noc_axi4lite_arvalid : in std_logic := 'X'; -- ch0_axil_arvalid
|
||||
s0_noc_axi4lite_arready : out std_logic; -- ch0_axil_arready
|
||||
s0_noc_axi4lite_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- ch0_axil_wdata
|
||||
s0_noc_axi4lite_wvalid : in std_logic := 'X'; -- ch0_axil_wvalid
|
||||
s0_noc_axi4lite_wready : out std_logic; -- ch0_axil_wready
|
||||
s0_noc_axi4lite_rresp : out std_logic_vector(1 downto 0); -- ch0_axil_rresp
|
||||
s0_noc_axi4lite_rdata : out std_logic_vector(31 downto 0); -- ch0_axil_rdata
|
||||
s0_noc_axi4lite_rvalid : out std_logic; -- ch0_axil_rvalid
|
||||
s0_noc_axi4lite_rready : in std_logic := 'X'; -- ch0_axil_rready
|
||||
s0_noc_axi4lite_bresp : out std_logic_vector(1 downto 0); -- ch0_axil_bresp
|
||||
s0_noc_axi4lite_bvalid : out std_logic; -- ch0_axil_bvalid
|
||||
s0_noc_axi4lite_bready : in std_logic := 'X'; -- ch0_axil_bready
|
||||
s0_noc_axi4lite_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- ch0_axil_awprot
|
||||
s0_noc_axi4lite_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- ch0_axil_arprot
|
||||
s0_noc_axi4lite_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- ch0_axil_wstrb
|
||||
s0_axi4_awaddr : in std_logic_vector(39 downto 0) := (others => 'X'); -- axi4_ch0_awaddr
|
||||
s0_axi4_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- axi4_ch0_awburst
|
||||
s0_axi4_awid : in std_logic_vector(6 downto 0) := (others => 'X'); -- axi4_ch0_awid
|
||||
s0_axi4_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- axi4_ch0_awlen
|
||||
s0_axi4_awlock : in std_logic := 'X'; -- axi4_ch0_awlock
|
||||
s0_axi4_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- axi4_ch0_awqos
|
||||
s0_axi4_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_awsize
|
||||
s0_axi4_awvalid : in std_logic := 'X'; -- axi4_ch0_awvalid
|
||||
s0_axi4_awuser : in std_logic_vector(13 downto 0) := (others => 'X'); -- axi4_ch0_awuser
|
||||
s0_axi4_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_awprot
|
||||
s0_axi4_awready : out std_logic; -- axi4_ch0_awready
|
||||
s0_axi4_araddr : in std_logic_vector(39 downto 0) := (others => 'X'); -- axi4_ch0_araddr
|
||||
s0_axi4_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- axi4_ch0_arburst
|
||||
s0_axi4_arid : in std_logic_vector(6 downto 0) := (others => 'X'); -- axi4_ch0_arid
|
||||
s0_axi4_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- axi4_ch0_arlen
|
||||
s0_axi4_arlock : in std_logic := 'X'; -- axi4_ch0_arlock
|
||||
s0_axi4_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- axi4_ch0_arqos
|
||||
s0_axi4_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_arsize
|
||||
s0_axi4_arvalid : in std_logic := 'X'; -- axi4_ch0_arvalid
|
||||
s0_axi4_aruser : in std_logic_vector(13 downto 0) := (others => 'X'); -- axi4_ch0_aruser
|
||||
s0_axi4_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_arprot
|
||||
s0_axi4_arready : out std_logic; -- axi4_ch0_arready
|
||||
s0_axi4_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- axi4_ch0_wdata
|
||||
s0_axi4_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- axi4_ch0_wstrb
|
||||
s0_axi4_wlast : in std_logic := 'X'; -- axi4_ch0_wlast
|
||||
s0_axi4_wvalid : in std_logic := 'X'; -- axi4_ch0_wvalid
|
||||
s0_axi4_wready : out std_logic; -- axi4_ch0_wready
|
||||
s0_axi4_bready : in std_logic := 'X'; -- axi4_ch0_bready
|
||||
s0_axi4_bid : out std_logic_vector(6 downto 0); -- axi4_ch0_bid
|
||||
s0_axi4_bresp : out std_logic_vector(1 downto 0); -- axi4_ch0_bresp
|
||||
s0_axi4_bvalid : out std_logic; -- axi4_ch0_bvalid
|
||||
s0_axi4_rready : in std_logic := 'X'; -- axi4_ch0_rready
|
||||
s0_axi4_rdata : out std_logic_vector(255 downto 0); -- axi4_ch0_rdata
|
||||
s0_axi4_rid : out std_logic_vector(6 downto 0); -- axi4_ch0_rid
|
||||
s0_axi4_rlast : out std_logic; -- axi4_ch0_rlast
|
||||
s0_axi4_rresp : out std_logic_vector(1 downto 0); -- axi4_ch0_rresp
|
||||
s0_axi4_rvalid : out std_logic; -- axi4_ch0_rvalid
|
||||
noc_aclk_0 : out std_logic; -- axi4_ch0_clk
|
||||
noc_rst_n_0 : out std_logic; -- axi4_ch0_reset_n
|
||||
s0_axi4_wuser : in std_logic_vector(31 downto 0) := (others => 'X'); -- axi4_ch0_wuser
|
||||
s0_axi4_ruser : out std_logic_vector(31 downto 0); -- axi4_ch0_ruser
|
||||
mem_0_cs : out std_logic_vector(0 downto 0); -- mem_cs
|
||||
mem_0_ca : out std_logic_vector(5 downto 0); -- mem_ca
|
||||
mem_0_cke : out std_logic_vector(0 downto 0); -- mem_cke
|
||||
mem_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
|
||||
mem_0_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
|
||||
mem_0_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
|
||||
mem_0_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
|
||||
mem_0_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
|
||||
mem_0_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
|
||||
mem_0_reset_n : out std_logic; -- mem_reset_n
|
||||
oct_rzqin_0 : in std_logic := 'X'; -- oct_rzqin
|
||||
ref_clk : in std_logic := 'X' -- clk
|
||||
);
|
||||
end component emif_io96b_hps_emif_io96b_hps_420_dyxenzq;
|
||||
|
||||
+19
@@ -0,0 +1,19 @@
|
||||
# system info emif_io96b_hps_emif_io96b_hps_420_dyxenzq on 2026.04.08.10:53:26
|
||||
system_info:
|
||||
name,value
|
||||
DEVICE,A5EB013BB23BE4SCS
|
||||
DEVICE_FAMILY,Agilex 5
|
||||
GENERATION_ID,0
|
||||
#
|
||||
#
|
||||
# Files generated for emif_io96b_hps_emif_io96b_hps_420_dyxenzq on 2026.04.08.10:53:26
|
||||
files:
|
||||
filepath,kind,attributes,module,is_top
|
||||
sim/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,emif_io96b_hps_emif_io96b_hps_420_dyxenzq,true
|
||||
#
|
||||
# Map from instance-path to kind of module
|
||||
instances:
|
||||
instancePath,module
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq.emif_0_lpddr4,emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq.refclk_bridge,emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq.refclk_gpio,emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio
|
||||
|
+267
@@ -0,0 +1,267 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for emif_io96b_hps_emif_io96b_hps_420_dyxenzq</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">emif_io96b_hps_emif_io96b_hps_420_dyxenzq</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2026.04.08.10:53:26</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_emif_0_lpddr4"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>emif_0_lpddr4</h2>emif_io96b_lpddr4 v4.2.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_refclk_bridge">refclk_bridge</a>
|
||||
</td>
|
||||
<td class="from">refclk_out  </td>
|
||||
<td class="main" rowspan="2">emif_0_lpddr4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  ref_clk</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_refclk_bridge"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>refclk_bridge</h2>qsys_interface_bridge v1.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_refclk_gpio">refclk_gpio</a>
|
||||
</td>
|
||||
<td class="from">dout  </td>
|
||||
<td class="main" rowspan="7">refclk_bridge</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  refclk_out_gpio</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">refclk_out  </td>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_emif_0_lpddr4">emif_0_lpddr4</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  ref_clk</td>
|
||||
</tr>
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">refclk_in_gpio  </td>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_refclk_gpio">refclk_gpio</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  pad_in</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<a name="module_refclk_gpio"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>refclk_gpio</h2>altera_gpio v23.0.0
|
||||
<br/>
|
||||
<div class="greydiv">
|
||||
<table class="connectionboxes">
|
||||
<tr>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_refclk_bridge">refclk_bridge</a>
|
||||
</td>
|
||||
<td class="from">refclk_in_gpio  </td>
|
||||
<td class="main" rowspan="4">refclk_gpio</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="to">  pad_in</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="from">dout  </td>
|
||||
<td class="neighbor" rowspan="2">
|
||||
<a href="#module_refclk_bridge">refclk_bridge</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td></td>
|
||||
<td class="to">  refclk_out_gpio</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.02 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
+1800
File diff suppressed because it is too large
Load Diff
+3386
File diff suppressed because it is too large
Load Diff
+12
@@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<simPackage>
|
||||
<file
|
||||
path="sim/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v"
|
||||
type="VERILOG"
|
||||
library="emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
hasInlineConfiguration="true" />
|
||||
<topLevel
|
||||
name="emif_io96b_hps_emif_io96b_hps_420_dyxenzq.emif_io96b_hps_emif_io96b_hps_420_dyxenzq" />
|
||||
<deviceFamily name="agilex5" />
|
||||
<device name="A5EB013BB23BE4SCS" />
|
||||
</simPackage>
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq (
|
||||
output wire s0_noc_axi4lite_clock, // io96b0_to_hps.ch0_axil_clk
|
||||
output wire s0_noc_axi4lite_reset_n, // .ch0_axil_reset_n
|
||||
input wire [26:0] s0_noc_axi4lite_awaddr, // .ch0_axil_awaddr
|
||||
input wire s0_noc_axi4lite_awvalid, // .ch0_axil_awvalid
|
||||
output wire s0_noc_axi4lite_awready, // .ch0_axil_awready
|
||||
input wire [26:0] s0_noc_axi4lite_araddr, // .ch0_axil_araddr
|
||||
input wire s0_noc_axi4lite_arvalid, // .ch0_axil_arvalid
|
||||
output wire s0_noc_axi4lite_arready, // .ch0_axil_arready
|
||||
input wire [31:0] s0_noc_axi4lite_wdata, // .ch0_axil_wdata
|
||||
input wire s0_noc_axi4lite_wvalid, // .ch0_axil_wvalid
|
||||
output wire s0_noc_axi4lite_wready, // .ch0_axil_wready
|
||||
output wire [1:0] s0_noc_axi4lite_rresp, // .ch0_axil_rresp
|
||||
output wire [31:0] s0_noc_axi4lite_rdata, // .ch0_axil_rdata
|
||||
output wire s0_noc_axi4lite_rvalid, // .ch0_axil_rvalid
|
||||
input wire s0_noc_axi4lite_rready, // .ch0_axil_rready
|
||||
output wire [1:0] s0_noc_axi4lite_bresp, // .ch0_axil_bresp
|
||||
output wire s0_noc_axi4lite_bvalid, // .ch0_axil_bvalid
|
||||
input wire s0_noc_axi4lite_bready, // .ch0_axil_bready
|
||||
input wire [2:0] s0_noc_axi4lite_awprot, // .ch0_axil_awprot
|
||||
input wire [2:0] s0_noc_axi4lite_arprot, // .ch0_axil_arprot
|
||||
input wire [3:0] s0_noc_axi4lite_wstrb, // .ch0_axil_wstrb
|
||||
input wire [39:0] s0_axi4_awaddr, // .axi4_ch0_awaddr
|
||||
input wire [1:0] s0_axi4_awburst, // .axi4_ch0_awburst
|
||||
input wire [6:0] s0_axi4_awid, // .axi4_ch0_awid
|
||||
input wire [7:0] s0_axi4_awlen, // .axi4_ch0_awlen
|
||||
input wire s0_axi4_awlock, // .axi4_ch0_awlock
|
||||
input wire [3:0] s0_axi4_awqos, // .axi4_ch0_awqos
|
||||
input wire [2:0] s0_axi4_awsize, // .axi4_ch0_awsize
|
||||
input wire s0_axi4_awvalid, // .axi4_ch0_awvalid
|
||||
input wire [13:0] s0_axi4_awuser, // .axi4_ch0_awuser
|
||||
input wire [2:0] s0_axi4_awprot, // .axi4_ch0_awprot
|
||||
output wire s0_axi4_awready, // .axi4_ch0_awready
|
||||
input wire [39:0] s0_axi4_araddr, // .axi4_ch0_araddr
|
||||
input wire [1:0] s0_axi4_arburst, // .axi4_ch0_arburst
|
||||
input wire [6:0] s0_axi4_arid, // .axi4_ch0_arid
|
||||
input wire [7:0] s0_axi4_arlen, // .axi4_ch0_arlen
|
||||
input wire s0_axi4_arlock, // .axi4_ch0_arlock
|
||||
input wire [3:0] s0_axi4_arqos, // .axi4_ch0_arqos
|
||||
input wire [2:0] s0_axi4_arsize, // .axi4_ch0_arsize
|
||||
input wire s0_axi4_arvalid, // .axi4_ch0_arvalid
|
||||
input wire [13:0] s0_axi4_aruser, // .axi4_ch0_aruser
|
||||
input wire [2:0] s0_axi4_arprot, // .axi4_ch0_arprot
|
||||
output wire s0_axi4_arready, // .axi4_ch0_arready
|
||||
input wire [255:0] s0_axi4_wdata, // .axi4_ch0_wdata
|
||||
input wire [31:0] s0_axi4_wstrb, // .axi4_ch0_wstrb
|
||||
input wire s0_axi4_wlast, // .axi4_ch0_wlast
|
||||
input wire s0_axi4_wvalid, // .axi4_ch0_wvalid
|
||||
output wire s0_axi4_wready, // .axi4_ch0_wready
|
||||
input wire s0_axi4_bready, // .axi4_ch0_bready
|
||||
output wire [6:0] s0_axi4_bid, // .axi4_ch0_bid
|
||||
output wire [1:0] s0_axi4_bresp, // .axi4_ch0_bresp
|
||||
output wire s0_axi4_bvalid, // .axi4_ch0_bvalid
|
||||
input wire s0_axi4_rready, // .axi4_ch0_rready
|
||||
output wire [255:0] s0_axi4_rdata, // .axi4_ch0_rdata
|
||||
output wire [6:0] s0_axi4_rid, // .axi4_ch0_rid
|
||||
output wire s0_axi4_rlast, // .axi4_ch0_rlast
|
||||
output wire [1:0] s0_axi4_rresp, // .axi4_ch0_rresp
|
||||
output wire s0_axi4_rvalid, // .axi4_ch0_rvalid
|
||||
output wire noc_aclk_0, // .axi4_ch0_clk
|
||||
output wire noc_rst_n_0, // .axi4_ch0_reset_n
|
||||
input wire [31:0] s0_axi4_wuser, // .axi4_ch0_wuser
|
||||
output wire [31:0] s0_axi4_ruser, // .axi4_ch0_ruser
|
||||
output wire [0:0] mem_0_cs, // mem_0.mem_cs
|
||||
output wire [5:0] mem_0_ca, // .mem_ca
|
||||
output wire [0:0] mem_0_cke, // .mem_cke
|
||||
inout wire [31:0] mem_0_dq, // .mem_dq
|
||||
inout wire [3:0] mem_0_dqs_t, // .mem_dqs_t
|
||||
inout wire [3:0] mem_0_dqs_c, // .mem_dqs_c
|
||||
inout wire [3:0] mem_0_dmi, // .mem_dmi
|
||||
output wire [0:0] mem_0_ck_t, // mem_ck_0.mem_ck_t
|
||||
output wire [0:0] mem_0_ck_c, // .mem_ck_c
|
||||
output wire mem_0_reset_n, // mem_reset_n.mem_reset_n
|
||||
input wire oct_rzqin_0, // oct_0.oct_rzqin
|
||||
input wire ref_clk // ref_clk.clk
|
||||
);
|
||||
endmodule
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
Info: Generated by version: 26.1 build 110
|
||||
Info: Starting: Create simulation model
|
||||
Info: qsys-generate /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq --family="Agilex 5" --part=A5EB013BB23BE4SCS
|
||||
Progress: Loading 0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Parameterizing module emif_0_ddr4comp
|
||||
Progress: Parameterizing module emif_0_ddr5comp
|
||||
Progress: Parameterizing module emif_0_ddr5dimm
|
||||
Progress: Parameterizing module emif_0_lpddr4
|
||||
Progress: Parameterizing module emif_0_lpddr5
|
||||
Progress: Parameterizing module emif_1_ddr4comp
|
||||
Progress: Parameterizing module emif_1_ddr5comp
|
||||
Progress: Parameterizing module emif_1_ddr5dimm
|
||||
Progress: Parameterizing module emif_1_lpddr4
|
||||
Progress: Parameterizing module emif_1_lpddr5
|
||||
Progress: Parameterizing module refclk_bridge
|
||||
Progress: Parameterizing module refclk_gpio
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Processing generation queue"
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"
|
||||
Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" with 4 modules, 1 files
|
||||
Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for specified device family. Use VCS-MX or another supported simulator.
|
||||
Info: Generating the following file(s) for XCELIUM simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: common/xcelium_files.tcl
|
||||
Info: Generating the following file(s) for RIVIERA simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: common/riviera_files.tcl
|
||||
Info: Generating the following file(s) for MODELSIM simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: common/modelsim_files.tcl
|
||||
Info: Generating the following file(s) for VCSMX simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: common/vcsmx_files.tcl
|
||||
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/.
|
||||
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
|
||||
Info: Finished: Create simulation model
|
||||
Info: Starting: Create simulation script
|
||||
Info: sim-script-gen --system-file=/tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys --output-directory=/tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ --use-relative-paths=true
|
||||
Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for specified device family. Use VCS-MX or another supported simulator.
|
||||
Info: Generating the following file(s) for XCELIUM simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: xcelium/cds.lib
|
||||
Info: xcelium/hdl.var
|
||||
Info: xcelium/xcelium_setup.sh
|
||||
Info: 1 .cds.lib files in xcelium/cds_libs/ directory
|
||||
Info: Generating the following file(s) for RIVIERA simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: aldec/rivierapro_setup.tcl
|
||||
Info: aldec/run_rivierapro_setup.tcl
|
||||
Info: Generating the following file(s) for MODELSIM simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: mentor/msim_setup.tcl
|
||||
Info: mentor/run_msim_setup.tcl
|
||||
Info: Generating the following file(s) for VCSMX simulator in /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/ directory:
|
||||
Info: synopsys/vcsmx/_device_synopsys_sim.setup
|
||||
Info: synopsys/vcsmx/synopsys_sim.setup
|
||||
Info: synopsys/vcsmx/vcsmx_setup.sh
|
||||
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /tmp/alt0551_16132048750212371584.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/sim/.
|
||||
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
|
||||
Info: Finished: Create simulation script
|
||||
+77
@@ -0,0 +1,77 @@
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq u0 (
|
||||
.s0_noc_axi4lite_clock (_connected_to_s0_noc_axi4lite_clock_), // output, width = 1, io96b0_to_hps.ch0_axil_clk
|
||||
.s0_noc_axi4lite_reset_n (_connected_to_s0_noc_axi4lite_reset_n_), // output, width = 1, .ch0_axil_reset_n
|
||||
.s0_noc_axi4lite_awaddr (_connected_to_s0_noc_axi4lite_awaddr_), // input, width = 27, .ch0_axil_awaddr
|
||||
.s0_noc_axi4lite_awvalid (_connected_to_s0_noc_axi4lite_awvalid_), // input, width = 1, .ch0_axil_awvalid
|
||||
.s0_noc_axi4lite_awready (_connected_to_s0_noc_axi4lite_awready_), // output, width = 1, .ch0_axil_awready
|
||||
.s0_noc_axi4lite_araddr (_connected_to_s0_noc_axi4lite_araddr_), // input, width = 27, .ch0_axil_araddr
|
||||
.s0_noc_axi4lite_arvalid (_connected_to_s0_noc_axi4lite_arvalid_), // input, width = 1, .ch0_axil_arvalid
|
||||
.s0_noc_axi4lite_arready (_connected_to_s0_noc_axi4lite_arready_), // output, width = 1, .ch0_axil_arready
|
||||
.s0_noc_axi4lite_wdata (_connected_to_s0_noc_axi4lite_wdata_), // input, width = 32, .ch0_axil_wdata
|
||||
.s0_noc_axi4lite_wvalid (_connected_to_s0_noc_axi4lite_wvalid_), // input, width = 1, .ch0_axil_wvalid
|
||||
.s0_noc_axi4lite_wready (_connected_to_s0_noc_axi4lite_wready_), // output, width = 1, .ch0_axil_wready
|
||||
.s0_noc_axi4lite_rresp (_connected_to_s0_noc_axi4lite_rresp_), // output, width = 2, .ch0_axil_rresp
|
||||
.s0_noc_axi4lite_rdata (_connected_to_s0_noc_axi4lite_rdata_), // output, width = 32, .ch0_axil_rdata
|
||||
.s0_noc_axi4lite_rvalid (_connected_to_s0_noc_axi4lite_rvalid_), // output, width = 1, .ch0_axil_rvalid
|
||||
.s0_noc_axi4lite_rready (_connected_to_s0_noc_axi4lite_rready_), // input, width = 1, .ch0_axil_rready
|
||||
.s0_noc_axi4lite_bresp (_connected_to_s0_noc_axi4lite_bresp_), // output, width = 2, .ch0_axil_bresp
|
||||
.s0_noc_axi4lite_bvalid (_connected_to_s0_noc_axi4lite_bvalid_), // output, width = 1, .ch0_axil_bvalid
|
||||
.s0_noc_axi4lite_bready (_connected_to_s0_noc_axi4lite_bready_), // input, width = 1, .ch0_axil_bready
|
||||
.s0_noc_axi4lite_awprot (_connected_to_s0_noc_axi4lite_awprot_), // input, width = 3, .ch0_axil_awprot
|
||||
.s0_noc_axi4lite_arprot (_connected_to_s0_noc_axi4lite_arprot_), // input, width = 3, .ch0_axil_arprot
|
||||
.s0_noc_axi4lite_wstrb (_connected_to_s0_noc_axi4lite_wstrb_), // input, width = 4, .ch0_axil_wstrb
|
||||
.s0_axi4_awaddr (_connected_to_s0_axi4_awaddr_), // input, width = 40, .axi4_ch0_awaddr
|
||||
.s0_axi4_awburst (_connected_to_s0_axi4_awburst_), // input, width = 2, .axi4_ch0_awburst
|
||||
.s0_axi4_awid (_connected_to_s0_axi4_awid_), // input, width = 7, .axi4_ch0_awid
|
||||
.s0_axi4_awlen (_connected_to_s0_axi4_awlen_), // input, width = 8, .axi4_ch0_awlen
|
||||
.s0_axi4_awlock (_connected_to_s0_axi4_awlock_), // input, width = 1, .axi4_ch0_awlock
|
||||
.s0_axi4_awqos (_connected_to_s0_axi4_awqos_), // input, width = 4, .axi4_ch0_awqos
|
||||
.s0_axi4_awsize (_connected_to_s0_axi4_awsize_), // input, width = 3, .axi4_ch0_awsize
|
||||
.s0_axi4_awvalid (_connected_to_s0_axi4_awvalid_), // input, width = 1, .axi4_ch0_awvalid
|
||||
.s0_axi4_awuser (_connected_to_s0_axi4_awuser_), // input, width = 14, .axi4_ch0_awuser
|
||||
.s0_axi4_awprot (_connected_to_s0_axi4_awprot_), // input, width = 3, .axi4_ch0_awprot
|
||||
.s0_axi4_awready (_connected_to_s0_axi4_awready_), // output, width = 1, .axi4_ch0_awready
|
||||
.s0_axi4_araddr (_connected_to_s0_axi4_araddr_), // input, width = 40, .axi4_ch0_araddr
|
||||
.s0_axi4_arburst (_connected_to_s0_axi4_arburst_), // input, width = 2, .axi4_ch0_arburst
|
||||
.s0_axi4_arid (_connected_to_s0_axi4_arid_), // input, width = 7, .axi4_ch0_arid
|
||||
.s0_axi4_arlen (_connected_to_s0_axi4_arlen_), // input, width = 8, .axi4_ch0_arlen
|
||||
.s0_axi4_arlock (_connected_to_s0_axi4_arlock_), // input, width = 1, .axi4_ch0_arlock
|
||||
.s0_axi4_arqos (_connected_to_s0_axi4_arqos_), // input, width = 4, .axi4_ch0_arqos
|
||||
.s0_axi4_arsize (_connected_to_s0_axi4_arsize_), // input, width = 3, .axi4_ch0_arsize
|
||||
.s0_axi4_arvalid (_connected_to_s0_axi4_arvalid_), // input, width = 1, .axi4_ch0_arvalid
|
||||
.s0_axi4_aruser (_connected_to_s0_axi4_aruser_), // input, width = 14, .axi4_ch0_aruser
|
||||
.s0_axi4_arprot (_connected_to_s0_axi4_arprot_), // input, width = 3, .axi4_ch0_arprot
|
||||
.s0_axi4_arready (_connected_to_s0_axi4_arready_), // output, width = 1, .axi4_ch0_arready
|
||||
.s0_axi4_wdata (_connected_to_s0_axi4_wdata_), // input, width = 256, .axi4_ch0_wdata
|
||||
.s0_axi4_wstrb (_connected_to_s0_axi4_wstrb_), // input, width = 32, .axi4_ch0_wstrb
|
||||
.s0_axi4_wlast (_connected_to_s0_axi4_wlast_), // input, width = 1, .axi4_ch0_wlast
|
||||
.s0_axi4_wvalid (_connected_to_s0_axi4_wvalid_), // input, width = 1, .axi4_ch0_wvalid
|
||||
.s0_axi4_wready (_connected_to_s0_axi4_wready_), // output, width = 1, .axi4_ch0_wready
|
||||
.s0_axi4_bready (_connected_to_s0_axi4_bready_), // input, width = 1, .axi4_ch0_bready
|
||||
.s0_axi4_bid (_connected_to_s0_axi4_bid_), // output, width = 7, .axi4_ch0_bid
|
||||
.s0_axi4_bresp (_connected_to_s0_axi4_bresp_), // output, width = 2, .axi4_ch0_bresp
|
||||
.s0_axi4_bvalid (_connected_to_s0_axi4_bvalid_), // output, width = 1, .axi4_ch0_bvalid
|
||||
.s0_axi4_rready (_connected_to_s0_axi4_rready_), // input, width = 1, .axi4_ch0_rready
|
||||
.s0_axi4_rdata (_connected_to_s0_axi4_rdata_), // output, width = 256, .axi4_ch0_rdata
|
||||
.s0_axi4_rid (_connected_to_s0_axi4_rid_), // output, width = 7, .axi4_ch0_rid
|
||||
.s0_axi4_rlast (_connected_to_s0_axi4_rlast_), // output, width = 1, .axi4_ch0_rlast
|
||||
.s0_axi4_rresp (_connected_to_s0_axi4_rresp_), // output, width = 2, .axi4_ch0_rresp
|
||||
.s0_axi4_rvalid (_connected_to_s0_axi4_rvalid_), // output, width = 1, .axi4_ch0_rvalid
|
||||
.noc_aclk_0 (_connected_to_noc_aclk_0_), // output, width = 1, .axi4_ch0_clk
|
||||
.noc_rst_n_0 (_connected_to_noc_rst_n_0_), // output, width = 1, .axi4_ch0_reset_n
|
||||
.s0_axi4_wuser (_connected_to_s0_axi4_wuser_), // input, width = 32, .axi4_ch0_wuser
|
||||
.s0_axi4_ruser (_connected_to_s0_axi4_ruser_), // output, width = 32, .axi4_ch0_ruser
|
||||
.mem_0_cs (_connected_to_mem_0_cs_), // output, width = 1, mem_0.mem_cs
|
||||
.mem_0_ca (_connected_to_mem_0_ca_), // output, width = 6, .mem_ca
|
||||
.mem_0_cke (_connected_to_mem_0_cke_), // output, width = 1, .mem_cke
|
||||
.mem_0_dq (_connected_to_mem_0_dq_), // inout, width = 32, .mem_dq
|
||||
.mem_0_dqs_t (_connected_to_mem_0_dqs_t_), // inout, width = 4, .mem_dqs_t
|
||||
.mem_0_dqs_c (_connected_to_mem_0_dqs_c_), // inout, width = 4, .mem_dqs_c
|
||||
.mem_0_dmi (_connected_to_mem_0_dmi_), // inout, width = 4, .mem_dmi
|
||||
.mem_0_ck_t (_connected_to_mem_0_ck_t_), // output, width = 1, mem_ck_0.mem_ck_t
|
||||
.mem_0_ck_c (_connected_to_mem_0_ck_c_), // output, width = 1, .mem_ck_c
|
||||
.mem_0_reset_n (_connected_to_mem_0_reset_n_), // output, width = 1, mem_reset_n.mem_reset_n
|
||||
.oct_rzqin_0 (_connected_to_oct_rzqin_0_), // input, width = 1, oct_0.oct_rzqin
|
||||
.ref_clk (_connected_to_ref_clk_) // input, width = 1, ref_clk.clk
|
||||
);
|
||||
|
||||
+157
@@ -0,0 +1,157 @@
|
||||
component emif_io96b_hps_emif_io96b_hps_420_dyxenzq is
|
||||
port (
|
||||
s0_noc_axi4lite_clock : out std_logic; -- ch0_axil_clk
|
||||
s0_noc_axi4lite_reset_n : out std_logic; -- ch0_axil_reset_n
|
||||
s0_noc_axi4lite_awaddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- ch0_axil_awaddr
|
||||
s0_noc_axi4lite_awvalid : in std_logic := 'X'; -- ch0_axil_awvalid
|
||||
s0_noc_axi4lite_awready : out std_logic; -- ch0_axil_awready
|
||||
s0_noc_axi4lite_araddr : in std_logic_vector(26 downto 0) := (others => 'X'); -- ch0_axil_araddr
|
||||
s0_noc_axi4lite_arvalid : in std_logic := 'X'; -- ch0_axil_arvalid
|
||||
s0_noc_axi4lite_arready : out std_logic; -- ch0_axil_arready
|
||||
s0_noc_axi4lite_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- ch0_axil_wdata
|
||||
s0_noc_axi4lite_wvalid : in std_logic := 'X'; -- ch0_axil_wvalid
|
||||
s0_noc_axi4lite_wready : out std_logic; -- ch0_axil_wready
|
||||
s0_noc_axi4lite_rresp : out std_logic_vector(1 downto 0); -- ch0_axil_rresp
|
||||
s0_noc_axi4lite_rdata : out std_logic_vector(31 downto 0); -- ch0_axil_rdata
|
||||
s0_noc_axi4lite_rvalid : out std_logic; -- ch0_axil_rvalid
|
||||
s0_noc_axi4lite_rready : in std_logic := 'X'; -- ch0_axil_rready
|
||||
s0_noc_axi4lite_bresp : out std_logic_vector(1 downto 0); -- ch0_axil_bresp
|
||||
s0_noc_axi4lite_bvalid : out std_logic; -- ch0_axil_bvalid
|
||||
s0_noc_axi4lite_bready : in std_logic := 'X'; -- ch0_axil_bready
|
||||
s0_noc_axi4lite_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- ch0_axil_awprot
|
||||
s0_noc_axi4lite_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- ch0_axil_arprot
|
||||
s0_noc_axi4lite_wstrb : in std_logic_vector(3 downto 0) := (others => 'X'); -- ch0_axil_wstrb
|
||||
s0_axi4_awaddr : in std_logic_vector(39 downto 0) := (others => 'X'); -- axi4_ch0_awaddr
|
||||
s0_axi4_awburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- axi4_ch0_awburst
|
||||
s0_axi4_awid : in std_logic_vector(6 downto 0) := (others => 'X'); -- axi4_ch0_awid
|
||||
s0_axi4_awlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- axi4_ch0_awlen
|
||||
s0_axi4_awlock : in std_logic := 'X'; -- axi4_ch0_awlock
|
||||
s0_axi4_awqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- axi4_ch0_awqos
|
||||
s0_axi4_awsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_awsize
|
||||
s0_axi4_awvalid : in std_logic := 'X'; -- axi4_ch0_awvalid
|
||||
s0_axi4_awuser : in std_logic_vector(13 downto 0) := (others => 'X'); -- axi4_ch0_awuser
|
||||
s0_axi4_awprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_awprot
|
||||
s0_axi4_awready : out std_logic; -- axi4_ch0_awready
|
||||
s0_axi4_araddr : in std_logic_vector(39 downto 0) := (others => 'X'); -- axi4_ch0_araddr
|
||||
s0_axi4_arburst : in std_logic_vector(1 downto 0) := (others => 'X'); -- axi4_ch0_arburst
|
||||
s0_axi4_arid : in std_logic_vector(6 downto 0) := (others => 'X'); -- axi4_ch0_arid
|
||||
s0_axi4_arlen : in std_logic_vector(7 downto 0) := (others => 'X'); -- axi4_ch0_arlen
|
||||
s0_axi4_arlock : in std_logic := 'X'; -- axi4_ch0_arlock
|
||||
s0_axi4_arqos : in std_logic_vector(3 downto 0) := (others => 'X'); -- axi4_ch0_arqos
|
||||
s0_axi4_arsize : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_arsize
|
||||
s0_axi4_arvalid : in std_logic := 'X'; -- axi4_ch0_arvalid
|
||||
s0_axi4_aruser : in std_logic_vector(13 downto 0) := (others => 'X'); -- axi4_ch0_aruser
|
||||
s0_axi4_arprot : in std_logic_vector(2 downto 0) := (others => 'X'); -- axi4_ch0_arprot
|
||||
s0_axi4_arready : out std_logic; -- axi4_ch0_arready
|
||||
s0_axi4_wdata : in std_logic_vector(255 downto 0) := (others => 'X'); -- axi4_ch0_wdata
|
||||
s0_axi4_wstrb : in std_logic_vector(31 downto 0) := (others => 'X'); -- axi4_ch0_wstrb
|
||||
s0_axi4_wlast : in std_logic := 'X'; -- axi4_ch0_wlast
|
||||
s0_axi4_wvalid : in std_logic := 'X'; -- axi4_ch0_wvalid
|
||||
s0_axi4_wready : out std_logic; -- axi4_ch0_wready
|
||||
s0_axi4_bready : in std_logic := 'X'; -- axi4_ch0_bready
|
||||
s0_axi4_bid : out std_logic_vector(6 downto 0); -- axi4_ch0_bid
|
||||
s0_axi4_bresp : out std_logic_vector(1 downto 0); -- axi4_ch0_bresp
|
||||
s0_axi4_bvalid : out std_logic; -- axi4_ch0_bvalid
|
||||
s0_axi4_rready : in std_logic := 'X'; -- axi4_ch0_rready
|
||||
s0_axi4_rdata : out std_logic_vector(255 downto 0); -- axi4_ch0_rdata
|
||||
s0_axi4_rid : out std_logic_vector(6 downto 0); -- axi4_ch0_rid
|
||||
s0_axi4_rlast : out std_logic; -- axi4_ch0_rlast
|
||||
s0_axi4_rresp : out std_logic_vector(1 downto 0); -- axi4_ch0_rresp
|
||||
s0_axi4_rvalid : out std_logic; -- axi4_ch0_rvalid
|
||||
noc_aclk_0 : out std_logic; -- axi4_ch0_clk
|
||||
noc_rst_n_0 : out std_logic; -- axi4_ch0_reset_n
|
||||
s0_axi4_wuser : in std_logic_vector(31 downto 0) := (others => 'X'); -- axi4_ch0_wuser
|
||||
s0_axi4_ruser : out std_logic_vector(31 downto 0); -- axi4_ch0_ruser
|
||||
mem_0_cs : out std_logic_vector(0 downto 0); -- mem_cs
|
||||
mem_0_ca : out std_logic_vector(5 downto 0); -- mem_ca
|
||||
mem_0_cke : out std_logic_vector(0 downto 0); -- mem_cke
|
||||
mem_0_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
|
||||
mem_0_dqs_t : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_t
|
||||
mem_0_dqs_c : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_c
|
||||
mem_0_dmi : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dmi
|
||||
mem_0_ck_t : out std_logic_vector(0 downto 0); -- mem_ck_t
|
||||
mem_0_ck_c : out std_logic_vector(0 downto 0); -- mem_ck_c
|
||||
mem_0_reset_n : out std_logic; -- mem_reset_n
|
||||
oct_rzqin_0 : in std_logic := 'X'; -- oct_rzqin
|
||||
ref_clk : in std_logic := 'X' -- clk
|
||||
);
|
||||
end component emif_io96b_hps_emif_io96b_hps_420_dyxenzq;
|
||||
|
||||
u0 : component emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
port map (
|
||||
s0_noc_axi4lite_clock => CONNECTED_TO_s0_noc_axi4lite_clock, -- io96b0_to_hps.ch0_axil_clk
|
||||
s0_noc_axi4lite_reset_n => CONNECTED_TO_s0_noc_axi4lite_reset_n, -- .ch0_axil_reset_n
|
||||
s0_noc_axi4lite_awaddr => CONNECTED_TO_s0_noc_axi4lite_awaddr, -- .ch0_axil_awaddr
|
||||
s0_noc_axi4lite_awvalid => CONNECTED_TO_s0_noc_axi4lite_awvalid, -- .ch0_axil_awvalid
|
||||
s0_noc_axi4lite_awready => CONNECTED_TO_s0_noc_axi4lite_awready, -- .ch0_axil_awready
|
||||
s0_noc_axi4lite_araddr => CONNECTED_TO_s0_noc_axi4lite_araddr, -- .ch0_axil_araddr
|
||||
s0_noc_axi4lite_arvalid => CONNECTED_TO_s0_noc_axi4lite_arvalid, -- .ch0_axil_arvalid
|
||||
s0_noc_axi4lite_arready => CONNECTED_TO_s0_noc_axi4lite_arready, -- .ch0_axil_arready
|
||||
s0_noc_axi4lite_wdata => CONNECTED_TO_s0_noc_axi4lite_wdata, -- .ch0_axil_wdata
|
||||
s0_noc_axi4lite_wvalid => CONNECTED_TO_s0_noc_axi4lite_wvalid, -- .ch0_axil_wvalid
|
||||
s0_noc_axi4lite_wready => CONNECTED_TO_s0_noc_axi4lite_wready, -- .ch0_axil_wready
|
||||
s0_noc_axi4lite_rresp => CONNECTED_TO_s0_noc_axi4lite_rresp, -- .ch0_axil_rresp
|
||||
s0_noc_axi4lite_rdata => CONNECTED_TO_s0_noc_axi4lite_rdata, -- .ch0_axil_rdata
|
||||
s0_noc_axi4lite_rvalid => CONNECTED_TO_s0_noc_axi4lite_rvalid, -- .ch0_axil_rvalid
|
||||
s0_noc_axi4lite_rready => CONNECTED_TO_s0_noc_axi4lite_rready, -- .ch0_axil_rready
|
||||
s0_noc_axi4lite_bresp => CONNECTED_TO_s0_noc_axi4lite_bresp, -- .ch0_axil_bresp
|
||||
s0_noc_axi4lite_bvalid => CONNECTED_TO_s0_noc_axi4lite_bvalid, -- .ch0_axil_bvalid
|
||||
s0_noc_axi4lite_bready => CONNECTED_TO_s0_noc_axi4lite_bready, -- .ch0_axil_bready
|
||||
s0_noc_axi4lite_awprot => CONNECTED_TO_s0_noc_axi4lite_awprot, -- .ch0_axil_awprot
|
||||
s0_noc_axi4lite_arprot => CONNECTED_TO_s0_noc_axi4lite_arprot, -- .ch0_axil_arprot
|
||||
s0_noc_axi4lite_wstrb => CONNECTED_TO_s0_noc_axi4lite_wstrb, -- .ch0_axil_wstrb
|
||||
s0_axi4_awaddr => CONNECTED_TO_s0_axi4_awaddr, -- .axi4_ch0_awaddr
|
||||
s0_axi4_awburst => CONNECTED_TO_s0_axi4_awburst, -- .axi4_ch0_awburst
|
||||
s0_axi4_awid => CONNECTED_TO_s0_axi4_awid, -- .axi4_ch0_awid
|
||||
s0_axi4_awlen => CONNECTED_TO_s0_axi4_awlen, -- .axi4_ch0_awlen
|
||||
s0_axi4_awlock => CONNECTED_TO_s0_axi4_awlock, -- .axi4_ch0_awlock
|
||||
s0_axi4_awqos => CONNECTED_TO_s0_axi4_awqos, -- .axi4_ch0_awqos
|
||||
s0_axi4_awsize => CONNECTED_TO_s0_axi4_awsize, -- .axi4_ch0_awsize
|
||||
s0_axi4_awvalid => CONNECTED_TO_s0_axi4_awvalid, -- .axi4_ch0_awvalid
|
||||
s0_axi4_awuser => CONNECTED_TO_s0_axi4_awuser, -- .axi4_ch0_awuser
|
||||
s0_axi4_awprot => CONNECTED_TO_s0_axi4_awprot, -- .axi4_ch0_awprot
|
||||
s0_axi4_awready => CONNECTED_TO_s0_axi4_awready, -- .axi4_ch0_awready
|
||||
s0_axi4_araddr => CONNECTED_TO_s0_axi4_araddr, -- .axi4_ch0_araddr
|
||||
s0_axi4_arburst => CONNECTED_TO_s0_axi4_arburst, -- .axi4_ch0_arburst
|
||||
s0_axi4_arid => CONNECTED_TO_s0_axi4_arid, -- .axi4_ch0_arid
|
||||
s0_axi4_arlen => CONNECTED_TO_s0_axi4_arlen, -- .axi4_ch0_arlen
|
||||
s0_axi4_arlock => CONNECTED_TO_s0_axi4_arlock, -- .axi4_ch0_arlock
|
||||
s0_axi4_arqos => CONNECTED_TO_s0_axi4_arqos, -- .axi4_ch0_arqos
|
||||
s0_axi4_arsize => CONNECTED_TO_s0_axi4_arsize, -- .axi4_ch0_arsize
|
||||
s0_axi4_arvalid => CONNECTED_TO_s0_axi4_arvalid, -- .axi4_ch0_arvalid
|
||||
s0_axi4_aruser => CONNECTED_TO_s0_axi4_aruser, -- .axi4_ch0_aruser
|
||||
s0_axi4_arprot => CONNECTED_TO_s0_axi4_arprot, -- .axi4_ch0_arprot
|
||||
s0_axi4_arready => CONNECTED_TO_s0_axi4_arready, -- .axi4_ch0_arready
|
||||
s0_axi4_wdata => CONNECTED_TO_s0_axi4_wdata, -- .axi4_ch0_wdata
|
||||
s0_axi4_wstrb => CONNECTED_TO_s0_axi4_wstrb, -- .axi4_ch0_wstrb
|
||||
s0_axi4_wlast => CONNECTED_TO_s0_axi4_wlast, -- .axi4_ch0_wlast
|
||||
s0_axi4_wvalid => CONNECTED_TO_s0_axi4_wvalid, -- .axi4_ch0_wvalid
|
||||
s0_axi4_wready => CONNECTED_TO_s0_axi4_wready, -- .axi4_ch0_wready
|
||||
s0_axi4_bready => CONNECTED_TO_s0_axi4_bready, -- .axi4_ch0_bready
|
||||
s0_axi4_bid => CONNECTED_TO_s0_axi4_bid, -- .axi4_ch0_bid
|
||||
s0_axi4_bresp => CONNECTED_TO_s0_axi4_bresp, -- .axi4_ch0_bresp
|
||||
s0_axi4_bvalid => CONNECTED_TO_s0_axi4_bvalid, -- .axi4_ch0_bvalid
|
||||
s0_axi4_rready => CONNECTED_TO_s0_axi4_rready, -- .axi4_ch0_rready
|
||||
s0_axi4_rdata => CONNECTED_TO_s0_axi4_rdata, -- .axi4_ch0_rdata
|
||||
s0_axi4_rid => CONNECTED_TO_s0_axi4_rid, -- .axi4_ch0_rid
|
||||
s0_axi4_rlast => CONNECTED_TO_s0_axi4_rlast, -- .axi4_ch0_rlast
|
||||
s0_axi4_rresp => CONNECTED_TO_s0_axi4_rresp, -- .axi4_ch0_rresp
|
||||
s0_axi4_rvalid => CONNECTED_TO_s0_axi4_rvalid, -- .axi4_ch0_rvalid
|
||||
noc_aclk_0 => CONNECTED_TO_noc_aclk_0, -- .axi4_ch0_clk
|
||||
noc_rst_n_0 => CONNECTED_TO_noc_rst_n_0, -- .axi4_ch0_reset_n
|
||||
s0_axi4_wuser => CONNECTED_TO_s0_axi4_wuser, -- .axi4_ch0_wuser
|
||||
s0_axi4_ruser => CONNECTED_TO_s0_axi4_ruser, -- .axi4_ch0_ruser
|
||||
mem_0_cs => CONNECTED_TO_mem_0_cs, -- mem_0.mem_cs
|
||||
mem_0_ca => CONNECTED_TO_mem_0_ca, -- .mem_ca
|
||||
mem_0_cke => CONNECTED_TO_mem_0_cke, -- .mem_cke
|
||||
mem_0_dq => CONNECTED_TO_mem_0_dq, -- .mem_dq
|
||||
mem_0_dqs_t => CONNECTED_TO_mem_0_dqs_t, -- .mem_dqs_t
|
||||
mem_0_dqs_c => CONNECTED_TO_mem_0_dqs_c, -- .mem_dqs_c
|
||||
mem_0_dmi => CONNECTED_TO_mem_0_dmi, -- .mem_dmi
|
||||
mem_0_ck_t => CONNECTED_TO_mem_0_ck_t, -- mem_ck_0.mem_ck_t
|
||||
mem_0_ck_c => CONNECTED_TO_mem_0_ck_c, -- .mem_ck_c
|
||||
mem_0_reset_n => CONNECTED_TO_mem_0_reset_n, -- mem_reset_n.mem_reset_n
|
||||
oct_rzqin_0 => CONNECTED_TO_oct_rzqin_0, -- oct_0.oct_rzqin
|
||||
ref_clk => CONNECTED_TO_ref_clk -- ref_clk.clk
|
||||
);
|
||||
|
||||
+475
@@ -0,0 +1,475 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script rivierapro_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Intel simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "aldec.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog -sv2k5 <your compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If emif_io96b_hps_emif_io96b_hps_420_dyxenzq is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "emif_io96b_hps_emif_io96b_hps_420_dyxenzq.emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "/opt/altera_pro/26.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_SIM_LIB_DIR] {
|
||||
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists DEVICES_SIM_LIB_DIR] {
|
||||
set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists SILENCE] {
|
||||
set SILENCE "false"
|
||||
}
|
||||
|
||||
if ![info exists PRECOMP_DEVICE_LIB_FILE] {
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
|
||||
|
||||
#-------------------------------------------
|
||||
# read .tcl file to override initialized variables
|
||||
if { [info exists ::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)] && [file exist $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)] } {
|
||||
echo "Sourcing $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)"
|
||||
source $::env(QSYS_SIM_SCRIPT_RIVIERA_OPTIONS_FILE)
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Source Common Tcl File
|
||||
source $QSYS_SIMDIR/common/riviera_files.tcl
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
if { ![ string match "*-64 vsim*" [ vsim -version ] ] } {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_32"
|
||||
} else {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_64"
|
||||
}
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
|
||||
setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
|
||||
}
|
||||
append ELAB_OPTIONS [subst [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append SIM_OPTIONS [subst [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_sim_options $SIMULATOR_TOOL_BITNESS]]
|
||||
|
||||
#-------------------------------------------
|
||||
# Check if $PRECOMP_DEVICE_LIB_FILE is set and points to correct file
|
||||
if { $PRECOMP_DEVICE_LIB_FILE ne "" } {
|
||||
set PRECOMP_DEVICE_LIB_FILE [string trim $PRECOMP_DEVICE_LIB_FILE]
|
||||
if { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match [file tail $PRECOMP_DEVICE_LIB_FILE] "library.cfg" ] } {
|
||||
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
|
||||
} else {
|
||||
echo "Unable to use $PRECOMP_DEVICE_LIB_FILE for device library mapping. Switching back to local library compilation"
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
}
|
||||
|
||||
set Aldec "Riviera"
|
||||
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
|
||||
set Aldec "Active"
|
||||
}
|
||||
|
||||
if { [ string match "Active" $Aldec ] } {
|
||||
scripterconf -tcl
|
||||
createdesign "$TOP_LEVEL_NAME" "."
|
||||
opendesign "$TOP_LEVEL_NAME"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files {
|
||||
set itercount 0
|
||||
while {$itercount < 10 && [file type $file] eq "link"} {
|
||||
set nf [file readlink $file]
|
||||
if {[string index $nf 0] ne "/"} {
|
||||
set nf [file dirname $file]/$nf
|
||||
}
|
||||
set file $nf
|
||||
}
|
||||
set dest_file [file join ./ [file tail $file]]
|
||||
set normalized_src [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::normalize_path "$file"]
|
||||
set normalized_dest [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::normalize_path "$dest_file"]
|
||||
if { $normalized_src ne $normalized_dest } {
|
||||
file copy -force $file ./
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
|
||||
set logical_libraries [list "work" "work_lib" "lpm_ver" "sgate_ver" "altera_ver" "altera_mf_ver" "altera_lnsim_ver" "tennm_ver" "tennm_sm_hps_ver" "tennm_sm4_hssi_ver" "tennm_revb_hvio_ver" "tennm_revb_io96_ver" "lpm" "sgate" "altera" "altera_mf" "altera_lnsim" "tennm" "tennm_sm_hps" "tennm_sm4_hssi" "tennm_revb_hvio" "tennm_revb_io96"]
|
||||
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
|
||||
# ----------------------------------------
|
||||
# setup shared libraries
|
||||
set DPI_LIBRARIES_ELAB ""
|
||||
if { [llength $dpi_libraries] != 0 } {
|
||||
echo "Using DPI Library settings"
|
||||
foreach library $dpi_libraries {
|
||||
append DPI_LIBRARIES_ELAB "-sv_lib $library "
|
||||
}
|
||||
}
|
||||
|
||||
ensure_lib ./libraries/
|
||||
ensure_lib ./libraries/work
|
||||
vmap work ./libraries/work
|
||||
if { $PRECOMP_DEVICE_LIB_FILE eq "" } {
|
||||
ensure_lib ./libraries/lpm_ver
|
||||
vmap lpm_ver ./libraries/lpm_ver
|
||||
ensure_lib ./libraries/sgate_ver
|
||||
vmap sgate_ver ./libraries/sgate_ver
|
||||
ensure_lib ./libraries/altera_ver
|
||||
vmap altera_ver ./libraries/altera_ver
|
||||
ensure_lib ./libraries/altera_mf_ver
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver
|
||||
ensure_lib ./libraries/altera_lnsim_ver
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
|
||||
ensure_lib ./libraries/tennm_ver
|
||||
vmap tennm_ver ./libraries/tennm_ver
|
||||
ensure_lib ./libraries/tennm_sm_hps_ver
|
||||
vmap tennm_sm_hps_ver ./libraries/tennm_sm_hps_ver
|
||||
ensure_lib ./libraries/tennm_sm4_hssi_ver
|
||||
vmap tennm_sm4_hssi_ver ./libraries/tennm_sm4_hssi_ver
|
||||
ensure_lib ./libraries/tennm_revb_hvio_ver
|
||||
vmap tennm_revb_hvio_ver ./libraries/tennm_revb_hvio_ver
|
||||
ensure_lib ./libraries/tennm_revb_io96_ver
|
||||
vmap tennm_revb_io96_ver ./libraries/tennm_revb_io96_ver
|
||||
ensure_lib ./libraries/lpm
|
||||
vmap lpm ./libraries/lpm
|
||||
ensure_lib ./libraries/sgate
|
||||
vmap sgate ./libraries/sgate
|
||||
ensure_lib ./libraries/altera
|
||||
vmap altera ./libraries/altera
|
||||
ensure_lib ./libraries/altera_mf
|
||||
vmap altera_mf ./libraries/altera_mf
|
||||
ensure_lib ./libraries/altera_lnsim
|
||||
vmap altera_lnsim ./libraries/altera_lnsim
|
||||
ensure_lib ./libraries/tennm
|
||||
vmap tennm ./libraries/tennm
|
||||
ensure_lib ./libraries/tennm_sm_hps
|
||||
vmap tennm_sm_hps ./libraries/tennm_sm_hps
|
||||
ensure_lib ./libraries/tennm_sm4_hssi
|
||||
vmap tennm_sm4_hssi ./libraries/tennm_sm4_hssi
|
||||
ensure_lib ./libraries/tennm_revb_hvio
|
||||
vmap tennm_revb_hvio ./libraries/tennm_revb_hvio
|
||||
ensure_lib ./libraries/tennm_revb_io96
|
||||
vmap tennm_revb_io96 ./libraries/tennm_revb_io96
|
||||
} else {
|
||||
vmap -link $PRECOMP_DEVICE_LIB_FILE
|
||||
}
|
||||
set design_libraries [dict create]
|
||||
set design_libraries [dict merge $design_libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_libraries]]
|
||||
set libraries [dict keys $design_libraries]
|
||||
foreach library $libraries {
|
||||
ensure_lib ./libraries/$library/
|
||||
vmap $library ./libraries/$library/
|
||||
lappend logical_libraries $library
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] dev_com"
|
||||
}
|
||||
if { $PRECOMP_DEVICE_LIB_FILE eq "" } {
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
|
||||
eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/aldec/tennm_atoms_ncrypt.sv" -work tennm_ver
|
||||
eval vlog -dpilib +define+fm7_fmica_SVA_OFF $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/aldec/tennm_atoms_ncrypt.sv" -work tennm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
|
||||
eval vlog -err VCP2675 W1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
||||
}
|
||||
ccomp -dpi -sc -o work "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# add device library elaboration and simulation properties
|
||||
append ELAB_OPTIONS " -sv_lib work"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] com"
|
||||
}
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
||||
set common_design_files [dict values $design_files]
|
||||
foreach file $common_design_files {
|
||||
eval $file
|
||||
}
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $design_files {
|
||||
eval $file
|
||||
}
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim +access +r $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -dbg -O2 option
|
||||
alias elab_debug {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab_debug"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim -dbg -O2 +access +r $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -dbg -O2
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Qsys base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
|
||||
echo
|
||||
echo "PRECOMP_DEVICE_LIB_FILE -- Precompiled device library file."
|
||||
echo " Use this variable to provide library.cfg containing device library mapping and dev_com will be skipped"
|
||||
echo " If value is empty, device libraries will be compiled local"
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script run_rivierapro_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to run the rivierapro_setup.tcl script for the following IP detected in
|
||||
# your Quartus project:
|
||||
# emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
#
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script to compile, elab and run the design without any customization.
|
||||
# For customization, please follow the steps mentioned in rivierapro_setup.tcl.
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
|
||||
ld
|
||||
run -all
|
||||
quit
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/common/modelsim_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/common/modelsim_files.tcl]
|
||||
|
||||
namespace eval emif_io96b_hps_emif_io96b_hps_420_dyxenzq {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_libraries]]
|
||||
dict set libraries emif_io96b_hps_emif_io96b_hps_420_dyxenzq 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_common_design_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_common_design_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_common_design_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "-makelib emif_io96b_hps_emif_io96b_hps_420_dyxenzq \"[normalize_path "$QSYS_SIMDIR/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v"]\" -end"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc normalize_path {FILEPATH} {
|
||||
if {[catch { package require fileutil } err]} {
|
||||
return $FILEPATH
|
||||
}
|
||||
set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
|
||||
if {[file pathtype $FILEPATH] eq "relative"} {
|
||||
set path [fileutil::relative [pwd] $path]
|
||||
}
|
||||
return $path
|
||||
}
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/common/riviera_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/common/riviera_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/common/riviera_files.tcl]
|
||||
|
||||
namespace eval emif_io96b_hps_emif_io96b_hps_420_dyxenzq {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_libraries]]
|
||||
dict set libraries emif_io96b_hps_emif_io96b_hps_420_dyxenzq 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"[normalize_path "$QSYS_SIMDIR/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v"]\" -work emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc normalize_path {FILEPATH} {
|
||||
if {[catch { package require fileutil } err]} {
|
||||
return $FILEPATH
|
||||
}
|
||||
set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]
|
||||
if {[file pathtype $FILEPATH] eq "relative"} {
|
||||
set path [fileutil::relative [pwd] $path]
|
||||
}
|
||||
return $path
|
||||
}
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/common/vcsmx_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/common/vcsmx_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/common/vcsmx_files.tcl]
|
||||
|
||||
namespace eval emif_io96b_hps_emif_io96b_hps_420_dyxenzq {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_libraries]]
|
||||
dict set libraries emif_io96b_hps_emif_io96b_hps_420_dyxenzq 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v\" -work emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/common/xcelium_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/common/xcelium_files.tcl]
|
||||
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/common/xcelium_files.tcl]
|
||||
|
||||
namespace eval emif_io96b_hps_emif_io96b_hps_420_dyxenzq {
|
||||
proc get_design_libraries {} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_libraries]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_libraries]]
|
||||
dict set libraries emif_io96b_hps_emif_io96b_hps_420_dyxenzq 1
|
||||
return $libraries
|
||||
}
|
||||
|
||||
proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
return $memory_files
|
||||
}
|
||||
|
||||
proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
|
||||
set design_files [dict create]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
|
||||
lappend design_files "xmvlog -zlib 1 -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS \"$QSYS_SIMDIR/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v\" -work emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
return $design_files
|
||||
}
|
||||
|
||||
proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
|
||||
set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
|
||||
if {$IS_DUPLICATE == -1} {
|
||||
return $NEW_ELAB_OPTION
|
||||
} else {
|
||||
return ""
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ELAB_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $SIM_OPTIONS
|
||||
}
|
||||
|
||||
|
||||
proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
|
||||
set ENV_VARIABLES [dict create]
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
|
||||
if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
|
||||
} else {
|
||||
}
|
||||
return $ENV_VARIABLES
|
||||
}
|
||||
|
||||
|
||||
proc get_dpi_libraries {QSYS_SIMDIR} {
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
|
||||
|
||||
return $libraries
|
||||
}
|
||||
|
||||
}
|
||||
+176
@@ -0,0 +1,176 @@
|
||||
// emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq (
|
||||
output wire s0_noc_axi4lite_clock, // io96b0_to_hps.ch0_axil_clk
|
||||
output wire s0_noc_axi4lite_reset_n, // .ch0_axil_reset_n
|
||||
input wire [26:0] s0_noc_axi4lite_awaddr, // .ch0_axil_awaddr
|
||||
input wire s0_noc_axi4lite_awvalid, // .ch0_axil_awvalid
|
||||
output wire s0_noc_axi4lite_awready, // .ch0_axil_awready
|
||||
input wire [26:0] s0_noc_axi4lite_araddr, // .ch0_axil_araddr
|
||||
input wire s0_noc_axi4lite_arvalid, // .ch0_axil_arvalid
|
||||
output wire s0_noc_axi4lite_arready, // .ch0_axil_arready
|
||||
input wire [31:0] s0_noc_axi4lite_wdata, // .ch0_axil_wdata
|
||||
input wire s0_noc_axi4lite_wvalid, // .ch0_axil_wvalid
|
||||
output wire s0_noc_axi4lite_wready, // .ch0_axil_wready
|
||||
output wire [1:0] s0_noc_axi4lite_rresp, // .ch0_axil_rresp
|
||||
output wire [31:0] s0_noc_axi4lite_rdata, // .ch0_axil_rdata
|
||||
output wire s0_noc_axi4lite_rvalid, // .ch0_axil_rvalid
|
||||
input wire s0_noc_axi4lite_rready, // .ch0_axil_rready
|
||||
output wire [1:0] s0_noc_axi4lite_bresp, // .ch0_axil_bresp
|
||||
output wire s0_noc_axi4lite_bvalid, // .ch0_axil_bvalid
|
||||
input wire s0_noc_axi4lite_bready, // .ch0_axil_bready
|
||||
input wire [2:0] s0_noc_axi4lite_awprot, // .ch0_axil_awprot
|
||||
input wire [2:0] s0_noc_axi4lite_arprot, // .ch0_axil_arprot
|
||||
input wire [3:0] s0_noc_axi4lite_wstrb, // .ch0_axil_wstrb
|
||||
input wire [39:0] s0_axi4_awaddr, // .axi4_ch0_awaddr
|
||||
input wire [1:0] s0_axi4_awburst, // .axi4_ch0_awburst
|
||||
input wire [6:0] s0_axi4_awid, // .axi4_ch0_awid
|
||||
input wire [7:0] s0_axi4_awlen, // .axi4_ch0_awlen
|
||||
input wire s0_axi4_awlock, // .axi4_ch0_awlock
|
||||
input wire [3:0] s0_axi4_awqos, // .axi4_ch0_awqos
|
||||
input wire [2:0] s0_axi4_awsize, // .axi4_ch0_awsize
|
||||
input wire s0_axi4_awvalid, // .axi4_ch0_awvalid
|
||||
input wire [13:0] s0_axi4_awuser, // .axi4_ch0_awuser
|
||||
input wire [2:0] s0_axi4_awprot, // .axi4_ch0_awprot
|
||||
output wire s0_axi4_awready, // .axi4_ch0_awready
|
||||
input wire [39:0] s0_axi4_araddr, // .axi4_ch0_araddr
|
||||
input wire [1:0] s0_axi4_arburst, // .axi4_ch0_arburst
|
||||
input wire [6:0] s0_axi4_arid, // .axi4_ch0_arid
|
||||
input wire [7:0] s0_axi4_arlen, // .axi4_ch0_arlen
|
||||
input wire s0_axi4_arlock, // .axi4_ch0_arlock
|
||||
input wire [3:0] s0_axi4_arqos, // .axi4_ch0_arqos
|
||||
input wire [2:0] s0_axi4_arsize, // .axi4_ch0_arsize
|
||||
input wire s0_axi4_arvalid, // .axi4_ch0_arvalid
|
||||
input wire [13:0] s0_axi4_aruser, // .axi4_ch0_aruser
|
||||
input wire [2:0] s0_axi4_arprot, // .axi4_ch0_arprot
|
||||
output wire s0_axi4_arready, // .axi4_ch0_arready
|
||||
input wire [255:0] s0_axi4_wdata, // .axi4_ch0_wdata
|
||||
input wire [31:0] s0_axi4_wstrb, // .axi4_ch0_wstrb
|
||||
input wire s0_axi4_wlast, // .axi4_ch0_wlast
|
||||
input wire s0_axi4_wvalid, // .axi4_ch0_wvalid
|
||||
output wire s0_axi4_wready, // .axi4_ch0_wready
|
||||
input wire s0_axi4_bready, // .axi4_ch0_bready
|
||||
output wire [6:0] s0_axi4_bid, // .axi4_ch0_bid
|
||||
output wire [1:0] s0_axi4_bresp, // .axi4_ch0_bresp
|
||||
output wire s0_axi4_bvalid, // .axi4_ch0_bvalid
|
||||
input wire s0_axi4_rready, // .axi4_ch0_rready
|
||||
output wire [255:0] s0_axi4_rdata, // .axi4_ch0_rdata
|
||||
output wire [6:0] s0_axi4_rid, // .axi4_ch0_rid
|
||||
output wire s0_axi4_rlast, // .axi4_ch0_rlast
|
||||
output wire [1:0] s0_axi4_rresp, // .axi4_ch0_rresp
|
||||
output wire s0_axi4_rvalid, // .axi4_ch0_rvalid
|
||||
output wire noc_aclk_0, // .axi4_ch0_clk
|
||||
output wire noc_rst_n_0, // .axi4_ch0_reset_n
|
||||
input wire [31:0] s0_axi4_wuser, // .axi4_ch0_wuser
|
||||
output wire [31:0] s0_axi4_ruser, // .axi4_ch0_ruser
|
||||
output wire [0:0] mem_0_cs, // mem_0.mem_cs
|
||||
output wire [5:0] mem_0_ca, // .mem_ca
|
||||
output wire [0:0] mem_0_cke, // .mem_cke
|
||||
inout wire [31:0] mem_0_dq, // .mem_dq
|
||||
inout wire [3:0] mem_0_dqs_t, // .mem_dqs_t
|
||||
inout wire [3:0] mem_0_dqs_c, // .mem_dqs_c
|
||||
inout wire [3:0] mem_0_dmi, // .mem_dmi
|
||||
output wire [0:0] mem_0_ck_t, // mem_ck_0.mem_ck_t
|
||||
output wire [0:0] mem_0_ck_c, // .mem_ck_c
|
||||
output wire mem_0_reset_n, // mem_reset_n.mem_reset_n
|
||||
input wire oct_rzqin_0, // oct_0.oct_rzqin
|
||||
input wire ref_clk // ref_clk.clk
|
||||
);
|
||||
|
||||
wire refclk_bridge_refclk_out_clk; // refclk_bridge:refclk_out -> emif_0_lpddr4:ref_clk
|
||||
wire [0:0] refclk_gpio_dout_export; // refclk_gpio:dout -> refclk_bridge:refclk_out_gpio
|
||||
wire refclk_bridge_refclk_in_gpio_export; // refclk_bridge:refclk_in_gpio -> refclk_gpio:pad_in
|
||||
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4 emif_0_lpddr4 (
|
||||
.s0_noc_axi4lite_clock (s0_noc_axi4lite_clock), // output, width = 1, io96b0_to_hps.ch0_axil_clk
|
||||
.s0_noc_axi4lite_reset_n (s0_noc_axi4lite_reset_n), // output, width = 1, .ch0_axil_reset_n
|
||||
.s0_noc_axi4lite_awaddr (s0_noc_axi4lite_awaddr), // input, width = 27, .ch0_axil_awaddr
|
||||
.s0_noc_axi4lite_awvalid (s0_noc_axi4lite_awvalid), // input, width = 1, .ch0_axil_awvalid
|
||||
.s0_noc_axi4lite_awready (s0_noc_axi4lite_awready), // output, width = 1, .ch0_axil_awready
|
||||
.s0_noc_axi4lite_araddr (s0_noc_axi4lite_araddr), // input, width = 27, .ch0_axil_araddr
|
||||
.s0_noc_axi4lite_arvalid (s0_noc_axi4lite_arvalid), // input, width = 1, .ch0_axil_arvalid
|
||||
.s0_noc_axi4lite_arready (s0_noc_axi4lite_arready), // output, width = 1, .ch0_axil_arready
|
||||
.s0_noc_axi4lite_wdata (s0_noc_axi4lite_wdata), // input, width = 32, .ch0_axil_wdata
|
||||
.s0_noc_axi4lite_wvalid (s0_noc_axi4lite_wvalid), // input, width = 1, .ch0_axil_wvalid
|
||||
.s0_noc_axi4lite_wready (s0_noc_axi4lite_wready), // output, width = 1, .ch0_axil_wready
|
||||
.s0_noc_axi4lite_rresp (s0_noc_axi4lite_rresp), // output, width = 2, .ch0_axil_rresp
|
||||
.s0_noc_axi4lite_rdata (s0_noc_axi4lite_rdata), // output, width = 32, .ch0_axil_rdata
|
||||
.s0_noc_axi4lite_rvalid (s0_noc_axi4lite_rvalid), // output, width = 1, .ch0_axil_rvalid
|
||||
.s0_noc_axi4lite_rready (s0_noc_axi4lite_rready), // input, width = 1, .ch0_axil_rready
|
||||
.s0_noc_axi4lite_bresp (s0_noc_axi4lite_bresp), // output, width = 2, .ch0_axil_bresp
|
||||
.s0_noc_axi4lite_bvalid (s0_noc_axi4lite_bvalid), // output, width = 1, .ch0_axil_bvalid
|
||||
.s0_noc_axi4lite_bready (s0_noc_axi4lite_bready), // input, width = 1, .ch0_axil_bready
|
||||
.s0_noc_axi4lite_awprot (s0_noc_axi4lite_awprot), // input, width = 3, .ch0_axil_awprot
|
||||
.s0_noc_axi4lite_arprot (s0_noc_axi4lite_arprot), // input, width = 3, .ch0_axil_arprot
|
||||
.s0_noc_axi4lite_wstrb (s0_noc_axi4lite_wstrb), // input, width = 4, .ch0_axil_wstrb
|
||||
.s0_axi4_awaddr (s0_axi4_awaddr), // input, width = 40, .axi4_ch0_awaddr
|
||||
.s0_axi4_awburst (s0_axi4_awburst), // input, width = 2, .axi4_ch0_awburst
|
||||
.s0_axi4_awid (s0_axi4_awid), // input, width = 7, .axi4_ch0_awid
|
||||
.s0_axi4_awlen (s0_axi4_awlen), // input, width = 8, .axi4_ch0_awlen
|
||||
.s0_axi4_awlock (s0_axi4_awlock), // input, width = 1, .axi4_ch0_awlock
|
||||
.s0_axi4_awqos (s0_axi4_awqos), // input, width = 4, .axi4_ch0_awqos
|
||||
.s0_axi4_awsize (s0_axi4_awsize), // input, width = 3, .axi4_ch0_awsize
|
||||
.s0_axi4_awvalid (s0_axi4_awvalid), // input, width = 1, .axi4_ch0_awvalid
|
||||
.s0_axi4_awuser (s0_axi4_awuser), // input, width = 14, .axi4_ch0_awuser
|
||||
.s0_axi4_awprot (s0_axi4_awprot), // input, width = 3, .axi4_ch0_awprot
|
||||
.s0_axi4_awready (s0_axi4_awready), // output, width = 1, .axi4_ch0_awready
|
||||
.s0_axi4_araddr (s0_axi4_araddr), // input, width = 40, .axi4_ch0_araddr
|
||||
.s0_axi4_arburst (s0_axi4_arburst), // input, width = 2, .axi4_ch0_arburst
|
||||
.s0_axi4_arid (s0_axi4_arid), // input, width = 7, .axi4_ch0_arid
|
||||
.s0_axi4_arlen (s0_axi4_arlen), // input, width = 8, .axi4_ch0_arlen
|
||||
.s0_axi4_arlock (s0_axi4_arlock), // input, width = 1, .axi4_ch0_arlock
|
||||
.s0_axi4_arqos (s0_axi4_arqos), // input, width = 4, .axi4_ch0_arqos
|
||||
.s0_axi4_arsize (s0_axi4_arsize), // input, width = 3, .axi4_ch0_arsize
|
||||
.s0_axi4_arvalid (s0_axi4_arvalid), // input, width = 1, .axi4_ch0_arvalid
|
||||
.s0_axi4_aruser (s0_axi4_aruser), // input, width = 14, .axi4_ch0_aruser
|
||||
.s0_axi4_arprot (s0_axi4_arprot), // input, width = 3, .axi4_ch0_arprot
|
||||
.s0_axi4_arready (s0_axi4_arready), // output, width = 1, .axi4_ch0_arready
|
||||
.s0_axi4_wdata (s0_axi4_wdata), // input, width = 256, .axi4_ch0_wdata
|
||||
.s0_axi4_wstrb (s0_axi4_wstrb), // input, width = 32, .axi4_ch0_wstrb
|
||||
.s0_axi4_wlast (s0_axi4_wlast), // input, width = 1, .axi4_ch0_wlast
|
||||
.s0_axi4_wvalid (s0_axi4_wvalid), // input, width = 1, .axi4_ch0_wvalid
|
||||
.s0_axi4_wready (s0_axi4_wready), // output, width = 1, .axi4_ch0_wready
|
||||
.s0_axi4_bready (s0_axi4_bready), // input, width = 1, .axi4_ch0_bready
|
||||
.s0_axi4_bid (s0_axi4_bid), // output, width = 7, .axi4_ch0_bid
|
||||
.s0_axi4_bresp (s0_axi4_bresp), // output, width = 2, .axi4_ch0_bresp
|
||||
.s0_axi4_bvalid (s0_axi4_bvalid), // output, width = 1, .axi4_ch0_bvalid
|
||||
.s0_axi4_rready (s0_axi4_rready), // input, width = 1, .axi4_ch0_rready
|
||||
.s0_axi4_rdata (s0_axi4_rdata), // output, width = 256, .axi4_ch0_rdata
|
||||
.s0_axi4_rid (s0_axi4_rid), // output, width = 7, .axi4_ch0_rid
|
||||
.s0_axi4_rlast (s0_axi4_rlast), // output, width = 1, .axi4_ch0_rlast
|
||||
.s0_axi4_rresp (s0_axi4_rresp), // output, width = 2, .axi4_ch0_rresp
|
||||
.s0_axi4_rvalid (s0_axi4_rvalid), // output, width = 1, .axi4_ch0_rvalid
|
||||
.noc_aclk_0 (noc_aclk_0), // output, width = 1, .axi4_ch0_clk
|
||||
.noc_rst_n_0 (noc_rst_n_0), // output, width = 1, .axi4_ch0_reset_n
|
||||
.s0_axi4_wuser (s0_axi4_wuser), // input, width = 32, .axi4_ch0_wuser
|
||||
.s0_axi4_ruser (s0_axi4_ruser), // output, width = 32, .axi4_ch0_ruser
|
||||
.mem_0_cs (mem_0_cs), // output, width = 1, mem_0.mem_cs
|
||||
.mem_0_ca (mem_0_ca), // output, width = 6, .mem_ca
|
||||
.mem_0_cke (mem_0_cke), // output, width = 1, .mem_cke
|
||||
.mem_0_dq (mem_0_dq), // inout, width = 32, .mem_dq
|
||||
.mem_0_dqs_t (mem_0_dqs_t), // inout, width = 4, .mem_dqs_t
|
||||
.mem_0_dqs_c (mem_0_dqs_c), // inout, width = 4, .mem_dqs_c
|
||||
.mem_0_dmi (mem_0_dmi), // inout, width = 4, .mem_dmi
|
||||
.mem_0_ck_t (mem_0_ck_t), // output, width = 1, mem_ck_0.mem_ck_t
|
||||
.mem_0_ck_c (mem_0_ck_c), // output, width = 1, .mem_ck_c
|
||||
.mem_0_reset_n (mem_0_reset_n), // output, width = 1, mem_reset_n.mem_reset_n
|
||||
.oct_rzqin_0 (oct_rzqin_0), // input, width = 1, oct_0.oct_rzqin
|
||||
.ref_clk (refclk_bridge_refclk_out_clk) // input, width = 1, ref_clk.clk
|
||||
);
|
||||
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge refclk_bridge (
|
||||
.refclk_in (ref_clk), // input, width = 1, refclk_in.clk
|
||||
.refclk_out (refclk_bridge_refclk_out_clk), // output, width = 1, refclk_out.clk
|
||||
.refclk_in_gpio (refclk_bridge_refclk_in_gpio_export), // output, width = 1, refclk_in_gpio.export
|
||||
.refclk_out_gpio (refclk_gpio_dout_export) // input, width = 1, refclk_out_gpio.export
|
||||
);
|
||||
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio refclk_gpio (
|
||||
.dout (refclk_gpio_dout_export), // output, width = 1, dout.export
|
||||
.pad_in (refclk_bridge_refclk_in_gpio_export) // input, width = 1, pad_in.export
|
||||
);
|
||||
|
||||
endmodule
|
||||
+505
@@ -0,0 +1,505 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script msim_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Intel simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "mentor.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run -a
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If emif_io96b_hps_emif_io96b_hps_420_dyxenzq is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "emif_io96b_hps_emif_io96b_hps_420_dyxenzq.emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "/opt/altera_pro/26.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_SIM_LIB_DIR] {
|
||||
set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists DEVICES_SIM_LIB_DIR] {
|
||||
set DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
if ![info exists SILENCE] {
|
||||
set SILENCE "false"
|
||||
}
|
||||
|
||||
if ![info exists PRECOMP_DEVICE_LIB_FILE] {
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
|
||||
if ![info exists FORCE_MODELSIM_AE_SELECTION] {
|
||||
set FORCE_MODELSIM_AE_SELECTION "false"
|
||||
}
|
||||
if ![info exists ENABLE_QE_LIBRARY_COMPILATION] {
|
||||
set ENABLE_QE_LIBRARY_COMPILATION "false"
|
||||
}
|
||||
|
||||
#-------------------------------------------
|
||||
# read .tcl file to override initialized variables
|
||||
if { [info exists ::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] && [file exist $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)] } {
|
||||
echo "Sourcing $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)"
|
||||
source $::env(QSYS_SIM_SCRIPT_QUESTASIM_OPTIONS_FILE)
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Source Common Tcl File
|
||||
source $QSYS_SIMDIR/common/modelsim_files.tcl
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
if { ![ string match "*-64 vsim*" [ vsimVersionString ] ] } {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_32"
|
||||
} else {
|
||||
set SIMULATOR_TOOL_BITNESS "bit_64"
|
||||
}
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [subst [join [dict keys $LD_LIBRARY_PATH] ":"]]
|
||||
setenv LD_LIBRARY_PATH "$LD_LIBRARY_PATH"
|
||||
}
|
||||
append ELAB_OPTIONS [subst [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_elab_options $SIMULATOR_TOOL_BITNESS]]
|
||||
append SIM_OPTIONS [subst [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_sim_options $SIMULATOR_TOOL_BITNESS]]
|
||||
|
||||
proc check_precomp_device {precomp_device_lib_path force_select_modelsim_ae enable_qe_library_compilation} {
|
||||
set len [string length $precomp_device_lib_path]
|
||||
if {($len == 0) && ([string is false -strict [modelsim_ae_select $force_select_modelsim_ae]] || [string is true -strict $enable_qe_library_compilation])} {
|
||||
return 1
|
||||
}
|
||||
return 0
|
||||
|
||||
}
|
||||
|
||||
proc modelsim_ae_select {force_select_modelsim_ae} {
|
||||
if [string is true -strict $force_select_modelsim_ae] {
|
||||
return 1
|
||||
}
|
||||
return [string match -nocase "*Altera*FPGA*" [ vsimVersionString ]]
|
||||
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
set memory_files [list]
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files {
|
||||
set itercount 0
|
||||
while {$itercount < 10 && [file type $file] eq "link"} {
|
||||
set nf [file readlink $file]
|
||||
if {[string index $nf 0] ne "/"} {
|
||||
set nf [file dirname $file]/$nf
|
||||
}
|
||||
set file $nf
|
||||
}
|
||||
set dest_file [file join ./ [file tail $file]]
|
||||
set normalized_src [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::normalize_path "$file"]
|
||||
set normalized_dest [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::normalize_path "$dest_file"]
|
||||
if { $normalized_src ne $normalized_dest } {
|
||||
file copy -force $file ./
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
# ----------------------------------------
|
||||
# Modify modelsim.ini if precompiled device libraries are in use
|
||||
if { $PRECOMP_DEVICE_LIB_FILE ne "" } {
|
||||
echo "Modifying modelsim.ini according to $PRECOMP_DEVICE_LIB_FILE"
|
||||
set PRECOMP_DEVICE_LIB_FILE [string trim $PRECOMP_DEVICE_LIB_FILE]
|
||||
if { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match [file tail $PRECOMP_DEVICE_LIB_FILE] "modelsim.ini" ] } {
|
||||
if { [file exists "modelsim.ini"] } {
|
||||
echo "modelsim.ini already exists, making backup modelsim.ini.bak"
|
||||
file copy -force "modelsim.ini" "modelsim.ini.bak"
|
||||
}
|
||||
echo "Copying modelsim.ini from $PRECOMP_DEVICE_LIB_FILE"
|
||||
file copy -force $PRECOMP_DEVICE_LIB_FILE ./
|
||||
} elseif { [file exists $PRECOMP_DEVICE_LIB_FILE] && [string match "*tcl" [file tail $PRECOMP_DEVICE_LIB_FILE] ] } {
|
||||
echo "Running $PRECOMP_DEVICE_LIB_FILE to generate device library mapping"
|
||||
source $PRECOMP_DEVICE_LIB_FILE
|
||||
} else {
|
||||
echo "Unable to use $PRECOMP_DEVICE_LIB_FILE for device library mapping. Switching back to local library compilation"
|
||||
set PRECOMP_DEVICE_LIB_FILE ""
|
||||
}
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
|
||||
set logical_libraries [list "work" "work_lib" "lpm_ver" "sgate_ver" "altera_ver" "altera_mf_ver" "altera_lnsim_ver" "tennm_ver" "tennm_sm_hps_ver" "tennm_sm4_hssi_ver" "tennm_revb_hvio_ver" "tennm_revb_io96_ver" "lpm" "sgate" "altera" "altera_mf" "altera_lnsim" "tennm" "tennm_sm_hps" "tennm_sm4_hssi" "tennm_revb_hvio" "tennm_revb_io96"]
|
||||
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries/
|
||||
ensure_lib ./libraries/work/
|
||||
vmap work ./libraries/work/
|
||||
vmap work_lib ./libraries/work/
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
set libraries [dict create]
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
|
||||
# ----------------------------------------
|
||||
# setup shared libraries
|
||||
set DPI_LIBRARIES_ELAB ""
|
||||
if { [llength $dpi_libraries] != 0 } {
|
||||
echo "Using DPI Library settings"
|
||||
foreach library $dpi_libraries {
|
||||
append DPI_LIBRARIES_ELAB "-sv_lib $library "
|
||||
}
|
||||
}
|
||||
|
||||
if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] {
|
||||
ensure_lib ./libraries/lpm_ver/
|
||||
vmap lpm_ver ./libraries/lpm_ver/
|
||||
ensure_lib ./libraries/sgate_ver/
|
||||
vmap sgate_ver ./libraries/sgate_ver/
|
||||
ensure_lib ./libraries/altera_ver/
|
||||
vmap altera_ver ./libraries/altera_ver/
|
||||
ensure_lib ./libraries/altera_mf_ver/
|
||||
vmap altera_mf_ver ./libraries/altera_mf_ver/
|
||||
ensure_lib ./libraries/altera_lnsim_ver/
|
||||
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
|
||||
ensure_lib ./libraries/tennm_ver/
|
||||
vmap tennm_ver ./libraries/tennm_ver/
|
||||
ensure_lib ./libraries/tennm_sm_hps_ver/
|
||||
vmap tennm_sm_hps_ver ./libraries/tennm_sm_hps_ver/
|
||||
ensure_lib ./libraries/tennm_sm4_hssi_ver/
|
||||
vmap tennm_sm4_hssi_ver ./libraries/tennm_sm4_hssi_ver/
|
||||
ensure_lib ./libraries/tennm_revb_hvio_ver/
|
||||
vmap tennm_revb_hvio_ver ./libraries/tennm_revb_hvio_ver/
|
||||
ensure_lib ./libraries/tennm_revb_io96_ver/
|
||||
vmap tennm_revb_io96_ver ./libraries/tennm_revb_io96_ver/
|
||||
ensure_lib ./libraries/lpm/
|
||||
vmap lpm ./libraries/lpm/
|
||||
ensure_lib ./libraries/sgate/
|
||||
vmap sgate ./libraries/sgate/
|
||||
ensure_lib ./libraries/altera/
|
||||
vmap altera ./libraries/altera/
|
||||
ensure_lib ./libraries/altera_mf/
|
||||
vmap altera_mf ./libraries/altera_mf/
|
||||
ensure_lib ./libraries/altera_lnsim/
|
||||
vmap altera_lnsim ./libraries/altera_lnsim/
|
||||
ensure_lib ./libraries/tennm/
|
||||
vmap tennm ./libraries/tennm/
|
||||
ensure_lib ./libraries/tennm_sm_hps/
|
||||
vmap tennm_sm_hps ./libraries/tennm_sm_hps/
|
||||
ensure_lib ./libraries/tennm_sm4_hssi/
|
||||
vmap tennm_sm4_hssi ./libraries/tennm_sm4_hssi/
|
||||
ensure_lib ./libraries/tennm_revb_hvio/
|
||||
vmap tennm_revb_hvio ./libraries/tennm_revb_hvio/
|
||||
ensure_lib ./libraries/tennm_revb_io96/
|
||||
vmap tennm_revb_io96 ./libraries/tennm_revb_io96/
|
||||
}
|
||||
set design_libraries [dict create]
|
||||
set design_libraries [dict merge $design_libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_libraries]]
|
||||
set libraries [dict keys $design_libraries]
|
||||
foreach library $libraries {
|
||||
ensure_lib ./libraries/$library/
|
||||
vmap $library ./libraries/$library/
|
||||
lappend logical_libraries $library
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] dev_com"
|
||||
}
|
||||
if [ check_precomp_device $PRECOMP_DEVICE_LIB_FILE $FORCE_MODELSIM_AE_SELECTION $ENABLE_QE_LIBRARY_COMPILATION ] {
|
||||
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
|
||||
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
|
||||
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
|
||||
-makelib lpm_ver "$QUARTUS_SIM_LIB_DIR/220model.v" -end \
|
||||
-makelib sgate_ver "$QUARTUS_SIM_LIB_DIR/sgate.v" -end \
|
||||
-makelib altera_ver "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -end \
|
||||
-makelib altera_mf_ver "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -end \
|
||||
-makelib altera_lnsim_ver "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -end \
|
||||
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -end \
|
||||
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/mentor/tennm_atoms_ncrypt.sv" -end \
|
||||
-makelib tennm_ver "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -end \
|
||||
-makelib tennm_sm_hps_ver "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -end \
|
||||
-makelib tennm_sm_hps_ver "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -end \
|
||||
-makelib tennm_sm4_hssi_ver "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -end \
|
||||
-makelib tennm_sm4_hssi_ver "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -suppress 7061,2583,13314,2244,2283,2600,3691 -end \
|
||||
-makelib tennm_revb_hvio_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -end \
|
||||
-makelib tennm_revb_hvio_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -suppress 2583 -end \
|
||||
-makelib tennm_revb_io96_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -end \
|
||||
-makelib tennm_revb_io96_ver "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -end \
|
||||
-makelib lpm "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -end \
|
||||
-makelib lpm "$QUARTUS_SIM_LIB_DIR/220model.vhd" -end \
|
||||
-makelib sgate "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -end \
|
||||
-makelib sgate "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -end \
|
||||
-makelib altera "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -end \
|
||||
-makelib altera_mf "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -end \
|
||||
-makelib altera_mf "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -end \
|
||||
-makelib altera_lnsim "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -end \
|
||||
-makelib altera_lnsim "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -end \
|
||||
-makelib tennm "$QUARTUS_SIM_LIB_DIR/mentor/tennm_atoms_ncrypt.sv" -end \
|
||||
-makelib tennm "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -end \
|
||||
-makelib tennm "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -end \
|
||||
-makelib tennm_sm_hps "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -end \
|
||||
-makelib tennm_sm_hps "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -end \
|
||||
-makelib tennm_sm4_hssi "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -end \
|
||||
-makelib tennm_sm4_hssi "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -suppress 7061,2583,13314,2244,2283,2600,3691 -end \
|
||||
-makelib tennm_revb_hvio "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -end \
|
||||
-makelib tennm_revb_hvio "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -suppress 2583 -end \
|
||||
-makelib tennm_revb_io96 "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -end \
|
||||
-makelib tennm_revb_io96 "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -end \
|
||||
|
||||
}
|
||||
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
|
||||
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
|
||||
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
|
||||
-makelib work "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp" -end \
|
||||
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] com"
|
||||
}
|
||||
set common_design_files [dict values [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_common_design_files "$QSYS_SIMDIR"]]
|
||||
|
||||
set design_files [list]
|
||||
set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
set files [concat $common_design_files $design_files ]
|
||||
set files [join $files " \\\n"]
|
||||
set com_file [open "modelsim_com.f" w+]
|
||||
puts $com_file $files
|
||||
close $com_file
|
||||
eval qrun -compile -noautoorder -parallel -outdir ./libraries -vlog.options $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS -end \
|
||||
-vcom.options $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS -end \
|
||||
-vlog.ext=+.vo -vlog.ext=+.vt -vcom.ext=+.vho -sv -suppress 13338 \
|
||||
-f modelsim_com.f
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -voptargs=+acc option
|
||||
alias elab_debug {
|
||||
if [string is false -strict $SILENCE] {
|
||||
echo "\[exec\] elab_debug"
|
||||
}
|
||||
set elabcommand " $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS"
|
||||
foreach library $logical_libraries { append elabcommand " -L $library" }
|
||||
append elabcommand " $TOP_LEVEL_NAME $DPI_LIBRARIES_ELAB "
|
||||
eval vsim -voptargs=+acc $elabcommand
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -voptargs=+acc
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Qsys base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. "
|
||||
echo
|
||||
echo "PRECOMP_DEVICE_LIB_FILE -- Precompiled device library file."
|
||||
echo " Use this variable to provide modelsim.ini or tcl containing device library mapping and dev_com will be skipped"
|
||||
echo " If value is empty, device libraries will be compiled local"
|
||||
echo
|
||||
echo "FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always."
|
||||
echo
|
||||
echo "ENABLE_QE_LIBRARY_COMPILATION -- Set to true to enable device library compilation for Questa FE."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script run_msim_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to run the msim_setup.tcl script for the following IP detected in
|
||||
# your Quartus project:
|
||||
# emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
#
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script to compile, elab and run the design without any customization.
|
||||
# For customization, please follow the steps mentioned in msim_setup.tcl.
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
source $QSYS_SIMDIR/mentor/msim_setup.tcl
|
||||
ld
|
||||
run -all
|
||||
quit
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
-- DONOT MODIFY
|
||||
-- Contains device library mapping
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
|
||||
WORK > DEFAULT
|
||||
DEFAULT: ./libraries/work/
|
||||
work: ./libraries/work/
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq: ./libraries/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/
|
||||
OTHERS=_device_synopsys_sim.setup
|
||||
OTHERS=_default_synopsys_sim.setup
|
||||
LIBRARY_SCAN = TRUE
|
||||
+429
@@ -0,0 +1,429 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
|
||||
# ----------------------------------------
|
||||
# vcsmx - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Intel simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated library
|
||||
# # setup "synopsys_sim.setup" into the location from which you launch the
|
||||
# # simulator, or incorporate into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# #
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# vlogan <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME="'-top <simulation top>'" \
|
||||
# QSYS_SIMDIR=<script generation output directory> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If emif_io96b_hps_emif_io96b_hps_420_dyxenzq is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="emif_io96b_hps_emif_io96b_hps_420_dyxenzq.emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
|
||||
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
DEFAULT_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# check tclsh version no earlier than 8.5
|
||||
version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
|
||||
if [ $version -eq -1 ]; then
|
||||
echo "Error: Minimum required tcl package version is 8.5." >&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# read .sh file to override initialized variables
|
||||
if [ -n "${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} ]; then
|
||||
echo "Sourcing ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}"
|
||||
source ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE}
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error:: This file ${QSYS_SIM_SCRIPT_VCSMX_OPTIONS_FILE} has invalid expression/s" >&2
|
||||
exit $?
|
||||
fi
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `vcs -platform` != *"amd64"* && `vcs -platform` != *"suse64"* && `vcs -platform` != *"linux64"* ]]; then
|
||||
SIMULATOR_TOOL_BITNESS="bit_32"
|
||||
else
|
||||
SIMULATOR_TOOL_BITNESS="bit_64"
|
||||
fi
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
|
||||
puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
|
||||
}
|
||||
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_elab_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
eval $cmd_output
|
||||
|
||||
#-------------------------------------------
|
||||
# Decision to skip device compilation,
|
||||
# based on value of PRECOMP_DEVICE_LIB_FILE.
|
||||
# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
|
||||
if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
|
||||
SKIP_DEV_COM=1
|
||||
else
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
fi
|
||||
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_libraries]]
|
||||
set design_libraries [dict keys $libraries]
|
||||
foreach file $design_libraries { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver altera_lnsim_ver tennm_ver tennm_sm_hps_ver tennm_sm4_hssi_ver tennm_revb_hvio_ver tennm_revb_io96_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
fi
|
||||
|
||||
for library in $design_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
mkdir -p ./libraries/work
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _device_synopsys_sim.setup including all device libraries
|
||||
echo "--DONOT MODIFY" > _device_synopsys_sim.setup
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "$library: ./libraries/$library" >> _device_synopsys_sim.setup
|
||||
done
|
||||
else
|
||||
echo "OTHERS=$PRECOMP_DEVICE_LIB_FILE" >> _device_synopsys_sim.setup
|
||||
fi
|
||||
#-------------------------------------------
|
||||
# write out _default_synopsys_sim.setup including all design libraries
|
||||
echo "-- DO NOT MODIFY " > _default_synopsys_sim.setup
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "$library: ./libraries/$library" >> _default_synopsys_sim.setup
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 2]
|
||||
set memory_files [list]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
memory_files=$cmd_output
|
||||
if [ $SKIP_FILE_COPY -eq 0 ]; then
|
||||
for file in $memory_files
|
||||
do
|
||||
cp -f $file ./
|
||||
done
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96_ver
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96_ver
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/synopsys/tennm_atoms_ncrypt.sv" -work tennm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
||||
fi
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# add device library elaboration and simulation properties
|
||||
ELAB_OPTIONS="$ELAB_OPTIONS $QUARTUS_INSTALL_DIR/eda/sim_lib/simsf_dpi.cpp"
|
||||
|
||||
# ----------------------------------------
|
||||
# get common system verilog package design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set design_files [dict create]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
||||
set common_design_files [dict values $design_files]
|
||||
foreach file $common_design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
common_design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 5]
|
||||
set files [list]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set files [concat $files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files $files
|
||||
foreach file $design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/vcsmx_files.tcl
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
foreach library $dpi_libraries { puts -nonewline "$library " }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
dpi_libraries=$cmd_output
|
||||
|
||||
if [ -n "$dpi_libraries" ]; then
|
||||
echo "Using DPI Library settings"
|
||||
LDFLAGS_LOCAL=""
|
||||
for library in $dpi_libraries; do
|
||||
library=$(readlink -m $library)
|
||||
FILENAME=${library##*/}
|
||||
LDFLAGS_LOCAL+=" -Wl,-rpath ${library%/*} -L ${library%/*} -l${FILENAME:3}"
|
||||
done
|
||||
export LDFLAGS="$LDFLAGS_LOCAL $LDFLAGS"
|
||||
ELAB_OPTIONS="$ELAB_OPTIONS -debug_access+r+w+nomemcbk"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
eval "$common_design_files"
|
||||
eval "$design_files"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
vcs -lca -t ps -liblist_work $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
||||
fi
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
|
||||
DEFINE std $CDS_ROOT/tools/inca/files/STD/
|
||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
|
||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
|
||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
|
||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
|
||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
DEFINE work ./libraries/work/
|
||||
DEFINE emif_io96b_hps_emif_io96b_hps_420_dyxenzq ./libraries/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/
|
||||
SOFTINCLUDE _device.cds.lib
|
||||
INCLUDE _default.cds.lib
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
|
||||
DEFINE std $CDS_ROOT/tools/inca/files/STD/
|
||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
|
||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
|
||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
|
||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
|
||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
|
||||
DEFINE WORK work
|
||||
+440
@@ -0,0 +1,440 @@
|
||||
|
||||
# (C) 2001-2026 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Intel
|
||||
# Program License Subscription Agreement, Intel MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Intel and sold by Intel
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
|
||||
# ----------------------------------------
|
||||
# xcelium - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# emif_io96b_hps_emif_io96b_hps_420_dyxenzq
|
||||
#
|
||||
# Intel recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# Xcelium Simulation Script.
|
||||
# To write a top-level shell script that compiles Intel simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "xcelium_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated files
|
||||
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
|
||||
# # into the location from which you launch the simulator, or incorporate
|
||||
# # into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/xcelium/xcelium_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# xmvlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/xcelium/xcelium_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# DEFAULT_ELAB_OPTIONS=<default elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If emif_io96b_hps_emif_io96b_hps_420_dyxenzq is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Intel IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Intel IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 26.1 110 linux 2026.04.08.10:53:29
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="emif_io96b_hps_emif_io96b_hps_420_dyxenzq.emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
|
||||
QSYS_SIMDIR="./../"
|
||||
QUARTUS_INSTALL_DIR="/opt/altera_pro/26.1/quartus/"
|
||||
QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib/"
|
||||
DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
DEFAULT_ELAB_OPTIONS=" -access +w+r+c -update -namemap_mixgen +DISABLEGENCHK -relax"
|
||||
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# check tclsh version no earlier than 8.5
|
||||
version=$(echo "puts [package vcompare [info tclversion] 8.5]; exit" | tclsh)
|
||||
if [ $version -eq -1 ]; then
|
||||
echo "Error: Minimum required tcl package version is 8.5." >&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# read .sh file to override initialized variables
|
||||
if [ -n "${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}" ] && [ -f ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} ]; then
|
||||
echo "Sourcing ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}"
|
||||
source ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE}
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error:: This file ${QSYS_SIM_SCRIPT_XCELIUM_OPTIONS_FILE} has invalid expression/s" >&2
|
||||
exit $?
|
||||
fi
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `xmsim -version` != *"xmsim(64)"* ]]; then
|
||||
SIMULATOR_TOOL_BITNESS="bit_32"
|
||||
else
|
||||
SIMULATOR_TOOL_BITNESS="bit_64"
|
||||
fi
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set SIMULATOR_TOOL_BITNESS [lindex $argv 2]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set LD_LIBRARY_PATH [dict create]
|
||||
set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
|
||||
if {[dict size $LD_LIBRARY_PATH] !=0 } {
|
||||
set LD_LIBRARY_PATH [join [dict keys $LD_LIBRARY_PATH] ":"]
|
||||
puts "LD_LIBRARY_PATH=\"$LD_LIBRARY_PATH\""
|
||||
}
|
||||
|
||||
set ELAB_OPTIONS ""
|
||||
append ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_elab_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "ELAB_OPTIONS+=\"$ELAB_OPTIONS\""
|
||||
set SIM_OPTIONS ""
|
||||
append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_sim_options $SIMULATOR_TOOL_BITNESS]
|
||||
puts "SIM_OPTIONS+=\"$SIM_OPTIONS\""
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$SIMULATOR_TOOL_BITNESS" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
eval $cmd_output
|
||||
|
||||
#-------------------------------------------
|
||||
# Decision to skip device compilation,
|
||||
# based on value of PRECOMP_DEVICE_LIB_FILE.
|
||||
# if PRECOMP_DEVICE_LIB_FILE is set, SKIP_DEV_COM will become true
|
||||
if [ ! -z "$PRECOMP_DEVICE_LIB_FILE" ] && [ -e $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
echo "Using $PRECOMP_DEVICE_LIB_FILE for device library mapping"
|
||||
SKIP_DEV_COM=1
|
||||
else
|
||||
PRECOMP_DEVICE_LIB_FILE=""
|
||||
fi
|
||||
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_libraries]]
|
||||
set design_libraries [dict keys $libraries]
|
||||
foreach file $design_libraries { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
device_libraries='lpm_ver sgate_ver altera_ver altera_mf_ver tennm_ver lpm sgate altera altera_mf altera_lnsim tennm tennm_sm_hps tennm_sm4_hssi tennm_revb_hvio tennm_revb_io96 '
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
fi
|
||||
|
||||
for library in $design_libraries
|
||||
do
|
||||
mkdir -p ./libraries/$library
|
||||
done
|
||||
mkdir -p ./libraries/work
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _device.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > _device.cds.lib
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "DEFINE $library ./libraries/$library" >> _device.cds.lib
|
||||
done
|
||||
else
|
||||
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> _device.cds.lib
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# write out device.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > ./cds_libs/device.cds.lib
|
||||
if [ -z $PRECOMP_DEVICE_LIB_FILE ]; then
|
||||
for library in $device_libraries
|
||||
do
|
||||
echo "DEFINE $library ./../libraries/$library" >> ./cds_libs/device.cds.lib
|
||||
done
|
||||
else
|
||||
echo "INCLUDE $PRECOMP_DEVICE_LIB_FILE" >> ./cds_libs/device.cds.lib
|
||||
fi
|
||||
|
||||
#-------------------------------------------
|
||||
# write out _default.cds.lib including all design libraries
|
||||
echo "# DO NOT MODIFY " > _default.cds.lib
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "DEFINE $library ./libraries/$library" >> _default.cds.lib
|
||||
done
|
||||
|
||||
#-------------------------------------------
|
||||
# create cds_libs for each design library
|
||||
for library in $design_libraries
|
||||
do
|
||||
echo "INCLUDE simulator.cds.lib" > cds_libs/$library.cds.lib
|
||||
echo "INCLUDE device.cds.lib" >> cds_libs/$library.cds.lib
|
||||
if [[ $design_libraries =~ "altera_common_sv_packages" ]] && [[ $library != "altera_common_sv_packages" ]]; then
|
||||
echo "DEFINE altera_common_sv_packages ./../libraries/altera_common_sv_packages/" >> cds_libs/$library.cds.lib
|
||||
fi
|
||||
echo "DEFINE $library ./../libraries/$library" >> cds_libs/$library.cds.lib
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 2]
|
||||
set memory_files [list]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_memory_files "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
foreach file $memory_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
memory_files=$cmd_output
|
||||
if [ $SKIP_FILE_COPY -eq 0 ]; then
|
||||
for file in $memory_files
|
||||
do
|
||||
cp -f $file ./
|
||||
done
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.v" -work lpm_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.v" -work sgate_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.v" -work altera_ver
|
||||
xmvlog -zlib 1 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.v" -work altera_mf_ver
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.sv" -work tennm_ver
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/fmica_atoms_ncrypt.sv" -work tennm_ver
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220pack.vhd" -work lpm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/220model.vhd" -work lpm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate_pack.vhd" -work sgate
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/sgate.vhd" -work sgate
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_syn_attributes.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_standard_functions.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/alt_dspbuilder_package.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_europa_support_lib.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives_components.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_primitives.vhd" -work altera
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf_components.vhd" -work altera_mf
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_mf.vhd" -work altera_mf
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim.sv" -work altera_lnsim
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
xmvlog -zlib 1 -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/cadence/tennm_atoms_ncrypt.sv" -work tennm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_atoms.vhd" -work tennm
|
||||
xmvhdl -v93 -zlib 1 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_SIM_LIB_DIR/tennm_components.vhd" -work tennm
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps.sv" -work tennm_sm_hps
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm_hps_ncrypt.sv" -work tennm_sm_hps
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi.sv" -work tennm_sm4_hssi
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_sm4_hssi_ncrypt.sv" -work tennm_sm4_hssi
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio.sv" -work tennm_revb_hvio
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_hvio_ncrypt.sv" -work tennm_revb_hvio
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96.sv" -work tennm_revb_io96
|
||||
xmvlog -zlib 1 -sv -compcnfg $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$DEVICES_SIM_LIB_DIR/tennm_revb_io96_ncrypt.sv" -work tennm_revb_io96
|
||||
fi
|
||||
gcc -fPIC -g -shared -o libdpi.so -I/`ncroot`/tools/inca/include "$QUARTUS_SIM_LIB_DIR/simsf_dpi.cpp"
|
||||
|
||||
# ----------------------------------------
|
||||
# add device library elaboration and simulation properties
|
||||
|
||||
# ----------------------------------------
|
||||
# get common system verilog package design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set design_files [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR"]]
|
||||
set common_design_files [dict values $design_files]
|
||||
foreach file $common_design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
common_design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get design files
|
||||
TCLSCRIPT='
|
||||
set USER_DEFINED_COMPILE_OPTIONS [lindex $argv 1]
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS [lindex $argv 2]
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS [lindex $argv 3]
|
||||
set QSYS_SIMDIR [lindex $argv 4]
|
||||
set QUARTUS_INSTALL_DIR [lindex $argv 5]
|
||||
set files [list]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set files [concat $files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR"]]
|
||||
set design_files $files
|
||||
foreach file $design_files { puts "$file" }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$USER_DEFINED_COMPILE_OPTIONS" "$USER_DEFINED_VERILOG_COMPILE_OPTIONS" "$USER_DEFINED_VHDL_COMPILE_OPTIONS" "$QSYS_SIMDIR" "$QUARTUS_INSTALL_DIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
design_files=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# get DPI libraries
|
||||
TCLSCRIPT='
|
||||
set QSYS_SIMDIR [lindex $argv 1]
|
||||
set libraries [dict create]
|
||||
source $QSYS_SIMDIR/common/xcelium_files.tcl
|
||||
set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq::get_dpi_libraries "$QSYS_SIMDIR"]]
|
||||
set dpi_libraries [dict values $libraries]
|
||||
foreach library $dpi_libraries { puts -nonewline "$library " }
|
||||
exit 0
|
||||
'
|
||||
cmd_output=$(
|
||||
tclsh -args "$QSYS_SIMDIR" << SCRIPT
|
||||
$TCLSCRIPT
|
||||
SCRIPT
|
||||
)
|
||||
|
||||
dpi_libraries=$cmd_output
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
eval "$common_design_files"
|
||||
eval "$design_files"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
xmelab $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $DEFAULT_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
if [ -n "$dpi_libraries" ]; then
|
||||
echo "Using DPI Library settings"
|
||||
FILES=""
|
||||
for library in $dpi_libraries; do
|
||||
FILES+="-sv_lib $library"
|
||||
done
|
||||
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME $FILES
|
||||
else
|
||||
eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
fi
|
||||
+366
@@ -0,0 +1,366 @@
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// emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_alt_mem_if_jtag_master_191_2xbfrbi.v
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// This file was auto-generated from alt_mem_if_jtag_master_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 26.1 110
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`timescale 1 ps / 1 ps
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module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_alt_mem_if_jtag_master_191_2xbfrbi #(
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parameter USE_PLI = 0,
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parameter PLI_PORT = 50000,
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parameter FIFO_DEPTHS = 2
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) (
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input wire clk_clk, // clk.clk, Clock Input
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input wire clk_reset_reset, // clk_reset.reset, Reset Input
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output wire master_reset_reset, // master_reset.reset, Reset Output
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output wire [31:0] master_address, // master.address, Address output of Avalon Memory Mapped Host
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input wire [31:0] master_readdata, // .readdata, Read Data input to Avalon Memory Mapped Host
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output wire master_read, // .read, Read command from Avalon Memory Mapped Host
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output wire master_write, // .write, Write command from Avalon Memory Mapped Host
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output wire [31:0] master_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
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input wire master_waitrequest, // .waitrequest, Wait request from Avalon Memory Mapped Agent, indicates agent is not ready
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input wire master_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
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output wire [3:0] master_byteenable // .byteenable, Indicates valid write data/read data location
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);
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wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
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wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
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wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
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wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
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wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
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wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
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wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
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wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
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wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
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wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
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wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
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wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
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wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
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wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
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wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
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wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
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wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
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wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
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wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
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wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
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wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
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wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
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wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
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wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
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wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
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wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
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wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
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wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
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wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
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wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
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wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
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wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
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wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
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wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
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generate
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// If any of the display statements (or deliberately broken
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// instantiations) within this generate block triggers then this module
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// has been instantiated this module with a set of parameters different
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// from those it was generated for. This will usually result in a
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// non-functioning system.
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if (USE_PLI != 0)
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begin
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// synthesis translate_off
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$stop;
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end
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// synthesis translate_on
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instantiated_with_wrong_parameters_error_see_comment_above
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use_pli_check ( .error(1'b1) );
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end
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if (PLI_PORT != 50000)
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begin
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// synthesis translate_off
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$stop;
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end
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// synthesis translate_on
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instantiated_with_wrong_parameters_error_see_comment_above
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pli_port_check ( .error(1'b1) );
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end
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if (FIFO_DEPTHS != 2)
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begin
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// synthesis translate_off
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$stop;
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end
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// synthesis translate_on
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instantiated_with_wrong_parameters_error_see_comment_above
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fifo_depths_check ( .error(1'b1) );
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end
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endgenerate
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altera_avalon_st_jtag_interface #(
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.PURPOSE (1),
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.UPSTREAM_FIFO_SIZE (0),
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.DOWNSTREAM_FIFO_SIZE (64),
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.MGMT_CHANNEL_WIDTH (-1),
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.EXPORT_JTAG (0),
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.USE_PLI (0),
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.PLI_PORT (50000)
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) jtag_phy_embedded_in_jtag_master (
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.clk (clk_clk), // input, width = 1, clock.clk
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.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clock_reset.reset_n
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.source_data (jtag_phy_embedded_in_jtag_master_src_data), // output, width = 8, src.data
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.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // output, width = 1, .valid
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.sink_data (p2b_out_bytes_stream_data), // input, width = 8, sink.data
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.sink_valid (p2b_out_bytes_stream_valid), // input, width = 1, .valid
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.sink_ready (p2b_out_bytes_stream_ready), // output, width = 1, .ready
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.resetrequest (master_reset_reset), // output, width = 1, resetrequest.reset
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.source_ready (1'b1), // (terminated),
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.mgmt_valid (), // (terminated),
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.mgmt_channel (), // (terminated),
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.mgmt_data (), // (terminated),
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.jtag_tck (1'b0), // (terminated),
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.jtag_tms (1'b0), // (terminated),
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.jtag_tdi (1'b0), // (terminated),
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.jtag_tdo (), // (terminated),
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.jtag_ena (1'b0), // (terminated),
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.jtag_usr1 (1'b0), // (terminated),
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.jtag_clr (1'b0), // (terminated),
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.jtag_clrn (1'b0), // (terminated),
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.jtag_state_tlr (1'b0), // (terminated),
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.jtag_state_rti (1'b0), // (terminated),
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.jtag_state_sdrs (1'b0), // (terminated),
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.jtag_state_cdr (1'b0), // (terminated),
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.jtag_state_sdr (1'b0), // (terminated),
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.jtag_state_e1dr (1'b0), // (terminated),
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.jtag_state_pdr (1'b0), // (terminated),
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.jtag_state_e2dr (1'b0), // (terminated),
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.jtag_state_udr (1'b0), // (terminated),
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.jtag_state_sirs (1'b0), // (terminated),
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.jtag_state_cir (1'b0), // (terminated),
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.jtag_state_sir (1'b0), // (terminated),
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.jtag_state_e1ir (1'b0), // (terminated),
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.jtag_state_pir (1'b0), // (terminated),
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.jtag_state_e2ir (1'b0), // (terminated),
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.jtag_state_uir (1'b0), // (terminated),
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.jtag_ir_in (3'b000), // (terminated),
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.jtag_irq (), // (terminated),
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.jtag_ir_out () // (terminated),
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);
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emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_timing_adapter_1950_bbjt6kq #(
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.SYNC_RESET (0),
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.FIFO_MEM_TYPE (0)
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) timing_adt (
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.clk (clk_clk), // input, width = 1, clk.clk
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.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
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.in_data (jtag_phy_embedded_in_jtag_master_src_data), // input, width = 8, in.data
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.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // input, width = 1, .valid
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.out_data (timing_adt_out_data), // output, width = 8, out.data
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.out_valid (timing_adt_out_valid), // output, width = 1, .valid
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.out_ready (timing_adt_out_ready) // input, width = 1, .ready
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);
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emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_altera_avalon_sc_fifo_1932_onpcouq #(
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.SYMBOLS_PER_BEAT (1),
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.BITS_PER_SYMBOL (8),
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.FIFO_DEPTH (64),
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.CHANNEL_WIDTH (0),
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.ERROR_WIDTH (0),
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.USE_PACKETS (0),
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.USE_FILL_LEVEL (0),
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.EMPTY_LATENCY (3),
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.USE_MEMORY_BLOCKS (1),
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.USE_STORE_FORWARD (0),
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.USE_ALMOST_FULL_IF (0),
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.USE_ALMOST_EMPTY_IF (0),
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.EMPTY_WIDTH (1),
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.MEM_TYPE ("M20K"),
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.SYNC_RESET (0)
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) fifo (
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.clk (clk_clk), // input, width = 1, clk.clk
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.reset (rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset
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.in_data (timing_adt_out_data), // input, width = 8, in.data
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.in_valid (timing_adt_out_valid), // input, width = 1, .valid
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.in_ready (timing_adt_out_ready), // output, width = 1, .ready
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.out_data (fifo_out_data), // output, width = 8, out.data
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.out_valid (fifo_out_valid), // output, width = 1, .valid
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.out_ready (fifo_out_ready), // input, width = 1, .ready
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.csr_address (2'b00), // (terminated),
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.csr_read (1'b0), // (terminated),
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.csr_write (1'b0), // (terminated),
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.csr_readdata (), // (terminated),
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.csr_writedata (32'b00000000000000000000000000000000), // (terminated),
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.almost_full_data (), // (terminated),
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.almost_empty_data (), // (terminated),
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.in_startofpacket (1'b0), // (terminated),
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.in_endofpacket (1'b0), // (terminated),
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.out_startofpacket (), // (terminated),
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.out_endofpacket (), // (terminated),
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.in_empty (1'b0), // (terminated),
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||||
.out_empty (), // (terminated),
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.in_error (1'b0), // (terminated),
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.out_error (), // (terminated),
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.in_channel (1'b0), // (terminated),
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.out_channel () // (terminated),
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);
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altera_avalon_st_bytes_to_packets #(
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.CHANNEL_WIDTH (8),
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.ENCODING (0)
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) b2p (
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.clk (clk_clk), // input, width = 1, clk.clk
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.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
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.out_channel (b2p_out_packets_stream_channel), // output, width = 8, out_packets_stream.channel
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.out_ready (b2p_out_packets_stream_ready), // input, width = 1, .ready
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.out_valid (b2p_out_packets_stream_valid), // output, width = 1, .valid
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.out_data (b2p_out_packets_stream_data), // output, width = 8, .data
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.out_startofpacket (b2p_out_packets_stream_startofpacket), // output, width = 1, .startofpacket
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.out_endofpacket (b2p_out_packets_stream_endofpacket), // output, width = 1, .endofpacket
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.in_ready (fifo_out_ready), // output, width = 1, in_bytes_stream.ready
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.in_valid (fifo_out_valid), // input, width = 1, .valid
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||||
.in_data (fifo_out_data) // input, width = 8, .data
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||||
);
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||||
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||||
altera_avalon_st_packets_to_bytes #(
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.CHANNEL_WIDTH (8),
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.ENCODING (0)
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) p2b (
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||||
.clk (clk_clk), // input, width = 1, clk.clk
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||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
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||||
.in_ready (p2b_adapter_out_ready), // output, width = 1, in_packets_stream.ready
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||||
.in_valid (p2b_adapter_out_valid), // input, width = 1, .valid
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||||
.in_data (p2b_adapter_out_data), // input, width = 8, .data
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||||
.in_channel (p2b_adapter_out_channel), // input, width = 8, .channel
|
||||
.in_startofpacket (p2b_adapter_out_startofpacket), // input, width = 1, .startofpacket
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||||
.in_endofpacket (p2b_adapter_out_endofpacket), // input, width = 1, .endofpacket
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||||
.out_ready (p2b_out_bytes_stream_ready), // input, width = 1, out_bytes_stream.ready
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||||
.out_valid (p2b_out_bytes_stream_valid), // output, width = 1, .valid
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||||
.out_data (p2b_out_bytes_stream_data) // output, width = 8, .data
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||||
);
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||||
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||||
altera_avalon_packets_to_master #(
|
||||
.FAST_VER (0),
|
||||
.FIFO_DEPTHS (2),
|
||||
.FIFO_WIDTHU (1)
|
||||
) transacto (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
|
||||
.out_ready (transacto_out_stream_ready), // input, width = 1, out_stream.ready
|
||||
.out_valid (transacto_out_stream_valid), // output, width = 1, .valid
|
||||
.out_data (transacto_out_stream_data), // output, width = 8, .data
|
||||
.out_startofpacket (transacto_out_stream_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (transacto_out_stream_endofpacket), // output, width = 1, .endofpacket
|
||||
.in_ready (b2p_adapter_out_ready), // output, width = 1, in_stream.ready
|
||||
.in_valid (b2p_adapter_out_valid), // input, width = 1, .valid
|
||||
.in_data (b2p_adapter_out_data), // input, width = 8, .data
|
||||
.in_startofpacket (b2p_adapter_out_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (b2p_adapter_out_endofpacket), // input, width = 1, .endofpacket
|
||||
.address (master_address), // output, width = 32, avalon_master.address
|
||||
.readdata (master_readdata), // input, width = 32, .readdata
|
||||
.read (master_read), // output, width = 1, .read
|
||||
.write (master_write), // output, width = 1, .write
|
||||
.writedata (master_writedata), // output, width = 32, .writedata
|
||||
.waitrequest (master_waitrequest), // input, width = 1, .waitrequest
|
||||
.readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
|
||||
.byteenable (master_byteenable) // output, width = 4, .byteenable
|
||||
);
|
||||
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_rd56ufy b2p_adapter (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (b2p_out_packets_stream_data), // input, width = 8, in.data
|
||||
.in_valid (b2p_out_packets_stream_valid), // input, width = 1, .valid
|
||||
.in_ready (b2p_out_packets_stream_ready), // output, width = 1, .ready
|
||||
.in_startofpacket (b2p_out_packets_stream_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (b2p_out_packets_stream_endofpacket), // input, width = 1, .endofpacket
|
||||
.in_channel (b2p_out_packets_stream_channel), // input, width = 8, .channel
|
||||
.out_data (b2p_adapter_out_data), // output, width = 8, out.data
|
||||
.out_valid (b2p_adapter_out_valid), // output, width = 1, .valid
|
||||
.out_ready (b2p_adapter_out_ready), // input, width = 1, .ready
|
||||
.out_startofpacket (b2p_adapter_out_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (b2p_adapter_out_endofpacket) // output, width = 1, .endofpacket
|
||||
);
|
||||
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_5vp3d5a p2b_adapter (
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
|
||||
.in_data (transacto_out_stream_data), // input, width = 8, in.data
|
||||
.in_valid (transacto_out_stream_valid), // input, width = 1, .valid
|
||||
.in_ready (transacto_out_stream_ready), // output, width = 1, .ready
|
||||
.in_startofpacket (transacto_out_stream_startofpacket), // input, width = 1, .startofpacket
|
||||
.in_endofpacket (transacto_out_stream_endofpacket), // input, width = 1, .endofpacket
|
||||
.out_data (p2b_adapter_out_data), // output, width = 8, out.data
|
||||
.out_valid (p2b_adapter_out_valid), // output, width = 1, .valid
|
||||
.out_ready (p2b_adapter_out_ready), // input, width = 1, .ready
|
||||
.out_startofpacket (p2b_adapter_out_startofpacket), // output, width = 1, .startofpacket
|
||||
.out_endofpacket (p2b_adapter_out_endofpacket), // output, width = 1, .endofpacket
|
||||
.out_channel (p2b_adapter_out_channel) // output, width = 8, .channel
|
||||
);
|
||||
|
||||
altera_reset_controller #(
|
||||
.NUM_RESET_INPUTS (1),
|
||||
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
||||
.SYNC_DEPTH (2),
|
||||
.RESET_REQUEST_PRESENT (0),
|
||||
.RESET_REQ_WAIT_TIME (1),
|
||||
.MIN_RST_ASSERTION_TIME (3),
|
||||
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||||
.USE_RESET_REQUEST_IN0 (0),
|
||||
.USE_RESET_REQUEST_IN1 (0),
|
||||
.USE_RESET_REQUEST_IN2 (0),
|
||||
.USE_RESET_REQUEST_IN3 (0),
|
||||
.USE_RESET_REQUEST_IN4 (0),
|
||||
.USE_RESET_REQUEST_IN5 (0),
|
||||
.USE_RESET_REQUEST_IN6 (0),
|
||||
.USE_RESET_REQUEST_IN7 (0),
|
||||
.USE_RESET_REQUEST_IN8 (0),
|
||||
.USE_RESET_REQUEST_IN9 (0),
|
||||
.USE_RESET_REQUEST_IN10 (0),
|
||||
.USE_RESET_REQUEST_IN11 (0),
|
||||
.USE_RESET_REQUEST_IN12 (0),
|
||||
.USE_RESET_REQUEST_IN13 (0),
|
||||
.USE_RESET_REQUEST_IN14 (0),
|
||||
.USE_RESET_REQUEST_IN15 (0),
|
||||
.ADAPT_RESET_REQUEST (0)
|
||||
) rst_controller (
|
||||
.reset_in0 (clk_reset_reset), // input, width = 1, reset_in0.reset
|
||||
.clk (clk_clk), // input, width = 1, clk.clk
|
||||
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
|
||||
.reset_req (), // (terminated),
|
||||
.reset_req_in0 (1'b0), // (terminated),
|
||||
.reset_in1 (1'b0), // (terminated),
|
||||
.reset_req_in1 (1'b0), // (terminated),
|
||||
.reset_in2 (1'b0), // (terminated),
|
||||
.reset_req_in2 (1'b0), // (terminated),
|
||||
.reset_in3 (1'b0), // (terminated),
|
||||
.reset_req_in3 (1'b0), // (terminated),
|
||||
.reset_in4 (1'b0), // (terminated),
|
||||
.reset_req_in4 (1'b0), // (terminated),
|
||||
.reset_in5 (1'b0), // (terminated),
|
||||
.reset_req_in5 (1'b0), // (terminated),
|
||||
.reset_in6 (1'b0), // (terminated),
|
||||
.reset_req_in6 (1'b0), // (terminated),
|
||||
.reset_in7 (1'b0), // (terminated),
|
||||
.reset_req_in7 (1'b0), // (terminated),
|
||||
.reset_in8 (1'b0), // (terminated),
|
||||
.reset_req_in8 (1'b0), // (terminated),
|
||||
.reset_in9 (1'b0), // (terminated),
|
||||
.reset_req_in9 (1'b0), // (terminated),
|
||||
.reset_in10 (1'b0), // (terminated),
|
||||
.reset_req_in10 (1'b0), // (terminated),
|
||||
.reset_in11 (1'b0), // (terminated),
|
||||
.reset_req_in11 (1'b0), // (terminated),
|
||||
.reset_in12 (1'b0), // (terminated),
|
||||
.reset_req_in12 (1'b0), // (terminated),
|
||||
.reset_in13 (1'b0), // (terminated),
|
||||
.reset_req_in13 (1'b0), // (terminated),
|
||||
.reset_in14 (1'b0), // (terminated),
|
||||
.reset_req_in14 (1'b0), // (terminated),
|
||||
.reset_in15 (1'b0), // (terminated),
|
||||
.reset_req_in15 (1'b0) // (terminated),
|
||||
);
|
||||
|
||||
endmodule
|
||||
+1244
File diff suppressed because it is too large
Load Diff
+1392
File diff suppressed because it is too large
Load Diff
+213
@@ -0,0 +1,213 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Bytes to Packet
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_bytes_to_packets
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0 )
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST out with packets
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data,
|
||||
output reg [CHANNEL_WIDTH-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc, received_channel, received_varchannel;
|
||||
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
|
||||
|
||||
// data out mux.
|
||||
// we need it twice (data & channel out), so use a wire here
|
||||
wire [7:0] data_out;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign sop_char = (in_data == 8'h7a);
|
||||
assign eop_char = (in_data == 8'h7b);
|
||||
assign channel_char = (in_data == 8'h7c);
|
||||
assign escape_char = (in_data == 8'h7d);
|
||||
|
||||
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
//we choose not to pipeline here. We can process special characters when
|
||||
//in_ready, but in a chain of microcores, backpressure path is usually
|
||||
//time critical, so we keep it simple here.
|
||||
in_ready = out_ready;
|
||||
|
||||
//out_valid when in_valid, except when we are processing the special
|
||||
//characters. However, if we are in escape received mode, then we are
|
||||
//valid
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
|
||||
end else begin
|
||||
assign varchannelesc_char = in_data[7];
|
||||
// Synchorous block -- reset and registers
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
received_channel <= 0;
|
||||
received_varchannel <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
// we take data when in_valid and in_ready
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
//if we got esc char, after next byte is consumed, quit esc mode
|
||||
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
if (channel_char & ENCODING ) received_varchannel <= 1;
|
||||
if (channel_char & ~ENCODING) received_channel <= 1;
|
||||
end
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
|
||||
received_channel <= 0;
|
||||
end
|
||||
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
received_varchannel <= 0;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Combinational block for in_ready and out_valid
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (received_esc) begin
|
||||
if (received_channel | received_varchannel) out_valid = 0;
|
||||
end else begin
|
||||
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
|
||||
end
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
// Channel block
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
always @(posedge clk) begin
|
||||
out_channel <= 'h0;
|
||||
end
|
||||
|
||||
end else if (CHANNEL_WIDTH < 8) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out only the required bits
|
||||
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
out_channel <= data_out;
|
||||
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
// Shifting out the lower 7 bits
|
||||
out_channel <= out_channel <<7;
|
||||
out_channel[6:0] <= data_out[6:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3ToCi97F+O4Jtd7lyb3HX6P4erEvg2ALdvMtyo/GHuQ/3I7pLrfwffqBLzWXXFs+6LextEIKaErTIQtRI5NPblwu4T4zWVtUAvzj5xOcu8gxOUxITJg1JZu+hgblTes2OH1rZVOYEc0eF6RV6M6mu1E0UjegEjjIH8WWlbRMFzdxz1MD+/1DOZKc2X+0imGI5dm+g8REigzqPK2bFQ27ymsU332zAZHeycYzNJZHNdp4UR/78MkHalkV8QT8ArFIuR8WyWGAcupKZKTKZDQDkHR68+dbi95JnS5K2TO0ztqaqbDaf+2QVKSQJPXXVst31OaRxADe5QDF+gWz6G2CGvrh9brNfZvLSIZIq0RDVcRDDWS9wykYAHrdn7oaVfa7Ocv3ZDY7SQC/MrrrmS7+EAwIxzdtdsmo69WDKjrhL7ao98J9L0HeZ35yJn4tmTjEgevmu0Pd++DbtOec2XvEvqoiObWXn1Ez0VgwNU0wYDLKlVz7bBTb3mS9dHgjyfaienlH7CJVn1dLF4TzwJbL1D0bmQWRhgjGJNwgPEO9iqaXZyUEDXTP6gVXMMdxaDz0GZsdz300XMv5zqF+qo557ZSiJ0QxsOcSxuNw/WvzP2stoPcFXwc0saeVFmka2V3RXgBKax4pG6q0+/KW6rpO8xAQ8EsXo8FdGHsW/FygMpuPqtz7/TFsXjrm9eJTLeTjS+bxhFsupTQd9HMcfTpXgiOk5Z4hPDwhwwe5/h7U5W/swzbB8EgT5oF/i14xZVWes6eqE3Jy3EZgj3vnUJyYO8OG7N4DNlBHxIYTfcCyegMVe5Q5+ZuX6J3X1CbMzwmWcu3T6JxSiezjpbS9gOOZ1l4i9903qMP1opGRzv8ngX55HNkAwpD3G7mshzVBGRG9BlUlq4GPpHwNHMVzXY1m12hDrSsAv9FQUOLqlKkgwsPXJYdp4oGejAaw/C0MZuVGZl8CKozUoaXUCLf3ejkN55fpY5hwHQIQEp/7otAd68JvUDbawCY8SJwht0NDxWww"
|
||||
`endif
|
||||
+263
@@ -0,0 +1,263 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Packets to Bytes Component
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_packets_to_bytes
|
||||
//if ENCODING ==0, CHANNEL_WIDTH must be 8
|
||||
//else CHANNEL_WIDTH can be from 0 to 127
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0)
|
||||
(
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in with packets
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
input [CHANNEL_WIDTH-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
|
||||
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
|
||||
reg sent_esc, sent_sop, sent_eop;
|
||||
reg sent_channel_char, channel_escaped, sent_channel;
|
||||
reg [CHANNEL_WIDTH-1:0] stored_channel;
|
||||
reg [4:0] channel_count;
|
||||
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
|
||||
reg channel_needs_esc;
|
||||
|
||||
|
||||
|
||||
wire need_sop, need_eop, need_esc, need_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// SYNTHESIS ONLY
|
||||
// synthesis read_comments_as_HDL on
|
||||
// assign need_esc = (in_data == 8'h7a | in_data == 8'h7b | in_data == 8'h7c | in_data == 8'h7d );
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
// SIMULATION ONYLU
|
||||
// synthesis translate_off
|
||||
assign need_esc = (in_data === 8'h7a | in_data === 8'h7b | in_data === 8'h7c | in_data === 8'h7d );
|
||||
// synthesis translate_on
|
||||
|
||||
|
||||
assign need_eop = (in_endofpacket);
|
||||
assign need_sop = (in_startofpacket);
|
||||
|
||||
|
||||
generate
|
||||
if( CHANNEL_WIDTH > 0) begin
|
||||
wire channel_changed;
|
||||
assign channel_changed = (in_channel != stored_channel);
|
||||
assign need_channel = (need_sop | channel_changed);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
channel_count <= 0;
|
||||
channel_needs_esc <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
channel_count <= CHN_COUNT[4:0];
|
||||
stored_varchannel <= in_channel;
|
||||
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
|
||||
channel_needs_esc <= (in_channel == 8'h7a |
|
||||
in_channel == 8'h7b |
|
||||
in_channel == 8'h7c |
|
||||
in_channel == 8'h7d );
|
||||
end
|
||||
end else if (channel_needs_esc & ~channel_escaped) begin
|
||||
out_data <= 8'h7d;
|
||||
channel_escaped <= 1;
|
||||
end else if (~sent_channel) begin
|
||||
if (ENCODING) begin
|
||||
// Sending out MSB=1, while not last 7 bits of Channel
|
||||
if (channel_count > 0) begin
|
||||
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
stored_varchannel <= stored_varchannel<<7;
|
||||
|
||||
channel_count <= channel_count - 1'b1;
|
||||
// check whether the last 7 bits need escape or not
|
||||
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
|
||||
channel_needs_esc <=
|
||||
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
|
||||
end
|
||||
end else begin
|
||||
// Sending out MSB=0, last 7 bits of Channel
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else begin
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= in_channel ^ 8'h20;
|
||||
end else out_data <= in_channel;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//channel related signals
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
//extra bit in stored_channel to force reset
|
||||
stored_channel <= {CHANNEL_WIDTH{1'b1}};
|
||||
end else begin
|
||||
//update stored_channel only when it is sent out
|
||||
if (sent_channel) stored_channel <= in_channel;
|
||||
end
|
||||
end
|
||||
always @* begin
|
||||
|
||||
// in_ready. Low when:
|
||||
// back pressured, or when
|
||||
// we are outputting a control character, which means that one of
|
||||
// {escape_char, start of packet, end of packet, channel}
|
||||
// needs to be, but has not yet, been handled.
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
assign need_channel = (need_sop);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
sent_channel <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
end else if (~sent_channel) begin
|
||||
out_data <= 'h0;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3ToCi97F+O4Jtd7lyb3HX6P4erEvg2ALdvMtyo/GHuQ/3I7pLrfwffqBLzWXXFs+6LextEIKaErTIQtRI5NPblwu4T4zWVtUAvzj5xOcu8gxOUxITJg1JZu+hgblTes2OH1rZVOYEc0eF6RV6M6mu1E0UjegEjjIH8WWlbRMFzdxz1MD+/1DOZKc2X+0imGI5dm+g8REigzqPK2bFQ27ymsU332zAZHeycYzNJZHNdp8+XrK3SsFR2TXk3FLIOUmw91xaAQa2pPF9I9+12OyjVG2j7UrmRpn+ju33pFdR5i8HjvX3QFyiR/4QzYCnXKXFTf/EbuhPYhm91NKEuGilm6Z9iXts0KIJ1aq4ua4i774oqTXgAIjXANyhyzGk5Ur3+smdc59bQ0Sc3RmPJ3T25tAVZoj11NQ3ZainP3Z5Y7iEIyrhuW0ZfcLAL4zUAr80q4aOvWun1iGrpTpWG9lw8gUoOsMcubxZPKnljcOAvngP0/HEe2NJuMfCuN1VXnnFVqM/f8miDEnsYbHQr1dAtF6nPFLnmjCz9PJlSLsknIn9XSlODFJZj523804/PT2LNZCWUVTP1SxC+eHsFXSKDwlX+6sBFC+fE9G29UYt6reIAw3Gd26uNnR/wmEv+CdXJSAaGORAYgT0/oqeojJaI5DdLsh769bfFLdhvKBf1UiMjagREV6OZHZU9j63BYPdZbrTBe8koPrfUD5PzFH26uU7fDSOD/wUOL4lZ1OM8aD6TDbCkDSEypvgByUHouVg4XkHfQD5BPepTp1QaQGEuLa83qx00cT62xUbb/sqh4Pbs5usdNejVBdKC9pIReQ8WCsSCpDLIkDTdeo9Cln0v2Kp0uYmoBqyK2hTP0gmjbSD6mm9c6Q2VCWOQ46h6HRSfc/aEoTLDDY0nDHlXssgeOKyKD4syMekhKo9f8bituh8dSnrpsvwSb4febBzcsonH3RHwGzym2vmfGfZm1kqG58y7aICrVpZOxfzI2/VYABROWLAtk2Jlthow6OtITe"
|
||||
`endif
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_clock_crosser(
|
||||
in_clk,
|
||||
in_reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_clk,
|
||||
out_reset,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter FORWARD_SYNC_DEPTH = 2;
|
||||
parameter BACKWARD_SYNC_DEPTH = 2;
|
||||
parameter USE_OUTPUT_PIPELINE = 1;
|
||||
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input in_clk;
|
||||
input in_reset;
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_clk;
|
||||
input out_reset;
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
// Data is guaranteed valid by control signal clock crossing. Cut data
|
||||
// buffer false path.
|
||||
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
|
||||
(* altera_attribute = {"-name DESIGN_ASSISTANT_EXCLUDE \"CDC-50001,CDC-50006\""} *) reg [DATA_WIDTH-1:0] out_data_buffer;
|
||||
|
||||
reg in_data_toggle;
|
||||
wire in_data_toggle_returned;
|
||||
wire out_data_toggle;
|
||||
reg out_data_toggle_flopped, out_data_toggle_1, out_data_toggle_flopped_n;
|
||||
|
||||
wire take_in_data;
|
||||
wire out_data_taken;
|
||||
|
||||
wire out_valid_internal;
|
||||
wire out_ready_internal;
|
||||
wire reset_merged;
|
||||
wire out_reset_merged;
|
||||
wire in_reset_merged;
|
||||
|
||||
assign in_ready = (in_data_toggle_returned ^ in_data_toggle);
|
||||
assign take_in_data = in_valid & in_ready;
|
||||
assign out_valid_internal = out_data_toggle_1 ^ out_data_toggle_flopped;
|
||||
assign out_data_taken = out_ready_internal & out_valid_internal;
|
||||
|
||||
assign reset_merged = in_reset | out_reset;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_in_rst
|
||||
(
|
||||
.clk (in_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (in_reset_merged)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_out_rst
|
||||
(
|
||||
.clk (out_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (out_reset_merged)
|
||||
);
|
||||
|
||||
always @(posedge in_clk or posedge in_reset_merged) begin
|
||||
if (in_reset_merged) begin
|
||||
in_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
in_data_toggle <= 1'b0;
|
||||
end else begin
|
||||
if (take_in_data) begin
|
||||
in_data_toggle <= ~in_data_toggle;
|
||||
in_data_buffer <= in_data;
|
||||
end
|
||||
end //in_reset
|
||||
end //in_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_1 <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_1 <= out_data_toggle;
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped <= 1'b0;
|
||||
out_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
end else begin
|
||||
out_data_buffer <= in_data_buffer;
|
||||
if (out_data_taken) begin
|
||||
out_data_toggle_flopped <= out_data_toggle_1;
|
||||
end
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped_n <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_flopped_n <= ~out_data_toggle_flopped;
|
||||
end //end if
|
||||
end //out_clk always block
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
|
||||
.clk(out_clk),
|
||||
.reset_n(~out_reset_merged),
|
||||
.din(in_data_toggle),
|
||||
.dout(out_data_toggle)
|
||||
);
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
|
||||
.clk(in_clk),
|
||||
.reset_n(~in_reset_merged),
|
||||
.din(out_data_toggle_flopped_n),
|
||||
.dout(in_data_toggle_returned)
|
||||
);
|
||||
|
||||
|
||||
generate if (USE_OUTPUT_PIPELINE == 1) begin
|
||||
|
||||
altera_avalon_st_pipeline_base
|
||||
#(
|
||||
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
|
||||
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
|
||||
) output_stage (
|
||||
.clk(out_clk),
|
||||
.reset(out_reset_merged),
|
||||
.in_ready(out_ready_internal),
|
||||
.in_valid(out_valid_internal),
|
||||
.in_data(out_data_buffer),
|
||||
.out_ready(out_ready),
|
||||
.out_valid(out_valid),
|
||||
.out_data(out_data)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign out_valid = out_valid_internal;
|
||||
assign out_ready_internal = out_ready;
|
||||
assign out_data = out_data_buffer;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kLaZ1eFbVnzLHFC3Iy8C952zU9KJLT86rKkmt6MuQRY9VO2r7wzhfXVuNaV6/LGJ22nFWPP1Zlp8tX/FsFICDuTFBgn16uT/eLZl7yEPcOC57c1nPIQtrXm/twebJnc+420/b7beqdRjmppQV89jcr4IutIRg0q/UzyCC4/2fY5Vuv4y2RLPqG3uLPwFsqCGQQ6W2iLHjEudISQfpD6UFZwQM3AK0EzVxzO2mWaSdjScZLEwdTYkTvzmmmqgK+TppgH8xTxu9R5AwAToenaFVO1UaJ0UesZAYuLz4Ahtj/NeR6JnsD937RDOcuA62eNx+kNN/DMnDdPeLnBRdu8+7skTxOsOQNemerCiMmE6Ih9psV6MIJNze8KR3H/TkE0Z6Xx7ZWYwao+kgAd36vATAbQYoEbfBUQZ5WpWtOgrk+SqJeNG7vIyc6DZf0HiT9CijPfhXQ/uP1Zcm8+Fy4zQgMFFXQJ+0z1dZpHdx0uQGWb2MVH1ip8rfstVLmnIExXhwxtGnMINCGOCHKHQhSmJFCCcp781UT0l2SFb2k8JnGfjBeV3qEc+YdyQlCecvpIvwm7kFOZVcuAPEMLCj9iNGZ6zF3eAtE3BwutrR3T8syz+uo4KETCahmI3C0VORjpH/ycGC9BPN4dzvSLQbbmWPa5EFqOk3o8zmzsxSS46ez0RkoPKBnL5RjvwZS9Nj4uWl10xn0GfUSYfryakKZSUfz2FSwg5R7XHIhLtozCCbV18uqxJnYE6U/YTd6OOvjDpm2J2r0y2aXKWgm6UfBCO4D"
|
||||
`endif
|
||||
+75
@@ -0,0 +1,75 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Inserter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_inserter (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & out_ready) begin
|
||||
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
|
||||
received_esc <= 1;
|
||||
end else begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
//we are always valid
|
||||
out_valid = 1'b1;
|
||||
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
|
||||
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
|
||||
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
|
||||
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
|
||||
in_data; //send data
|
||||
end
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kCRpW4r+SV5JNpaTWRJVwAk9Te9/4uDK/9P0jpNRt3FOTzSu+eCkD8vGTJ5ECpem121uVEsoaBkVw0tq6Pggh2yrt9+q2ZO2tCEdipsY9N2PU9Z9Nj4iWsLLcDXmWgIAHWGO4T2+T7mbqEU5LjSrAMcn2L1vYwRzCNJd0M7ZpmDzHaTrNjl85ThSXMoHSH7N+H07hgkxMC1B30BuOwJxbhVqM0O1bF1Lif3HQMwjuUEiZfWNAJCRVdGevNN+uFzb/N6ZI4U3aK1Pp5wbm6kdhIKTAGgK0GtE8hPWxh5G7DsFE2cHNdngQfX5OYn0LIFo9VE+RF0ce1Kk6/FBWv5zyZObFFLudpM+Dx4HKmNA0hqznPjcEK5HUx/CqIoy+T+89G2VSZc51jSHy763msXNjBNbnLPa0o0GL9GKYUn7eTjFkX0ic3rdZ/cy05luCYKmHyzGod00WDMbQb1yGwwwQ/ZnrEo9c2tl5FZE5pGnOxz7U0HTSL+F3xVmryBy3IzK7Wba5uEE/TNJcXcpdFNyidBoE5DdhffwjzH5ST+9v6dGBiQNWybRauhLu3glW4Y8SP5cbqGqNzDfH3p9Iuo1CS35rXY/zqTXCIYOMxMe/k4eBk5L31Xly023r2RGrhiNrbTK3oG3b458LgR4pkEiQOZI6XT5DbVqmDmF0vbLkOM3U8RLsM2vNiZaHGSgb9yLIl/jIiic1pGCTXXGy7dUH11hlrEfbCYR9WrhCbMQhdb09X6g0/OwAKyeKVpvZXKkoZj8g6iRj6JvK9gbgLl0Ot"
|
||||
`endif
|
||||
+73
@@ -0,0 +1,73 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon ST Idle Remover
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_idle_remover (
|
||||
|
||||
// Interface: clk
|
||||
input clk,
|
||||
input reset_n,
|
||||
// Interface: ST in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
|
||||
// Interface: ST out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Signal Declarations
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
reg received_esc;
|
||||
wire escape_char, idle_char;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Thingofamagick
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
assign idle_char = (in_data == 8'h4a);
|
||||
assign escape_char = (in_data == 8'h4d);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
end else begin
|
||||
if (in_valid & in_ready) begin
|
||||
if (escape_char & ~received_esc) begin
|
||||
received_esc <= 1;
|
||||
end else if (out_valid) begin
|
||||
received_esc <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
//out valid when in_valid. Except when we get idle or escape
|
||||
//however, if we have received an escape character, then we are valid
|
||||
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
|
||||
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
end
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m+IIK1ixAbxPYTwnlCpKSDGmf9frfeCOy1EuDdRMaMJDEncztGlmHshJHRvfDGi/EEg4qjealxu0yL1imOpUKwuC6jLHx+dcdMKTloQvSNAU4Ymo3vSmsF7htT5b7B+pQMk3eJ63Nlxzofxy0nRoc2DSa78oKwkrWsu24+0oPKMoSmiMZAgW09tP9QVzEx7lZXQxm+3D73Xk7A5PXrOZPeu7qTH+pV8ogw4chnFtGP8J3P7FSAaef2V+PkFrJZed+TxKjcfG1zWgD52v1YNr4EwgTXtsfI2IkNCcmUeiJzw0MmKBg0cFqgYY/KXk+ILqaO39elRp0WwiXa0ZgcZ01GZeKMErd/mirZg1w1BoqX+E7VvvuuBkzGRjDflArMJwOmqHDZXKvCmRaegV32DmVtkNv5em3f/A4hvUp6y11KPZoYd/lg3Dv7S2OZT8UtmT62CJPubbNCZr8O+odRCIgO+Msq0LW6sevM+v8eEJzcn8OCYmDyUHyW1XO9jmtBrFFtAYl97lb7cgg6nkgaN3+CafnTFJb+x8piB+Xk/S7gS9ZnKC8xMd1469RwAP9ohUVJHNA60UUFfc6uixYibBz9o86aCTZ0+ICG91msNAwFSGv7UmYnYK8TxTPc7V3eA8puX8bO4h6tt0EAs8Zb794I5mcDCYafM79/RkgRkWtxlMkqSYyASjn/anZHE8GW1Re7jrUJgxWBPIBOMY61EztDDdY/TKPhbH1O4tF7cI4lSVM5OQwfY5RgFqX52cCydrhFFqEIX1NmMX/N/4bLUcyX"
|
||||
`endif
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
# (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License Subscription
|
||||
# Agreement, Altera IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
set_false_path -from [get_registers *altera_jtag_src_crosser:*|sink_data_buffer*] -to [get_registers *altera_jtag_src_crosser:*|src_data*]
|
||||
+229
@@ -0,0 +1,229 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This top level module chooses between the original Altera-ST JTAG Interface
|
||||
// component in ACDS version 8.1 and before, and the new one with the PLI
|
||||
// Simulation mode turned on, which adds a wrapper over the original component.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// altera message_off 16735
|
||||
|
||||
module altera_avalon_st_jtag_interface #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0,
|
||||
parameter EXPORT_JTAG = 0,
|
||||
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
|
||||
parameter PLI_PORT = 50000 // PLI Simulation Port
|
||||
) (
|
||||
input wire jtag_tck,
|
||||
input wire jtag_tms,
|
||||
input wire jtag_tdi,
|
||||
output wire jtag_tdo,
|
||||
input wire jtag_ena,
|
||||
input wire jtag_usr1,
|
||||
input wire jtag_clr,
|
||||
input wire jtag_clrn,
|
||||
input wire jtag_state_tlr,
|
||||
input wire jtag_state_rti,
|
||||
input wire jtag_state_sdrs,
|
||||
input wire jtag_state_cdr,
|
||||
input wire jtag_state_sdr,
|
||||
input wire jtag_state_e1dr,
|
||||
input wire jtag_state_pdr,
|
||||
input wire jtag_state_e2dr,
|
||||
input wire jtag_state_udr,
|
||||
input wire jtag_state_sirs,
|
||||
input wire jtag_state_cir,
|
||||
input wire jtag_state_sir,
|
||||
input wire jtag_state_e1ir,
|
||||
input wire jtag_state_pir,
|
||||
input wire jtag_state_e2ir,
|
||||
input wire jtag_state_uir,
|
||||
input wire [2:0] jtag_ir_in,
|
||||
output wire jtag_irq,
|
||||
output wire [2:0] jtag_ir_out,
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
input wire source_ready,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// Signals in the JTAG clock domain
|
||||
wire tck;
|
||||
wire tdi;
|
||||
wire tdo;
|
||||
wire [2:0] ir_in;
|
||||
wire virtual_state_cdr;
|
||||
wire virtual_state_sdr;
|
||||
wire virtual_state_udr;
|
||||
|
||||
assign jtag_irq = 1'b0;
|
||||
assign jtag_ir_out = 3'b000;
|
||||
|
||||
generate
|
||||
if (EXPORT_JTAG == 0) begin
|
||||
// SLD node instantiation
|
||||
altera_jtag_sld_node node (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_out (3'b0),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_cir (),
|
||||
.virtual_state_e1dr (),
|
||||
.virtual_state_e2dr (),
|
||||
.virtual_state_pdr (),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_uir ()
|
||||
);
|
||||
|
||||
assign jtag_tdo = 1'b0;
|
||||
end else begin
|
||||
assign tck = jtag_tck;
|
||||
assign tdi = jtag_tdi;
|
||||
assign jtag_tdo = tdo;
|
||||
assign ir_in = jtag_ir_in;
|
||||
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
|
||||
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
|
||||
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (USE_PLI == 0)
|
||||
begin : normal
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(source_data),
|
||||
.source_valid(source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(sink_ready),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
end
|
||||
else
|
||||
begin : pli_mode
|
||||
|
||||
//synthesis translate_off
|
||||
reg pli_out_valid;
|
||||
reg pli_in_ready;
|
||||
reg [7 : 0] pli_out_data;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
pli_out_valid <= 0;
|
||||
pli_out_data <= 'b0;
|
||||
pli_in_ready <= 0;
|
||||
end
|
||||
else begin
|
||||
`ifdef MODEL_TECH
|
||||
$do_transaction(
|
||||
PLI_PORT,
|
||||
pli_out_valid,
|
||||
source_ready,
|
||||
pli_out_data,
|
||||
sink_valid,
|
||||
pli_in_ready,
|
||||
sink_data
|
||||
);
|
||||
`endif
|
||||
end
|
||||
end
|
||||
|
||||
//synthesis translate_on
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire jtag_sink_ready;
|
||||
wire jtag_resetrequest;
|
||||
|
||||
altera_jtag_dc_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_dc_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(sink_data),
|
||||
.sink_valid(sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.resetrequest(jtag_resetrequest)//,
|
||||
//.debug_reset(debug_reset),
|
||||
//.mgmt_valid(mgmt_valid),
|
||||
//.mgmt_channel(mgmt_channel),
|
||||
//.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synthesis read_comments_as_HDL on
|
||||
// assign source_valid = jtag_source_valid;
|
||||
// assign source_data = jtag_source_data;
|
||||
// assign sink_ready = jtag_sink_ready;
|
||||
// assign resetrequest = jtag_resetrequest;
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
//synthesis translate_off
|
||||
assign source_valid = pli_out_valid;
|
||||
assign source_data = pli_out_data;
|
||||
assign sink_ready = pli_in_ready;
|
||||
assign resetrequest = 1'b0;
|
||||
//synthesis translate_on
|
||||
assign jtag_tdo = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43kE5SETwJy1XH1XEICOs+R/qa00jHEPMso8nVR5QBxKZ3zmrNoJGALGfV84dFJY7TP7iACdYKKx96iRdKyFJaGqH/GObmGJBmKepuqsSvBxbvatkRUGFK/JteQ8Ui7UML33rpNB0DC9tzM4sjZGGDRROsVvNyeM/JoBEukWM0gp2LrwdU+q8fGVQlxl0Nx7Z+rcS00DCy6lJWwnJ7We9WtGffZfDH2xCBmmC0BI4zytrYMCswtE1vXzQEWmbJ6Hyj0yR9hYVQB3qbgw9w/KCzwPBB/KfwvNIuKJU00I89ABvezTidY9Yq7ybSF83M2CNNSpoF/mGcfnX34Ts8njIrUr/tnmjnUp3Vj3Ykrgr6Bpww5JTPI58bYlZkc9RKqFms1hz+T76tQgMjY2Puh+UVXjT5GNjZa0aeiooqibu2yukQK+h09B029L8BfIqleXx4v3RTJ8Fumdz4qrJWNwHUVcYoInUx+J4SPmD6MlAuIdM/FF/ASfYCTQ0svDaRUgKHAWI4TnxFd9T9Pguxt3p29Umz6BZwrQTmn73OPFtmgFjzqSIpubc6sK20vi8SZxjemX5z4na7wsgUYULmNw2OIDdNsaSiFkJlONz3crAxONGlyQ7/4xMJLOlk03I6UfRoHOO23yZ4vZUqcWl31MmDVkHybED5u1f3shr/pCIZ+nK+gfsvykwJ5psOap3kwbGh37URGjln5a6qQBF18+Ugzf44YSZ/sDI35oa9Tt5DXjk6nxH1oU2wXYC2MZ7JLYefvIxpwR07B8VkgIq2ejHbr4"
|
||||
`endif
|
||||
+222
@@ -0,0 +1,222 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_base (
|
||||
clk,
|
||||
reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter PIPELINE_READY = 1;
|
||||
parameter SYNC_RESET = 0;
|
||||
parameter BACKPRESSURE_DURING_RESET = 0;
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input clk;
|
||||
input reset;
|
||||
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
reg full0;
|
||||
reg full1;
|
||||
reg [DATA_WIDTH-1:0] data0;
|
||||
reg [DATA_WIDTH-1:0] data1;
|
||||
|
||||
assign out_valid = full1;
|
||||
assign out_data = data1;
|
||||
|
||||
// Generation of internal reset synchronization
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (PIPELINE_READY == 1)
|
||||
begin : REGISTERED_READY_PLINE
|
||||
|
||||
assign in_ready = !full0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
// ----------------------------
|
||||
// always load the second slot if we can
|
||||
// ----------------------------
|
||||
if (~full0)
|
||||
data0 <= in_data;
|
||||
// ----------------------------
|
||||
// first slot is loaded either from the second,
|
||||
// or with new data
|
||||
// ----------------------------
|
||||
if (~full1 || (out_ready && out_valid)) begin
|
||||
if (full0)
|
||||
data1 <= data0;
|
||||
else
|
||||
data1 <= in_data;
|
||||
end
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst0
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
// out of reset.
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
// no data in pipeline
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end // ~f1 & ~f0
|
||||
|
||||
// one datum in pipeline
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
// back to empty
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end // f1 & ~f0
|
||||
|
||||
// two data in pipeline
|
||||
if (full1 & full0) begin
|
||||
// go back to one datum state
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end // end go back to one datum stage
|
||||
end
|
||||
end
|
||||
end // async_rst0
|
||||
else begin // sync_rst0
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
// out of reset.
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
// no data in pipeline
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end // ~f1 & ~f0
|
||||
|
||||
// one datum in pipeline
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
// back to empty
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end // f1 & ~f0
|
||||
|
||||
// two data in pipeline
|
||||
if (full1 & full0) begin
|
||||
// go back to one datum state
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end // end go back to one datum stage
|
||||
end
|
||||
end
|
||||
end // sync_rst0
|
||||
end
|
||||
else
|
||||
begin : UNREGISTERED_READY_PLINE
|
||||
|
||||
// in_ready will be a pass through of the out_ready signal as it is not registered
|
||||
assign in_ready = (~full1) | out_ready;
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst1
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // async_rst1
|
||||
else begin // sync_rst1
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // sync_rst1
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m+2WbbziRXNHGvxsiU9BKfbzYIwxqkjbRY646Jry08YTxgl+u6Mpx3BaAnY8zD8arB0qHAHWeHxZk4Hc5CUUMkBqNpBDW51MKpXcPm9ytMiKASxRBYyGC1DUc1qjCFcJ5eP5kqviLbdBDKpFyc4xAZtJR3LjcT2rHr0r0dcOSAei50r8+hZH5ImpM5IZVnLbFjvfn4gTm34ATDBGaBb/k1ixtHUMFRwKcfLhVwgd8+qp2ZJ42U9B2sa83JRKaJOUtJVMRsuQ4zH1pDaBVKz7tvcbQ9KL6BBsCE6Sn4uDBb1m/T5jxvgV5CgkGSt3amLUBTupfKUvmukO0wGF8cOyjjsWhBq1qj9uHJBIsE6jwGoavEMRH7KppIs+N4blyw3mkk8JbsyZPTmQwkEUKc2Eu8+YcGa/yBIOJeGapk3JOOMjZMuI9zGnVgMljFU0MZZpzbVzMsGSddTz1Cd1namRpB7EOF2NFXOu8hoePaL/YYTrXZAfM5iEuTRjAzVa9LsjKI3vp/WpNZ6Kq6djMwZ7YilOOcNsiCALgQe+1s0QGFBQ7zYwJE7udtUdsEw9GhzuG98Vo/3mB6Z4cGzvj86WrHyy1X9WuRyTDVSGGvAxMWPBEHomZd8TS4+FkOF5oH9QDGhrzKgYpLsfkbAhYvDH4ZjsA2q1aJCrEUFoXGZC8fwYEgx9xhV5T9Hre3WKR3wWPXLu3J/SQ4ecRTdkpcZY0DRzrXao825TRnfAqfECespkaam8sE849QMiWHBh/p0vH+n54ztMPrCthmLaeUe5/O"
|
||||
`endif
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $File: //acds/rel/26.1/ip/iconnect/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage.sv $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
// $Author: psgswbuild $
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_stage #(
|
||||
parameter
|
||||
USE_FIFO_IP = 0, // unsued at moment
|
||||
SYMBOLS_PER_BEAT = 1,
|
||||
BITS_PER_SYMBOL = 8,
|
||||
USE_PACKETS = 0,
|
||||
USE_EMPTY = 0,
|
||||
PIPELINE_READY = 1,
|
||||
SYNC_RESET = 0,
|
||||
// Optional ST signal widths. Value "0" means no such port.
|
||||
CHANNEL_WIDTH = 0,
|
||||
ERROR_WIDTH = 0,
|
||||
|
||||
// Derived parameters
|
||||
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
|
||||
PACKET_WIDTH = 0,
|
||||
EMPTY_WIDTH = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
output in_ready,
|
||||
input in_valid,
|
||||
input [DATA_WIDTH - 1 : 0] in_data,
|
||||
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
|
||||
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
|
||||
|
||||
input out_ready,
|
||||
output out_valid,
|
||||
output [DATA_WIDTH - 1 : 0] out_data,
|
||||
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
|
||||
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
|
||||
output out_startofpacket,
|
||||
output out_endofpacket,
|
||||
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
|
||||
);
|
||||
localparam
|
||||
PAYLOAD_WIDTH =
|
||||
DATA_WIDTH +
|
||||
PACKET_WIDTH +
|
||||
CHANNEL_WIDTH +
|
||||
EMPTY_WIDTH +
|
||||
ERROR_WIDTH;
|
||||
|
||||
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
|
||||
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
|
||||
|
||||
// Assign in_data and other optional in_* interface signals to in_payload.
|
||||
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
|
||||
generate
|
||||
// optional packet inputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH - 1 :
|
||||
DATA_WIDTH
|
||||
] = {in_startofpacket, in_endofpacket};
|
||||
end
|
||||
// optional channel input
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
] = in_channel;
|
||||
end
|
||||
// optional empty input
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
] = in_empty;
|
||||
end
|
||||
// optional error input
|
||||
if (ERROR_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
] = in_error;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
localparam NUM_128BIT_SLOTS = (PAYLOAD_WIDTH / 128) + (((PAYLOAD_WIDTH % 128) == 0) ? 0 : 1);
|
||||
localparam LAST_PAYLOAD_W = ((PAYLOAD_WIDTH % 128) == 0) ? 128 : (PAYLOAD_WIDTH % 128);
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < NUM_128BIT_SLOTS; i = i + 1) begin : gen_inst
|
||||
if (i == NUM_128BIT_SLOTS - 1) begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (LAST_PAYLOAD_W),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (in_ready),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (out_valid),
|
||||
.out_data (out_payload[(i*128)+LAST_PAYLOAD_W-1:i*128])
|
||||
);
|
||||
end
|
||||
else begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (128),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i+1)*128-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (),
|
||||
.out_data (out_payload[(i+1)*128-1:i*128])
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Assign out_data and other optional out_* interface signals from out_payload.
|
||||
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
|
||||
generate
|
||||
// optional packet outputs
|
||||
if (PACKET_WIDTH) begin
|
||||
assign {out_startofpacket, out_endofpacket} =
|
||||
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign {out_startofpacket, out_endofpacket} = 2'b0;
|
||||
end
|
||||
|
||||
// optional channel output
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign out_channel = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_channel = 1'b0;
|
||||
end
|
||||
// optional empty output
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign out_empty = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_empty = 1'b0;
|
||||
end
|
||||
// optional error output
|
||||
if (ERROR_WIDTH) begin
|
||||
assign out_error = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
];
|
||||
end else begin
|
||||
// Avoid a "has no driver" warning.
|
||||
assign out_error = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43lzNdzic8kf095rgT/UkF24bAsY8NGL39W2vnb6QHycbl1peRxuMswSGmotl+qU7rTPIN3gVwEy7e13KVfLqnUSbl5Aj/njXXTCqo0XReaJeMqVFNLoUFEke22KyVtbOBwxIqkfp66fh+LWjI8lLUheUnX8eq4FgV+krso2vFPZ546y52KsJs5qTfDpbX85DJ0+l6Sg4mvb0n9nLB+1SBwdQxY+r1X93owARyzVOcF5CIBN3i1YywJdDG2I6/wxZvAVIxD4KPrlWY8xxukciAYJpr7+Oxf07u7Bv9H7LS8ql7c3ZPPL6Kpk7gEXCnrndNnqENjDVEtnvbjA6q+vmxDW9LgWTd6FRrTHU5Um7j2HfYjJbl2DU/X/VTzmGL3KXLvc1D5ep6LYnHgBoyJbdio3ArirlItOV5zcEnJGUvohgbi/xykdpALrQjbFkskaqu+K/ngGgtZ4YyA1F1U3MJQ9F/wkhC/NqgVc4K5CDIi+J8c2KoINY8OXRB0RtZB0MHeyCpS3WwAzlWQKEYI7Lxkb+2RKzqymsSdH5CltjfEgf4SFk/bXwnv33gBS8bg6OZwu+StypSNvj5Z9C+2aokZD39boscHt24WZchtkJsQtgNM7leRuB9n60dKI+nHwPtiYa5FghnJBzSyeQ49QcgDovq9MQlu/FGFMeXM/mYvcN4Fo2janBMoGBSGEidqiL0nZZxZV6q0inrtQVERT2AkPmL/m7JtCU2FMDauZoOIZ6p2O1DWpE0OzBGyHYRE+yhwMyzOAlT6Yq8VeAt7hHIgA"
|
||||
`endif
|
||||
+264
@@ -0,0 +1,264 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// This module is a simple clock crosser for control signals. It will take
|
||||
// the asynchronous control signal and synchronize it to the clk domain
|
||||
// attached to the clk input. It does so by passing the control signal
|
||||
// through a pair of registers and then sensing the level transition from
|
||||
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
|
||||
// that the control signal will always transition every time is asserted.
|
||||
// i.e.:
|
||||
// ____ ___________________
|
||||
// -> ___| |___ and ___| |_____
|
||||
//
|
||||
// on the control signal will be seen as only one assertion of the control
|
||||
// signal. In short, if your control could be asserted back-to-back, then
|
||||
// don't use this module. You'll be losing data.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_jtag_control_signal_crosser (
|
||||
clk,
|
||||
reset_n,
|
||||
async_control_signal,
|
||||
sense_pos_edge,
|
||||
sync_control_signal
|
||||
);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input async_control_signal;
|
||||
input sense_pos_edge;
|
||||
output sync_control_signal;
|
||||
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
reg sync_control_signal;
|
||||
|
||||
wire synchronized_raw_signal;
|
||||
reg edge_detector_register;
|
||||
|
||||
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.din(async_control_signal),
|
||||
.dout(synchronized_raw_signal)
|
||||
);
|
||||
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
if (~reset_n)
|
||||
edge_detector_register <= 1'b0;
|
||||
else
|
||||
edge_detector_register <= synchronized_raw_signal;
|
||||
|
||||
always @* begin
|
||||
if (sense_pos_edge)
|
||||
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
|
||||
else
|
||||
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
|
||||
end
|
||||
endmodule
|
||||
|
||||
// This module crosses the clock domain for a given source
|
||||
module altera_jtag_src_crosser (
|
||||
sink_clk,
|
||||
sink_reset_n,
|
||||
sink_valid,
|
||||
sink_data,
|
||||
src_clk,
|
||||
src_reset_n,
|
||||
src_valid,
|
||||
src_data
|
||||
);
|
||||
parameter WIDTH = 8;
|
||||
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
|
||||
|
||||
input sink_clk;
|
||||
input sink_reset_n;
|
||||
input sink_valid;
|
||||
input [WIDTH-1:0] sink_data;
|
||||
input src_clk;
|
||||
input src_reset_n;
|
||||
output src_valid;
|
||||
output [WIDTH-1:0] src_data;
|
||||
|
||||
reg sink_valid_buffer;
|
||||
reg [WIDTH-1:0] sink_data_buffer;
|
||||
|
||||
reg src_valid;
|
||||
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
|
||||
|
||||
wire synchronized_valid;
|
||||
|
||||
altera_jtag_control_signal_crosser #(
|
||||
.SYNC_DEPTH(SYNC_DEPTH)
|
||||
) crosser (
|
||||
.clk(src_clk),
|
||||
.reset_n(src_reset_n),
|
||||
.async_control_signal(sink_valid_buffer),
|
||||
.sense_pos_edge(1'b1),
|
||||
.sync_control_signal(synchronized_valid)
|
||||
);
|
||||
always @ (posedge sink_clk or negedge sink_reset_n) begin
|
||||
if (~sink_reset_n) begin
|
||||
sink_valid_buffer <= 1'b0;
|
||||
sink_data_buffer <= 'b0;
|
||||
end else begin
|
||||
sink_valid_buffer <= sink_valid;
|
||||
if (sink_valid) begin
|
||||
sink_data_buffer <= sink_data;
|
||||
end
|
||||
end //end if
|
||||
end //always sink_clk
|
||||
|
||||
always @ (posedge src_clk or negedge src_reset_n) begin
|
||||
if (~src_reset_n) begin
|
||||
src_valid <= 1'b0;
|
||||
src_data <= {WIDTH{1'b0}};
|
||||
end else begin
|
||||
src_valid <= synchronized_valid;
|
||||
src_data <= synchronized_valid ? sink_data_buffer : src_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module altera_jtag_dc_streaming #(
|
||||
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
|
||||
// for JTAG Phy, 1 for Packets to Master
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0
|
||||
) (
|
||||
// Signals in the JTAG clock domain
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output wire tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire clk,
|
||||
input wire reset_n,
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
output wire resetrequest,
|
||||
output wire debug_reset,
|
||||
output wire mgmt_valid,
|
||||
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output wire mgmt_data
|
||||
);
|
||||
|
||||
// the tck to sysclk sync depth is fixed at 8
|
||||
// 8 is the worst case scenario from our metastability analysis, and since
|
||||
// using TCK serially is so slow we should have plenty of clock cycles.
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
|
||||
// Since the tck clock is so slow, no parameter is exposed.
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
|
||||
wire jtag_clock_reset_n; // system reset is synchronized with tck
|
||||
wire [7:0] jtag_source_data;
|
||||
wire jtag_source_valid;
|
||||
wire [7:0] jtag_sink_data;
|
||||
wire jtag_sink_valid;
|
||||
wire jtag_sink_ready;
|
||||
|
||||
/* Reset Synchronizer module.
|
||||
*
|
||||
* The SLD Node does not provide a reset for the TCK clock domain.
|
||||
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
|
||||
* internal states need to be reset to 0 in order to guarantee proper
|
||||
* functionality throughout resets.
|
||||
*
|
||||
* This reset block will asynchronously assert reset, and synchronously
|
||||
* deassert reset for the tck clock domain.
|
||||
*/
|
||||
altera_std_synchronizer #(
|
||||
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
|
||||
) synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(reset_n),
|
||||
.din(1'b1),
|
||||
.dout(jtag_clock_reset_n)
|
||||
);
|
||||
|
||||
altera_jtag_streaming #(
|
||||
.PURPOSE(PURPOSE),
|
||||
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
|
||||
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
|
||||
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
|
||||
) jtag_streaming (
|
||||
.tck (tck),
|
||||
.tdi (tdi),
|
||||
.tdo (tdo),
|
||||
.ir_in (ir_in),
|
||||
.virtual_state_cdr(virtual_state_cdr),
|
||||
.virtual_state_sdr(virtual_state_sdr),
|
||||
.virtual_state_udr(virtual_state_udr),
|
||||
|
||||
.reset_n(jtag_clock_reset_n),
|
||||
.source_data(jtag_source_data),
|
||||
.source_valid(jtag_source_valid),
|
||||
.sink_data(jtag_sink_data),
|
||||
.sink_valid(jtag_sink_valid),
|
||||
.sink_ready(jtag_sink_ready),
|
||||
.clock_to_sample(clk),
|
||||
.reset_to_sample(reset_n),
|
||||
.resetrequest(resetrequest),
|
||||
.debug_reset(debug_reset),
|
||||
.mgmt_valid(mgmt_valid),
|
||||
.mgmt_channel(mgmt_channel),
|
||||
.mgmt_data(mgmt_data)
|
||||
);
|
||||
|
||||
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
|
||||
|
||||
altera_avalon_st_clock_crosser #(
|
||||
.SYMBOLS_PER_BEAT(1),
|
||||
.BITS_PER_SYMBOL(8),
|
||||
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
|
||||
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) sink_crosser (
|
||||
.in_clk(clk),
|
||||
.in_reset(~reset_n),
|
||||
.in_data(sink_data),
|
||||
.in_ready(sink_ready),
|
||||
.in_valid(sink_valid),
|
||||
.out_clk(tck),
|
||||
.out_reset(~jtag_clock_reset_n),
|
||||
.out_data(jtag_sink_data),
|
||||
.out_ready(jtag_sink_ready),
|
||||
.out_valid(jtag_sink_valid)
|
||||
);
|
||||
|
||||
altera_jtag_src_crosser #(
|
||||
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
|
||||
) source_crosser (
|
||||
.sink_clk(tck),
|
||||
.sink_reset_n(jtag_clock_reset_n),
|
||||
.sink_valid(jtag_source_valid),
|
||||
.sink_data(jtag_source_data),
|
||||
.src_clk(clk),
|
||||
.src_reset_n(reset_n),
|
||||
.src_valid(source_valid),
|
||||
.src_data(source_data)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43mf05yrKMA+uPdz5tOrx7e5HExSwPsvBYo6nuRS+JViKkGWUOniDW3NDMxPpUiEChz1wDtyqt0bYSnK0cPHA0neGHMbl9mxVDoyOW9dlDnU0P+Ym6p1vzyQYq52H54kJy0/c2GKCikQaqX+YZG1pBZ8V1YlMDOepq+7WF8JX+GAmDLFbl4L26qzoGrlN8LdW+Qr9k9ZxE8W1J5okyjtyTvqLTXCbxxGD0ZwAKjQeQl4U35Fdi4PNa2IdJc+h4nOoJ0WJEa6i65rhFGLDxHYlwWBBFZt4MoFrk7Bw7MzQXNHkV0UHlnK6oqS6Rka3xOujIzwzOqgDXjaSoXt7Ts4VRjY08temLjq2rgczO+5ED6hks3Qh9Yx1GnZnEnLTpc/zmAYd3jStXvd8MmeLvriTIAGcm4vNW1viqjaQaBnIobM3TOc+Z8P8oKk6P3JO/7t89bGi5/A7HojpJw0daAZkSDHyh7xQfDDc+GJeRg5k5tPVf65FmVbpco36fRM5fQwhnmXisNZkoEgYO044IoBceUE4HD6jbh2umBVPDrb66IvDZyr/64QmjHMNT6uzPUsph1jBD0BhzoPwllykfeQhEnHrIrXQ/s+QKBImnLRlix4+rMt0cWaqJ+tZ7i1V2tqTA1hSR5HjXN+NtuCoDTtnMV+fMrPTa2VARCrY6Bh2DM63R0fNSjnq+5pB8SbDlmb6EDxYKzZDSJTB2pXfiHco8gHytfgMSvg4m1LKS9xUVDV2VjnxoKbWPBfr8fCCcfSm1Qb54affjg0pAgS6lz2zkGD"
|
||||
`endif
|
||||
+264
@@ -0,0 +1,264 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
module altera_jtag_sld_node (
|
||||
ir_out,
|
||||
tdo,
|
||||
ir_in,
|
||||
tck,
|
||||
tdi,
|
||||
virtual_state_cdr,
|
||||
virtual_state_cir,
|
||||
virtual_state_e1dr,
|
||||
virtual_state_e2dr,
|
||||
virtual_state_pdr,
|
||||
virtual_state_sdr,
|
||||
virtual_state_udr,
|
||||
virtual_state_uir
|
||||
);
|
||||
|
||||
parameter TCK_FREQ_MHZ = 20;
|
||||
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
input [IRWIDTH - 1:0] ir_out;
|
||||
input tdo;
|
||||
output reg [IRWIDTH - 1:0] ir_in;
|
||||
output tck;
|
||||
output reg tdi = 1'b0;
|
||||
output virtual_state_cdr;
|
||||
output virtual_state_cir;
|
||||
output virtual_state_e1dr;
|
||||
output virtual_state_e2dr;
|
||||
output virtual_state_pdr;
|
||||
output virtual_state_sdr;
|
||||
output virtual_state_udr;
|
||||
output virtual_state_uir;
|
||||
|
||||
// PHY Simulation signals
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
reg simulation_clock;
|
||||
reg sdrs;
|
||||
reg cdr;
|
||||
reg sdr;
|
||||
reg e1dr;
|
||||
reg udr;
|
||||
reg [7:0] bit_index;
|
||||
`endif
|
||||
|
||||
|
||||
// PHY Instantiation
|
||||
`ifdef ALTERA_RESERVED_QIS
|
||||
wire tdi_port;
|
||||
wire [IRWIDTH - 1:0] ir_in_port;
|
||||
always @(tdi_port)
|
||||
tdi = tdi_port;
|
||||
always @(ir_in_port)
|
||||
ir_in = ir_in_port;
|
||||
sld_virtual_jtag_basic sld_virtual_jtag_component (
|
||||
.ir_out (ir_out),
|
||||
.tdo (tdo),
|
||||
.tdi (tdi_port),
|
||||
.tck (tck),
|
||||
.ir_in (ir_in_port),
|
||||
.virtual_state_cir (virtual_state_cir),
|
||||
.virtual_state_pdr (virtual_state_pdr),
|
||||
.virtual_state_uir (virtual_state_uir),
|
||||
.virtual_state_sdr (virtual_state_sdr),
|
||||
.virtual_state_cdr (virtual_state_cdr),
|
||||
.virtual_state_udr (virtual_state_udr),
|
||||
.virtual_state_e1dr (virtual_state_e1dr),
|
||||
.virtual_state_e2dr (virtual_state_e2dr)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.jtag_state_cdr (),
|
||||
.jtag_state_cir (),
|
||||
.jtag_state_e1dr (),
|
||||
.jtag_state_e1ir (),
|
||||
.jtag_state_e2dr (),
|
||||
.jtag_state_e2ir (),
|
||||
.jtag_state_pdr (),
|
||||
.jtag_state_pir (),
|
||||
.jtag_state_rti (),
|
||||
.jtag_state_sdr (),
|
||||
.jtag_state_sdrs (),
|
||||
.jtag_state_sir (),
|
||||
.jtag_state_sirs (),
|
||||
.jtag_state_tlr (),
|
||||
.jtag_state_udr (),
|
||||
.jtag_state_uir (),
|
||||
.tms ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
sld_virtual_jtag_component.sld_mfg_id = 110,
|
||||
sld_virtual_jtag_component.sld_type_id = 132,
|
||||
sld_virtual_jtag_component.sld_version = 1,
|
||||
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
|
||||
sld_virtual_jtag_component.sld_instance_index = 0,
|
||||
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
|
||||
sld_virtual_jtag_component.sld_sim_action = "",
|
||||
sld_virtual_jtag_component.sld_sim_n_scan = 0,
|
||||
sld_virtual_jtag_component.sld_sim_total_length = 0;
|
||||
`endif
|
||||
|
||||
// PHY Simulation
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
always
|
||||
//#TCK_HALF_PERIOD_US simulation_clock = $random;
|
||||
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
|
||||
|
||||
assign tck = simulation_clock;
|
||||
assign virtual_state_cdr = cdr;
|
||||
assign virtual_state_sdr = sdr;
|
||||
assign virtual_state_e1dr = e1dr;
|
||||
assign virtual_state_udr = udr;
|
||||
|
||||
task reset_jtag_state;
|
||||
begin
|
||||
simulation_clock = 0;
|
||||
enter_data_mode;
|
||||
clear_states_async;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_data_mode;
|
||||
begin
|
||||
ir_in = DATA;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_loopback_mode;
|
||||
begin
|
||||
ir_in = LOOPBACK;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_debug_mode;
|
||||
begin
|
||||
ir_in = DEBUG;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_info_mode;
|
||||
begin
|
||||
ir_in = INFO;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_control_mode;
|
||||
begin
|
||||
ir_in = CONTROL;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_mgmt_mode;
|
||||
begin
|
||||
ir_in = MGMT;
|
||||
clear_states;
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_sdrs_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_cdr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_e1dr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task enter_udr_state;
|
||||
begin
|
||||
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
|
||||
tdi = 1'b0;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states;
|
||||
begin
|
||||
clear_states_async;
|
||||
@(posedge tck);
|
||||
end
|
||||
endtask
|
||||
|
||||
task clear_states_async;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0000;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_bit;
|
||||
input bit_to_send;
|
||||
output reg bit_received;
|
||||
begin
|
||||
{cdr, sdr, e1dr, udr} = 4'b0100;
|
||||
tdi = bit_to_send;
|
||||
@(posedge tck);
|
||||
bit_received = tdo;
|
||||
end
|
||||
endtask
|
||||
|
||||
task shift_one_byte;
|
||||
input [7:0] byte_to_send;
|
||||
output reg [7:0] byte_received;
|
||||
integer i;
|
||||
reg bit_received;
|
||||
begin
|
||||
for (i=0; i<8; i=i+1)
|
||||
begin
|
||||
bit_index = i;
|
||||
shift_one_bit(byte_to_send[i], bit_received);
|
||||
byte_received[i] = bit_received;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43lBZX0Ql68xHccZnfqaRGQKXb+suw0+G/pVTEtXeJpzBq/7bnHCezbavBscZWMlhms2Wz2URmxx5AQLfZNrIwyosndTDl7mhnY6ckOE2QmsqzCPHFVfq4mRCzHjlTEGBvU3Pi38puWVFCyHUhgA9k5vRLZLgICA671LQ7mWobio/jqN82rZy/80hkczOwRBCHIoEVojMe7Kee0pbosxgMF1hkjKr5sjgpJOuqnyk4mT2P6InXKbojsvp3j8x0NMlhZOLjYgGBtL4CeflmEzC2f1K6TWppWrqIv/d8t6sEGsAcEGhf/yaUUSe52KNjrmgKMp4cGL2M9LaQ++/BgomIZGsd5X3dgDh1XBHnCeY3AWP5sbZTrUGvsMJQBDYG/U9hdKB3l+nEMztYgo/WSROuURMSAuR14Qo+CHE6+OhjGLoOK1H+5Au7Alv7ZPDO39BRzf5JTH9LBHOCmhvRB7L5PsG9GP1+JpBpvCRQTt5Hv+fyOo521Uk2R1SU2tiXA2S3GgwsxTJjt9PLhSg2EgIkvixp5B4uO24Xy4vepP5zBOrHa/viz3qjUzdfJsOUOm/0q9mtykoOCHfBQ/mraGzh6nemQdKQ5vLYUn+G6AseV+rRLINc0S8qKakNetEG0zXEKBXfXIism4w+uKFnlomoQ1+TS+kj2fXKzUZW2eiWHL9azON0cDdGmTDQS8hu0p7Lf2x6iOlJUT9Po56UXAOLwOpCXHhiz8kfDU6ZBQDuZx0B/acIgjJ0p57A0qd2sFzN8oX7UcAIq/FF4EUfKiHNDk"
|
||||
`endif
|
||||
+650
@@ -0,0 +1,650 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ns / 1 ns
|
||||
// synopsys translate_on
|
||||
|
||||
module altera_jtag_streaming #(
|
||||
parameter PURPOSE = 0,
|
||||
parameter UPSTREAM_FIFO_SIZE = 0,
|
||||
parameter DOWNSTREAM_FIFO_SIZE = 0,
|
||||
parameter MGMT_CHANNEL_WIDTH = 0
|
||||
) (
|
||||
// JTAG Signals
|
||||
input wire tck,
|
||||
input wire tdi,
|
||||
output reg tdo,
|
||||
input wire [2:0] ir_in,
|
||||
input wire virtual_state_cdr,
|
||||
input wire virtual_state_sdr,
|
||||
input wire virtual_state_udr,
|
||||
|
||||
input wire reset_n,
|
||||
// Source Signals
|
||||
output wire [7:0] source_data,
|
||||
output wire source_valid,
|
||||
// Sink Signals
|
||||
input wire [7:0] sink_data,
|
||||
input wire sink_valid,
|
||||
output wire sink_ready,
|
||||
// Clock Debug Signals
|
||||
input wire clock_to_sample,
|
||||
input wire reset_to_sample,
|
||||
// Resetrequest signal
|
||||
output reg resetrequest,
|
||||
// Debug reset and management channel
|
||||
output wire debug_reset,
|
||||
output reg mgmt_valid,
|
||||
output reg [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
|
||||
output reg mgmt_data
|
||||
);
|
||||
|
||||
// function to calculate log2, floored.
|
||||
function integer flog2;
|
||||
input [31:0] Depth;
|
||||
integer i;
|
||||
begin
|
||||
i = Depth;
|
||||
if ( i <= 0 ) flog2 = 0;
|
||||
else begin
|
||||
for(flog2 = -1; i > 0; flog2 = flog2 + 1)
|
||||
i = i >> 1;
|
||||
end
|
||||
end
|
||||
endfunction // flog2
|
||||
|
||||
localparam UPSTREAM_ENCODED_SIZE = flog2(UPSTREAM_FIFO_SIZE);
|
||||
localparam DOWNSTREAM_ENCODED_SIZE = flog2(DOWNSTREAM_FIFO_SIZE);
|
||||
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
|
||||
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
|
||||
localparam TCK_TO_SYSCLK_SYNC_DEPTH_PLUS_ONE = 9;
|
||||
|
||||
// IR values determine the operating modes
|
||||
localparam DATA = 0;
|
||||
localparam LOOPBACK = 1;
|
||||
localparam DEBUG = 2;
|
||||
localparam INFO = 3;
|
||||
localparam CONTROL = 4;
|
||||
localparam MGMT = 5;
|
||||
|
||||
// Operating Modes:
|
||||
// Data - To send data which its size and valid position are encoded in the header bytes of the data stream
|
||||
// Loopback - To become a JTAG loopback with a bypass register
|
||||
// Debug - To read the values of the clock sensing, clock sampling and reset sampling
|
||||
// Info - To read the parameterized values that describe the components connected to JTAG Phy which is of great interest to the driver
|
||||
// Control - To set the offset of bit-padding and to do a reset request
|
||||
// Mgmt - Send management commands (resets mostly) to agents
|
||||
|
||||
localparam IRWIDTH = 3;
|
||||
|
||||
// State machine encoding for write_state
|
||||
localparam ST_BYPASS = 'h0;
|
||||
localparam ST_HEADER_1 = 'h1;
|
||||
localparam ST_HEADER_2 = 'h2;
|
||||
localparam ST_WRITE_DATA = 'h3;
|
||||
|
||||
// State machine encoding for read_state
|
||||
localparam ST_HEADER = 'h0;
|
||||
localparam ST_PADDED = 'h1;
|
||||
localparam ST_READ_DATA = 'h2;
|
||||
|
||||
reg [1:0] write_state = ST_BYPASS;
|
||||
reg [1:0] read_state = ST_HEADER;
|
||||
|
||||
reg [ 7:0] dr_data_in = 'b0;
|
||||
reg [ 7:0] dr_data_out = 'b0;
|
||||
reg dr_loopback = 'b0;
|
||||
reg [ 2:0] dr_debug = 'b0;
|
||||
reg [10:0] dr_info = 'b0;
|
||||
reg [ 8:0] dr_control = 'b0;
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] dr_mgmt = 'b0;
|
||||
|
||||
reg [ 8:0] padded_bit_counter = 'b0;
|
||||
reg [ 7:0] bypass_bit_counter = 'b0;
|
||||
reg [ 2:0] write_data_bit_counter = 'b0;
|
||||
reg [ 2:0] read_data_bit_counter = 'b0;
|
||||
reg [ 3:0] header_in_bit_counter = 'b0;
|
||||
reg [ 3:0] header_out_bit_counter = 'b0;
|
||||
reg [18:0] scan_length_byte_counter = 'b0;
|
||||
reg [18:0] valid_write_data_length_byte_counter = 'b0;
|
||||
|
||||
reg write_data_valid = 'b0;
|
||||
reg read_data_valid = 'b0;
|
||||
reg read_data_all_valid = 'b0;
|
||||
|
||||
reg decode_header_1 = 'b0;
|
||||
reg decode_header_2 = 'b0;
|
||||
|
||||
wire write_data_byte_aligned;
|
||||
wire read_data_byte_aligned;
|
||||
wire padded_bit_byte_aligned;
|
||||
wire bytestream_end;
|
||||
|
||||
assign write_data_byte_aligned = (write_data_bit_counter == 1);
|
||||
assign read_data_byte_aligned = (read_data_bit_counter == 1);
|
||||
assign padded_bit_byte_aligned = (padded_bit_counter[2:0] == 'b0);
|
||||
assign bytestream_end = (scan_length_byte_counter == 'b0);
|
||||
|
||||
reg [ 7:0] offset = 'b0;
|
||||
reg [15:0] header_in = 'b0;
|
||||
|
||||
reg [9:0] scan_length = 'b0;
|
||||
reg [2:0] read_data_length = 'b0;
|
||||
reg [2:0] write_data_length = 'b0;
|
||||
|
||||
wire [7:0] idle_inserter_sink_data;
|
||||
wire idle_inserter_sink_valid;
|
||||
wire idle_inserter_sink_ready;
|
||||
wire [7:0] idle_inserter_source_data;
|
||||
reg idle_inserter_source_ready = 'b0;
|
||||
reg [7:0] idle_remover_sink_data = 'b0;
|
||||
reg idle_remover_sink_valid = 'b0;
|
||||
wire [7:0] idle_remover_source_data;
|
||||
wire idle_remover_source_valid;
|
||||
|
||||
assign source_data = idle_remover_source_data;
|
||||
assign source_valid = idle_remover_source_valid;
|
||||
assign sink_ready = idle_inserter_sink_ready;
|
||||
assign idle_inserter_sink_data = sink_data;
|
||||
assign idle_inserter_sink_valid = sink_valid;
|
||||
|
||||
reg clock_sensor = 'b0;
|
||||
reg clock_to_sample_div2 = 'b0;
|
||||
(* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg clock_sense_reset_n = 'b1;
|
||||
|
||||
wire data_available;
|
||||
|
||||
assign data_available = sink_valid;
|
||||
|
||||
wire [18:0] decoded_scan_length;
|
||||
wire [18:0] decoded_write_data_length;
|
||||
wire [18:0] decoded_read_data_length;
|
||||
|
||||
assign decoded_scan_length = { scan_length, {8{1'b1}} };
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | scan_length | Length (bytes) | decoded_scan_length |
|
||||
// +-------------------+----------------+---------------------+
|
||||
// | 0x0 | 256 | 0x0ff (255) |
|
||||
// | 0x1 | 512 | 0x1ff (511) |
|
||||
// | 0x2 | 768 | 0x2ff (767) |
|
||||
// | . | . | . |
|
||||
// | 0x3ff | 256k | 0x3ff (256k-1) |
|
||||
// +-------------------+----------------+---------------------+
|
||||
|
||||
// TODO: use look up table to save LEs?
|
||||
// Decoded value is correct except for 0x7
|
||||
assign decoded_write_data_length = (write_data_length == 0) ? 19'h0 : (19'h00080 << write_data_length);
|
||||
assign decoded_read_data_length = (read_data_length == 0) ? 19'h0 : (19'h00080 << read_data_length);
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | read_data_length | Length | decoded_read_data_length |
|
||||
// | write_data_length | (bytes) | decoded_write_data_length |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
// | 0x0 | 0 | 0x0000 (0) |
|
||||
// | 0x1 | 256 | 0x0100 (256) |
|
||||
// | 0x2 | 512 | 0x0200 (512) |
|
||||
// | 0x3 | 1k | 0x0400 (1024) |
|
||||
// | 0x4 | 2k | 0x0800 (2048) |
|
||||
// | 0x5 | 4k | 0x1000 (4096) |
|
||||
// | 0x6 | 8k | 0x2000 (8192) |
|
||||
// | 0x7 | scan_length | invalid |
|
||||
// +-------------------+---------------+---------------------------+
|
||||
|
||||
wire clock_sensor_sync;
|
||||
wire reset_to_sample_sync;
|
||||
wire clock_to_sample_div2_sync;
|
||||
wire clock_sense_reset_n_sync;
|
||||
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_sensor_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_sensor),
|
||||
.dout(clock_sensor_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) reset_to_sample_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(reset_to_sample),
|
||||
.dout(reset_to_sample_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(SYSCLK_TO_TCK_SYNC_DEPTH)) clock_to_sample_div2_synchronizer (
|
||||
.clk(tck),
|
||||
.reset_n(1'b1),
|
||||
.din(clock_to_sample_div2),
|
||||
.dout(clock_to_sample_div2_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) clock_sense_reset_n_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(clock_sense_reset_n),
|
||||
.din(1'b1),
|
||||
.dout(clock_sense_reset_n_sync));
|
||||
|
||||
|
||||
|
||||
always @ (posedge clock_to_sample or negedge clock_sense_reset_n_sync) begin
|
||||
if (~clock_sense_reset_n_sync) begin
|
||||
clock_sensor <= 1'b0;
|
||||
end else begin
|
||||
clock_sensor <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clock_to_sample) begin
|
||||
clock_to_sample_div2 <= ~clock_to_sample_div2;
|
||||
end
|
||||
|
||||
always @ (posedge tck) begin
|
||||
|
||||
idle_remover_sink_valid <= 1'b0;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
|
||||
// Data mode sourcing (write)
|
||||
|
||||
// offset(rounded 8) m-i i 16 offset
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// tdi -> | padded_bit | undefined | valid_write_data | header | bypass_bit |
|
||||
// +------------+-----------+------------------+--------+------------+
|
||||
// Data mode DR data stream write format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
if (offset == 'b0) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end else begin
|
||||
write_state <= ST_BYPASS;
|
||||
end
|
||||
// 8-bit bypass_bit_counter
|
||||
bypass_bit_counter <= offset;
|
||||
// 4-bit header_in_bit_counter
|
||||
header_in_bit_counter <= 15;
|
||||
// 3-bit write_data_bit_counter
|
||||
write_data_bit_counter <= 0;
|
||||
// Reset the registers
|
||||
// TODO: not necessarily all, reduce LE
|
||||
decode_header_1 <= 1'b0;
|
||||
decode_header_2 <= 1'b0;
|
||||
read_data_all_valid <= 1'b0;
|
||||
valid_write_data_length_byte_counter <= 0;
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// Discard bypass bits, then decode the 16-bit header
|
||||
// 3 3 10
|
||||
// +-------------------+------------------+-------------+
|
||||
// | write_data_length | read_data_length | scan_length |
|
||||
// +-------------------+------------------+-------------+
|
||||
// Header format
|
||||
|
||||
case (write_state)
|
||||
ST_BYPASS: begin
|
||||
// Discard the bypass bit
|
||||
bypass_bit_counter <= bypass_bit_counter - 1'b1;
|
||||
if (bypass_bit_counter == 1) begin
|
||||
write_state <= ST_HEADER_1;
|
||||
end
|
||||
end
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER_1: begin
|
||||
// TODO: header_in can be shorter
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
if (header_in_bit_counter == 3) begin
|
||||
read_data_length <= {tdi, header_in[15:14]};
|
||||
scan_length <= header_in[13:4];
|
||||
write_state <= ST_HEADER_2;
|
||||
decode_header_1 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the write_data_length
|
||||
ST_HEADER_2: begin
|
||||
// Shift into header_in
|
||||
header_in <= {tdi, header_in[15:1]};
|
||||
header_in_bit_counter <= header_in_bit_counter - 1'b1;
|
||||
// Decode read_data_length and scan_length
|
||||
if (decode_header_1) begin
|
||||
decode_header_1 <= 1'b0;
|
||||
// Set read_data_all_valid
|
||||
if (read_data_length == 3'b111) begin
|
||||
read_data_all_valid <= 1'b1;
|
||||
end
|
||||
// Load scan_length_byte_counter
|
||||
scan_length_byte_counter <= decoded_scan_length;
|
||||
end
|
||||
if (header_in_bit_counter == 0) begin
|
||||
write_data_length <= {tdi, header_in[15:14]};
|
||||
write_state <= ST_WRITE_DATA;
|
||||
decode_header_2 <= 1'b1;
|
||||
end
|
||||
end
|
||||
// Shift the valid_write_data
|
||||
ST_WRITE_DATA: begin
|
||||
// Shift into dr_data_in
|
||||
dr_data_in <= {tdi, dr_data_in[7:1]};
|
||||
// Decode write_data_length
|
||||
if (decode_header_2) begin
|
||||
decode_header_2 <= 1'b0;
|
||||
// Load valid_write_data_length_byte_counter
|
||||
case (write_data_length)
|
||||
3'b111: valid_write_data_length_byte_counter <= decoded_scan_length + 1'b1;
|
||||
3'b000: valid_write_data_length_byte_counter <= 'b0;
|
||||
default: valid_write_data_length_byte_counter <= decoded_write_data_length;
|
||||
endcase
|
||||
end
|
||||
write_data_bit_counter <= write_data_bit_counter - 1'b1;
|
||||
write_data_valid <= (valid_write_data_length_byte_counter != 0);
|
||||
// Feed the data to the idle remover
|
||||
if (write_data_byte_aligned && write_data_valid) begin
|
||||
valid_write_data_length_byte_counter <= valid_write_data_length_byte_counter - 1'b1;
|
||||
idle_remover_sink_valid <= 1'b1;
|
||||
idle_remover_sink_data <= {tdi, dr_data_in[7:1]};
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Data mode sinking (read)
|
||||
|
||||
// i m-i offset(rounded 8) 16
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// | valid_read_data | undefined | padded_bit | header | -> tdo
|
||||
// +-----------------+-----------+------------+--------+
|
||||
// Data mode DR data stream read format (as seen by hardware)
|
||||
//
|
||||
if (ir_in == DATA) begin
|
||||
|
||||
if (virtual_state_cdr) begin
|
||||
|
||||
read_state <= ST_HEADER;
|
||||
// Offset is rounded to nearest ceiling x8 to byte-align padded bits
|
||||
// 9-bit padded_bit_counter
|
||||
if (|offset[2:0]) begin
|
||||
padded_bit_counter[8:3] <= offset[7:3] + 1'b1;
|
||||
padded_bit_counter[2:0] <= 3'b0;
|
||||
end else begin
|
||||
padded_bit_counter <= {1'b0, offset};
|
||||
end
|
||||
// 4-bit header_out_bit_counter
|
||||
header_out_bit_counter <= 0;
|
||||
// 3-bit read_data_bit_counter
|
||||
read_data_bit_counter <= 0;
|
||||
// Load the data_available bit into header
|
||||
dr_data_out <= {{7{1'b0}}, data_available};
|
||||
read_data_valid <= 0;
|
||||
|
||||
end
|
||||
|
||||
if (virtual_state_sdr) begin
|
||||
// 10 1
|
||||
// +-----------------------------------+----------------+
|
||||
// | reserved | data_available |
|
||||
// +-----------------------------------+----------------+
|
||||
// Header format
|
||||
|
||||
dr_data_out <= {1'b0, dr_data_out[7:1]};
|
||||
case (read_state)
|
||||
// Shift the scan_length and read_data_length
|
||||
ST_HEADER: begin
|
||||
header_out_bit_counter <= header_out_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter for the next shift if no paddded bits
|
||||
if (header_out_bit_counter == 2) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
end
|
||||
if (header_out_bit_counter == 1) begin
|
||||
if (padded_bit_counter == 0) begin
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end else begin
|
||||
read_state <= ST_PADDED;
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
idle_inserter_source_ready <= 1'b0;
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
end
|
||||
end
|
||||
ST_PADDED: begin
|
||||
padded_bit_counter <= padded_bit_counter - 1'b1;
|
||||
if (padded_bit_byte_aligned) begin
|
||||
// Load idle character into data register
|
||||
dr_data_out <= 8'h4a;
|
||||
end
|
||||
// Retrieve data from idle inserter for the next shift when padded bits finish
|
||||
if (padded_bit_counter == 1) begin
|
||||
idle_inserter_source_ready <= read_data_all_valid;
|
||||
end
|
||||
if (padded_bit_counter == 0) begin // TODO: might make use of (padded_bit_counter[8:3]&padded_bit_byte_aligned)
|
||||
read_state <= ST_READ_DATA;
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
dr_data_out <= read_data_all_valid ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
ST_READ_DATA: begin
|
||||
read_data_bit_counter <= read_data_bit_counter - 1'b1;
|
||||
// Retrieve data from idle inserter just before read_data_byte_aligned
|
||||
if (read_data_bit_counter == 2) begin
|
||||
// Assert ready to retrieve data from idle inserter only when the bytestream has not ended,
|
||||
// data is valid (idle_inserter is always valid) and data is needed (read_data_valid)
|
||||
idle_inserter_source_ready <= bytestream_end ? 1'b0 : read_data_valid;
|
||||
end
|
||||
if (read_data_byte_aligned) begin
|
||||
// Note that bytestream_end is driven by scan_length_byte_counter
|
||||
if (~bytestream_end) begin
|
||||
scan_length_byte_counter <= scan_length_byte_counter - 1'b1;
|
||||
end
|
||||
read_data_valid <= read_data_all_valid || (scan_length_byte_counter<=decoded_read_data_length+1);
|
||||
// Load idle character if bytestream has ended, else get data from the idle inserter
|
||||
dr_data_out <= (read_data_valid & ~bytestream_end) ? idle_inserter_source_data : 8'h4a;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// Loopback mode
|
||||
if (ir_in == LOOPBACK) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_loopback <= 1'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_loopback
|
||||
dr_loopback <= tdi;
|
||||
end
|
||||
end
|
||||
|
||||
// Debug mode
|
||||
if (ir_in == DEBUG) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_debug <= {clock_sensor_sync, clock_to_sample_div2_sync, reset_to_sample_sync};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_debug <= {1'b0, dr_debug[2:1]}; // tdi is ignored
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
clock_sense_reset_n <= 1'b0;
|
||||
end else begin
|
||||
clock_sense_reset_n <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Info mode
|
||||
if (ir_in == INFO) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_info <= {PURPOSE[2:0], UPSTREAM_ENCODED_SIZE[3:0], DOWNSTREAM_ENCODED_SIZE[3:0]};
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_info
|
||||
dr_info <= {1'b0, dr_info[10:1]}; // tdi is ignored
|
||||
end
|
||||
end
|
||||
|
||||
// Control mode
|
||||
if (ir_in == CONTROL) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_control <= 'b0; // capture 0
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_control
|
||||
dr_control <= {tdi, dr_control[8:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
// Update resetrequest and offset
|
||||
{resetrequest, offset} <= dr_control;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @ * begin
|
||||
if (virtual_state_sdr) begin
|
||||
case (ir_in)
|
||||
DATA: tdo <= dr_data_out[0];
|
||||
LOOPBACK: tdo <= dr_loopback;
|
||||
DEBUG: tdo <= dr_debug[0];
|
||||
INFO: tdo <= dr_info[0];
|
||||
CONTROL: tdo <= dr_control[0];
|
||||
MGMT: tdo <= dr_mgmt[0];
|
||||
default: tdo <= 1'b0;
|
||||
endcase
|
||||
end else begin
|
||||
tdo <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Idle Remover
|
||||
altera_avalon_st_idle_remover idle_remover (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (), // left disconnected
|
||||
.in_valid (idle_remover_sink_valid),
|
||||
.in_data (idle_remover_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (1'b1), // downstream is expected to be always ready
|
||||
.out_valid (idle_remover_source_valid),
|
||||
.out_data (idle_remover_source_data)
|
||||
);
|
||||
|
||||
// Idle Inserter
|
||||
altera_avalon_st_idle_inserter idle_inserter (
|
||||
// Interface: clk
|
||||
.clk (tck),
|
||||
.reset_n (reset_n),
|
||||
|
||||
// Interface: ST in
|
||||
.in_ready (idle_inserter_sink_ready),
|
||||
.in_valid (idle_inserter_sink_valid),
|
||||
.in_data (idle_inserter_sink_data),
|
||||
|
||||
// Interface: ST out
|
||||
.out_ready (idle_inserter_source_ready),
|
||||
.out_valid (),
|
||||
.out_data (idle_inserter_source_data)
|
||||
);
|
||||
|
||||
generate
|
||||
if (MGMT_CHANNEL_WIDTH > 0)
|
||||
begin : has_mgmt
|
||||
reg [MGMT_CHANNEL_WIDTH+2:0] mgmt_out = 'b0;
|
||||
reg mgmt_toggle = 1'b0;
|
||||
wire mgmt_toggle_sync;
|
||||
reg mgmt_toggle_prev;
|
||||
wire mgmt_out_sync_ctl;
|
||||
|
||||
always @ (posedge tck) begin
|
||||
// Debug mode
|
||||
if (ir_in == MGMT) begin
|
||||
if (virtual_state_cdr) begin
|
||||
dr_mgmt <= 'b0;
|
||||
dr_mgmt[MGMT_CHANNEL_WIDTH+2] <= 1'b1;
|
||||
end
|
||||
if (virtual_state_sdr) begin
|
||||
// Shift dr_debug
|
||||
dr_mgmt <= {tdi, dr_mgmt[MGMT_CHANNEL_WIDTH+2:1]};
|
||||
end
|
||||
if (virtual_state_udr) begin
|
||||
mgmt_out <= dr_mgmt;
|
||||
mgmt_toggle <= mgmt_out[MGMT_CHANNEL_WIDTH+2] ? 1'b0 : ~mgmt_toggle;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) debug_reset_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_out[MGMT_CHANNEL_WIDTH+2]),
|
||||
.dout(debug_reset));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH_PLUS_ONE)) mgmt_toggle_synchronizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_toggle),
|
||||
.dout(mgmt_toggle_sync));
|
||||
|
||||
altera_std_synchronizer #(.depth(TCK_TO_SYSCLK_SYNC_DEPTH)) mgmt_out_synchornizer (
|
||||
.clk(clock_to_sample),
|
||||
.reset_n(1'b1),
|
||||
.din(mgmt_out[MGMT_CHANNEL_WIDTH+1]),
|
||||
.dout(mgmt_out_sync_ctl));
|
||||
|
||||
|
||||
|
||||
always @ (posedge clock_to_sample or posedge debug_reset) begin
|
||||
if (debug_reset) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_toggle_prev <= 1'b0;
|
||||
end else begin
|
||||
if ((mgmt_toggle_sync ^ mgmt_toggle_prev) && mgmt_out_sync_ctl) begin
|
||||
mgmt_valid <= 1'b1;
|
||||
mgmt_channel <= mgmt_out[MGMT_CHANNEL_WIDTH:1];
|
||||
mgmt_data <= mgmt_out[0];
|
||||
end else begin
|
||||
mgmt_valid <= 1'b0;
|
||||
end
|
||||
mgmt_toggle_prev <= mgmt_toggle_sync;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
begin : no_mgmt
|
||||
always @ (posedge tck) begin
|
||||
dr_mgmt[0] <= 1'b0;
|
||||
end
|
||||
assign debug_reset = 1'b0;
|
||||
always @ (posedge clock_to_sample) begin
|
||||
mgmt_valid <= 1'b0;
|
||||
mgmt_data <= 'b0;
|
||||
mgmt_channel <= 'b0;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43nch1THUj1J8wIocquwt/bKC/6wb5IrPaKQhLL4d9X7qOL25fim0OQ3w1e0kI9Su7SxOq7ZeSyLHj+thEW81l9l8AIIwYAnL8RErrsKah5+K4cM0jnu4Q57T7g5np938yAiAJHtcHjIGKM7kBQ8LOc/GvAIFGNaoWSAU+fzOm9T0zKuxhwPOFnvX/y2bCxbSGVw0YUtrKWi6k3DtxMHvxpI1B0A/PRseX5R/ZU0YsatatbrJ9bBer2Cgm95xnVbEsjyotNgilqeYUu/UgEby87pNGmOZd+Q8kTdNo6dBoHXXd3SQgzQZmNfyzZ0rudNzqJIG1q1YDtm3mMyQLIPhgneAjvB3l4HHHEdZaQW7QqQekZIxvqWjb6uCAKdfleuj/5tSASLRRKfjbS3tgmSR/vENA8bCbwBIQyPjO6a8sP/cVJJ1SY1UpSWi8lFdOA/YU8Y93mbIp3zqbCGvJX2uFvY9isn0VI71r0cYtq0LiKIv1+cEhjBsjHkjTHOSIfB45TxCawv4zFyTFlXFMeu1eSw+gKDrO3f944d/+fO5hb9awxgONZ1Qc8sdjDvw+JSnNwIvj+CZHWhF7k8EnUrGrA3id6ahcy5ss0wiZSNia7RwLg/y+hBdhnmCSMTdDFwXQ8UCndkIJi6mfsx3C+/NbHL7Mq1WOF/8+t0eBVEWrBrbtoiet15r/GMbZycW2wzHUUd5lW5CrMBdqVcOXKkS4nid4gZdeUdB5gifM6uvnL0hMwlftSdr1VbxBNE8EnzL5+Sbe7tRYnJrpPaI9v467AP"
|
||||
`endif
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43m3wnlehhyl/tvDkBTp1EtPpbSB7YBxMa/I8ZSI1dsWR/qcwyHhk27aoKzAbN2oGgXxnkwGf/9jPkx/jeL/VKbKIEY/78RjwxdNSCxTIRDJqQC4btrU936foYfcH4GIkOj1Pb8nFcEnnGY2UJoXMYcN51IJ1jy971+TxnUYP9B6ARYUmle9XtPoHHUKAYDS/tpju+pAaSva2iqW+gYvhSLYW1152f8xap7C5X60qVk8Bs11aIz0KJPZdF+f8bl9mwoAU39/rZQ6WcxvYEj1WnTK9f+aUGqcmmR+vUNBXXNN0C54sq0s5+6Nl8rpoXhs5VLdHpQr7Hat1GKzvMbNFmVBKP7BMC8ZPrGL63Oy6brcicq+7H7Ba23PxPyxRFJRiTAzutT9yIp3fNKDF8Mxfa18JediNCf2ZaBWrSnyppAn3tdQhF/5EzJyKO4hnV97MohBYYq5jOYf9FAlLGWdPlUgTCu3eUDmAhDMLjL1gJ3Ra4I6eUQfUcGeV3naPYko4wBX4pUYdx5CfIVAObW/RPsXGvLBU/6Ua16JjWk9+HRLtyu1oF+tSyHwHSe6GTbtVimKfBv+Z9iq9fw3/pchuMmvOQ0erCRAWsGe1gVpq3THnpq2rsWByBDOpaxfSLEyW/s5dLZy5F77rEz3L5gN6hPD1Ip/9hRQqCswu8HpGj2nu8SfFiMcD7SGKBiuaXTY5Cjib0cZWywM7PTWyZf2PACVBwRn7evdMFX0LLrqaC0VbIgjapuMBfJ9UfmsFIdeEDpIFZUwIkWqsKmeF1BIPe1C"
|
||||
`endif
|
||||
+267
@@ -0,0 +1,267 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
|
||||
// $Revision: #8 $
|
||||
// $Date: 2009/02/18 $
|
||||
// $Author: pscheidt $
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// File: altera_std_synchronizer_nocut.v
|
||||
//
|
||||
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
|
||||
// as altera_std_synchronizer.v, except that the embedded false
|
||||
// path constraint is removed in this module. If you use this
|
||||
// module, you will have to apply the appropriate timing
|
||||
// constraints.
|
||||
//
|
||||
// We expect to make this a standard Quartus atom eventually.
|
||||
//
|
||||
// Composed of two or more flip flops connected in series.
|
||||
// Random metastable condition is simulated when the
|
||||
// __ALTERA_STD__METASTABLE_SIM macro is defined.
|
||||
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
|
||||
// on the Verilog simulator compiler command line to
|
||||
// enable this mode. In addition, define the macro
|
||||
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
|
||||
// with every metastable event generated in the synchronizer.
|
||||
//
|
||||
// Copyright (C) Altera Corporation 2009, All Rights Reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_std_synchronizer_nocut (
|
||||
clk,
|
||||
reset_n,
|
||||
din,
|
||||
dout
|
||||
);
|
||||
|
||||
parameter depth = 3; // This value must be >= 2 !
|
||||
parameter rst_value = 0;
|
||||
|
||||
//when enabled, this will allow retiming for the sync depth >3.
|
||||
parameter retiming_reg_en = 0;
|
||||
|
||||
input clk;
|
||||
input reset_n;
|
||||
input din;
|
||||
output dout;
|
||||
|
||||
// QuartusII synthesis directives:
|
||||
// 1. Preserve all registers ie. do not touch them.
|
||||
// 2. Do not merge other flip-flops with synchronizer flip-flops.
|
||||
// QuartusII TimeQuest directives:
|
||||
// 1. Identify all flip-flops in this module as members of the synchronizer
|
||||
// to enable automatic metastability MTBF analysis.
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
|
||||
|
||||
//synthesis translate_off
|
||||
`ifndef QUARTUS_CDC
|
||||
initial begin
|
||||
if (retiming_reg_en == 0 ) begin
|
||||
if (depth <2) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (depth <4) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 4 with retiming enabled.", depth);
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
// the first synchronizer register is either a simple D flop for synthesis
|
||||
// and non-metastable simulation or a D flop with a method to inject random
|
||||
// metastable events resulting in random delay of [0,1] cycles
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM
|
||||
|
||||
reg[31:0] RANDOM_SEED = 123456;
|
||||
wire next_din_s1;
|
||||
wire dout;
|
||||
reg din_last;
|
||||
reg random;
|
||||
event metastable_event; // hook for debug monitoring
|
||||
|
||||
initial begin
|
||||
$display("%m: Info: Metastable event injection simulation mode enabled");
|
||||
random = $random;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset_n == 0)
|
||||
random <= $random(RANDOM_SEED);
|
||||
else
|
||||
random <= $random;
|
||||
end
|
||||
|
||||
assign next_din_s1 = (din_last ^ din) ? random : din;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_last <= din;
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_s1 <= next_din_s1;
|
||||
end
|
||||
|
||||
`else
|
||||
|
||||
//synthesis translate_on
|
||||
generate if (rst_value == 0)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b0;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (rst_value == 1)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b1;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
//synthesis translate_off
|
||||
|
||||
`endif
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
|
||||
always @(*) begin
|
||||
if (reset_n && (din_last != din) && (random != din)) begin
|
||||
$display("%m: Verbose Info: metastable event @ time %t", $time);
|
||||
->metastable_event;
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
//synthesis translate_on
|
||||
|
||||
// the remaining synchronizer registers form a simple shift register
|
||||
// of length depth-1
|
||||
generate if (rst_value == 0) begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin //This part is enabled when we set retiming_reg_en =1
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b0}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
else begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b1}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "YTu29eqC0KhfAXeRYUICwrAy8f9dNBV8Yu+dcGvIzwUfS9I5ptCmbZm2uCuZOPVBwtVKcWxCI/+NeoaHntIaySHYiXfBS0rjxyGQ1PvQXHCWij1r9uR37Xhl/QPx0bCXnHcqTISdKzkt8Ln8KkNYH7nrnMsVsPv0qdFfytVvHaZA2ymERVJWzYTBStzr1wFRdvdc4EFdV8tOn6e9D/1x/55lNPxUJFwXEnW21qrq43mCNPgtQr4hyUU4j86E903EvNfn1Ii/WXb12AEo64XSzinw4H9M64X3VrqZhPbCO8xw9VuZTidKsxxCiGMDNJFPc5y1BTrLcKFthIozfH+O4KS+/oVUEBy9vO4GOsJxaSxhKvtTgjz5HZCGqEVWWYErC33V9PybEQtP4jtcp/BoprsnJd8iwiVAgsTIGcopMmGgf84pOj3nOuhzeU8d7uS3dusa48HLsimnu0BhQMaLC4weSp1Kt/Up8x/ernjcbOKU1hpYaJ4Ujin7FtRELzaVB/EYUhMmzNw94lF0CD9pLiLXhAhE2Keh19nNOqWY1WDhkTvMYyVp7CBh3Dryo3df78teIPhp52/W2iSie+4uUmcM5fMbH8OxEAonWNr09vofAiynIGfHVpzGGj6ut3v2SLN2gEtbakpZAaFooskDYgGwsJRa9S2uVGkTs5Gsa8vKFHOs96TdG59fw54QNai04RRZs6VlOcKk4dVTr9WYthRGlandQHiCDG85hyUn9M6QRI5hA5vsf3xqBsiP7RrHqFZzoVWopikMJzkNCQxbcIqmp+Pp85b9szMI7qPO9knJD2ujGcuLRYMBaFNQtoGTzU+PhfLRHQEdH7lI63TRJpwDx41BBVljDGLpc4lBF4PBIEZ5LeeFzjMIY+Oy2asXd7c93WPJbmwZDcwvoO3ZH9CJefKH3y0z83QRTPgYlTp1Cpe6jtY3L0HNttlWFhj4b7rwi+SRJgWVdxPcc+WoE/0/gN4BxAYeAs4HJ2gfBLX/cP75eNMU/eXC/UlLFneB"
|
||||
`endif
|
||||
+44
@@ -0,0 +1,44 @@
|
||||
# (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and other
|
||||
# software and tools, and its AMPP partner logic functions, and any output
|
||||
# files from any of the foregoing (including device programming or simulation
|
||||
# files), and any associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License Subscription
|
||||
# Agreement, Altera IP License Agreement, or other applicable
|
||||
# license agreement, including, without limitation, that your use is for the
|
||||
# sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
|
||||
# +---------------------------------------------------
|
||||
# | Cut the async clear paths
|
||||
# +---------------------------------------------------
|
||||
set aclr_counter 0
|
||||
set clrn_counter 0
|
||||
if { [expr ![info exists show_hpath_of_all_reset_controller_inst]] } {
|
||||
set show_hpath_of_all_reset_controller_inst 0
|
||||
}
|
||||
if {[get_current_instance] == ""} {set hpath ""} else {set hpath "[get_current_instance]|*"}
|
||||
if {$show_hpath_of_all_reset_controller_inst == 1} {
|
||||
post_message -type info "Following instance found in the design - $hpath"
|
||||
}
|
||||
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
set num_sync_stage [get_registers -nocase -nowarn ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[*]]
|
||||
set num_sync_count [get_collection_size $num_sync_stage]
|
||||
set aclr_counter [get_collection_size $aclr_collection]
|
||||
set clrn_counter [get_collection_size $clrn_collection]
|
||||
|
||||
if {$aclr_counter == 0 && $clrn_counter == 0 && $num_sync_count > 0} {
|
||||
set_max_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] 100
|
||||
set_min_delay -to [get_registers ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[[expr $num_sync_count-1]]] -100
|
||||
}
|
||||
|
||||
if {$aclr_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
|
||||
}
|
||||
|
||||
if {$clrn_counter > 0} {
|
||||
set_false_path -to [get_pins -compatibility_mode -nocase ${hpath}alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
|
||||
}
|
||||
+367
@@ -0,0 +1,367 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_controller.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// --------------------------------------
|
||||
// Reset controller
|
||||
//
|
||||
// Combines all the input resets and synchronizes
|
||||
// the result to the clk.
|
||||
// ACDS13.1 - Added reset request as part of reset sequencing
|
||||
// --------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_controller
|
||||
#(
|
||||
parameter NUM_RESET_INPUTS = 6,
|
||||
parameter USE_RESET_REQUEST_IN0 = 0,
|
||||
parameter USE_RESET_REQUEST_IN1 = 0,
|
||||
parameter USE_RESET_REQUEST_IN2 = 0,
|
||||
parameter USE_RESET_REQUEST_IN3 = 0,
|
||||
parameter USE_RESET_REQUEST_IN4 = 0,
|
||||
parameter USE_RESET_REQUEST_IN5 = 0,
|
||||
parameter USE_RESET_REQUEST_IN6 = 0,
|
||||
parameter USE_RESET_REQUEST_IN7 = 0,
|
||||
parameter USE_RESET_REQUEST_IN8 = 0,
|
||||
parameter USE_RESET_REQUEST_IN9 = 0,
|
||||
parameter USE_RESET_REQUEST_IN10 = 0,
|
||||
parameter USE_RESET_REQUEST_IN11 = 0,
|
||||
parameter USE_RESET_REQUEST_IN12 = 0,
|
||||
parameter USE_RESET_REQUEST_IN13 = 0,
|
||||
parameter USE_RESET_REQUEST_IN14 = 0,
|
||||
parameter USE_RESET_REQUEST_IN15 = 0,
|
||||
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
|
||||
parameter SYNC_DEPTH = 2,
|
||||
parameter RESET_REQUEST_PRESENT = 0,
|
||||
parameter RESET_REQ_WAIT_TIME = 3,
|
||||
parameter MIN_RST_ASSERTION_TIME = 11,
|
||||
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
|
||||
parameter ADAPT_RESET_REQUEST = 0
|
||||
)
|
||||
(
|
||||
// --------------------------------------
|
||||
// We support up to 16 reset inputs, for now
|
||||
// --------------------------------------
|
||||
input reset_in0,
|
||||
input reset_in1,
|
||||
input reset_in2,
|
||||
input reset_in3,
|
||||
input reset_in4,
|
||||
input reset_in5,
|
||||
input reset_in6,
|
||||
input reset_in7,
|
||||
input reset_in8,
|
||||
input reset_in9,
|
||||
input reset_in10,
|
||||
input reset_in11,
|
||||
input reset_in12,
|
||||
input reset_in13,
|
||||
input reset_in14,
|
||||
input reset_in15,
|
||||
input reset_req_in0,
|
||||
input reset_req_in1,
|
||||
input reset_req_in2,
|
||||
input reset_req_in3,
|
||||
input reset_req_in4,
|
||||
input reset_req_in5,
|
||||
input reset_req_in6,
|
||||
input reset_req_in7,
|
||||
input reset_req_in8,
|
||||
input reset_req_in9,
|
||||
input reset_req_in10,
|
||||
input reset_req_in11,
|
||||
input reset_req_in12,
|
||||
input reset_req_in13,
|
||||
input reset_req_in14,
|
||||
input reset_req_in15,
|
||||
|
||||
|
||||
input clk,
|
||||
output reg reset_out,
|
||||
output reg reset_req
|
||||
);
|
||||
|
||||
// Always use async reset synchronizer if reset_req is used
|
||||
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
|
||||
|
||||
// --------------------------------------
|
||||
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
|
||||
// --------------------------------------
|
||||
localparam MIN_METASTABLE = 3;
|
||||
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
|
||||
|
||||
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
|
||||
|
||||
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
|
||||
MIN_RST_ASSERTION_TIME + 1 :
|
||||
(
|
||||
(MIN_RST_ASSERTION_TIME > LARGER)?
|
||||
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
|
||||
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
|
||||
);
|
||||
|
||||
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
|
||||
// --------------------------------------
|
||||
|
||||
wire merged_reset;
|
||||
wire merged_reset_req_in;
|
||||
wire reset_out_pre;
|
||||
reg reset_out_pre_reg;
|
||||
wire reset_req_pre;
|
||||
|
||||
// Registers and Interconnect
|
||||
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
|
||||
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
|
||||
reg r_sync_rst;
|
||||
reg r_early_rst;
|
||||
|
||||
// --------------------------------------
|
||||
// "Or" all the input resets together
|
||||
// --------------------------------------
|
||||
assign merged_reset = (
|
||||
reset_in0 |
|
||||
reset_in1 |
|
||||
reset_in2 |
|
||||
reset_in3 |
|
||||
reset_in4 |
|
||||
reset_in5 |
|
||||
reset_in6 |
|
||||
reset_in7 |
|
||||
reset_in8 |
|
||||
reset_in9 |
|
||||
reset_in10 |
|
||||
reset_in11 |
|
||||
reset_in12 |
|
||||
reset_in13 |
|
||||
reset_in14 |
|
||||
reset_in15
|
||||
);
|
||||
|
||||
assign merged_reset_req_in = (
|
||||
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
|
||||
);
|
||||
|
||||
|
||||
// --------------------------------------
|
||||
// And if required, synchronize it to the required clock domain,
|
||||
// with the correct synchronization type
|
||||
// --------------------------------------
|
||||
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
|
||||
|
||||
assign reset_out_pre = merged_reset;
|
||||
assign reset_req_pre = merged_reset_req_in;
|
||||
|
||||
end else begin
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
|
||||
)
|
||||
alt_rst_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset),
|
||||
.reset_out (reset_out_pre)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_req_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset_req_in),
|
||||
.reset_out (reset_req_pre)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
|
||||
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
|
||||
always @* begin
|
||||
reset_out = reset_out_pre;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
|
||||
|
||||
wire reset_out_pre2;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH+1),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_sync_uq2
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (reset_out_pre),
|
||||
.reset_out (reset_out_pre2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
reset_out = reset_out_pre2;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
// 3-FF Metastability Synchronizer
|
||||
//synthesis translate_off
|
||||
initial
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
|
||||
end
|
||||
|
||||
// Synchronous reset pipe
|
||||
initial
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
//synthesis translate_on
|
||||
|
||||
always @(posedge clk or posedge reset_out_pre)
|
||||
begin
|
||||
if (reset_out_pre)
|
||||
reset_out_pre_reg <= 1'h1;
|
||||
else
|
||||
reset_out_pre_reg <= reset_out_pre;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
|
||||
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre_reg};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
|
||||
end
|
||||
end
|
||||
|
||||
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
|
||||
// matches the early input.
|
||||
if (OUTPUT_RESET_SYNC_EDGES != "deassert" ) begin
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0; // Not reset
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1; // In Reset
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset_out_pre )
|
||||
begin
|
||||
if(reset_out_pre) begin
|
||||
r_early_rst <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0; // Not reset
|
||||
2'b01: r_early_rst <= 1'b1; // Coming out of reset
|
||||
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
|
||||
2'b11: r_early_rst <= 1'b1; // Held in reset
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @* begin
|
||||
reset_out = r_sync_rst;
|
||||
reset_req = r_early_rst;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZnnPJQ9GW+KzJV34fwWUvQ3dkA3L6G1Y5K7Msyidrmy1+Wu1L3OcWjX9FvtOw9qp2N3MEsh8d37Y/XaDWgwPKNC8qRv7AvhMJ8gFYwiLYTkPi1JGF8rlDOciOlSe0OOKsr8Qz81WHxnR038xpX6fIqkZWCweSvngUTKyauUaG3pcY+PLaI1oAcJ9eRym8kGs7+NwWcvmELdBMCucyRm52xLUprKDGjl1P42hAILSXrJXQndIyOW9vmm5Nz2evvj2gB7JvvzIfzZNuCdhnar89ChldW1j3A+Y5m6PjMM9pOU+Kdh26eGwj9fZZaPPrvl+VD5Hayq5zw3hzxXM33wd7ilCEvwS6rEk8Y9ZOslAUf74KejNArjekIHMmeFTx8aBtKMMm9wuP0WfEDxS4D7dDYDACm+FLX34qfxBjV7W/HokgwigFzSriqhaJqGkXLfN5+hTHkfsgDXx2KmN06gp1nCxVedTw83W3GZ0BDKFGGS0SrJDzge4q0Uk/lHtpo0n3W2FLL7TnG2r0QOY3YYnu0XSzCwIGa7WV4lIgGQ2UA+tiJkkVFL8zBqM6qqSx9ti08BQh/ob6g2E6CgPAuslJthgrG6/r1FvrY6mpyjO0c0vIAKswPchm+wB2Dx4+tBsnmX0peJXGJsrHXXjvrk52pzvpmXakJa2qerImbpknUXUBPR32Ek97/2wIEZ2iBp/jGeJDFttVPGoIXLHd4UgEdCmpFbUpZryi8bTJExus/YhIhp284WmXYOU22OgxwRtIPZ4CLG3lWeyiuxybU+R6eL"
|
||||
`endif
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/26.1/ip/iconnect/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2026/02/05 $
|
||||
|
||||
// -----------------------------------------------
|
||||
// Reset Synchronizer
|
||||
// -----------------------------------------------
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
// -----------------------------------------------
|
||||
// Synchronizer register chain. We cannot reuse the
|
||||
// standard synchronizer in this implementation
|
||||
// because our timing constraints are different.
|
||||
//
|
||||
// Instead of cutting the timing path to the d-input
|
||||
// on the first flop we need to cut the aclr input.
|
||||
//
|
||||
// We omit the "preserve" attribute on the final
|
||||
// output register, so that the synthesis tool can
|
||||
// duplicate it where needed.
|
||||
// -----------------------------------------------
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert asynchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
// -----------------------------------------------
|
||||
// Assert synchronously, deassert synchronously.
|
||||
// -----------------------------------------------
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "mfufSZOYfNPxmSfS+FkCl32e9bHGnpakqHX1nHXvrhE4J6x8qGVCEAJRqHIBXSp/FcyWPq9/UmljeMey51E9VTMH3OCNEvZdEUSPU4/Vf6DgtU26zIfR3Ws2AtmUBXEHD5yEeHuHpEMedz5PLIdzFsBxJ/9OiyM+8A3UVG3icM2FQlZPfaXli71zX1obNH4Hi4tyLUZvYQoJv7xSQMqW1lxant16XP5C2V2aZfTOCZm98qIL7ekOBsgi3Jk6JINlBn1MPss/MY/onstD48jcwiif8Gs4IWdQ2N3ArmvPwztGaa9pFUdrqFC/ySuZse43QXHTSLktppbb5RWP6kUriuoicmo6krAD1dbg/gJD2CPBniH3lvaXSbq4NXuXvaIi5JFjsHvqYH5AYGEBbEYIvX50OtmvM7MmdXWz8yMt/2x5MXTWbyba6bfKDJO6u5VlcHp85j3oXhLyoSx6ddNAgFJy9rjF3Z+u9E7PhkTCkebQtUzC8lIU9rG1+dwJE98atxbf1BPMRyiFcpFny635Ygt4p5jSQaXJnjSr6IUlFMLGpbYxPn1FcSkyMGPl2hZ7QtQENnQ3zejAwBl3Ze7ED8vOSzEBB93wGiKKZGd9hNwx5qeE0sgSNJa00qx6RLsg5tdDdzTo2bNXHlCtfYMIt2/YE75hzYCE//Zmb1mMx8nElfiU7/CpeYigjPvinVN5SqMGjIfMFWJasqdSm9Kw1UAN9s0LK8S6K3T1TGkHThOkJWDfpad7wvhxSkVJ99h9FdBLMlmkBYEwI/u/MKtNrzgKPsLz1FZ5EHB/JZti7aWbfhXQS1FoZYSLodk3NCTCmYgyghebDnmxCjIcHta/kmoyhMwLpM8ogUx6J3QA9oOxI+AvWy9A+id8Pj2XJjjQZxXzlg9JOVaXvn88zi6LVC88csY6kT+ANYw3OMfSjw9C2F6wme2VCibcI+DhqZCNXC41h1m9pqNYMUyyrBy5GMRZpEvb5yXb0+fS85rTPw4BgZkbkOxcmoA92mjOky5L"
|
||||
`endif
|
||||
+98
@@ -0,0 +1,98 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_5vp3d5a
|
||||
// in_channel_width: 0
|
||||
// in_max_channel: 0
|
||||
// out_channel_width: 8
|
||||
// out_max_channel: 255
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
// altera message_off 13469
|
||||
|
||||
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_5vp3d5a
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg [8-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
wire in_channel;
|
||||
assign in_channel =0 ;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = 0;
|
||||
out_channel = in_channel;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+101
@@ -0,0 +1,101 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// (C) 2001-2013 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
// $Id: //acds/rel/13.1/ip/.../avalon-st_channel_adapter.sv.terp#1 $
|
||||
// $Revision: #1 $
|
||||
// $Date: 2013/09/09 $
|
||||
// $Author: dmunday $
|
||||
|
||||
// --------------------------------------------------------------------------------
|
||||
//| Avalon Streaming Channel Adapter
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
// ------------------------------------------
|
||||
// Generation parameters:
|
||||
// output_name: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_rd56ufy
|
||||
// in_channel_width: 8
|
||||
// in_max_channel: 255
|
||||
// out_channel_width: 0
|
||||
// out_max_channel: 0
|
||||
// data_width: 8
|
||||
// error_width: 0
|
||||
// use_ready: true
|
||||
// use_packets: true
|
||||
// use_empty: 0
|
||||
// empty_width: 0
|
||||
|
||||
// ------------------------------------------
|
||||
|
||||
// altera message_off 13469
|
||||
|
||||
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_rd56ufy
|
||||
(
|
||||
// Interface: in
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [8-1: 0] in_data,
|
||||
input [8-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
// Interface: out
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [8-1: 0] out_data,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
// Interface: clk
|
||||
input clk,
|
||||
// Interface: reset
|
||||
input reset_n
|
||||
|
||||
|
||||
);
|
||||
|
||||
reg out_channel;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
//| Payload Mapping
|
||||
// ---------------------------------------------------------------------
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = in_valid;
|
||||
out_data = in_data;
|
||||
out_startofpacket = in_startofpacket;
|
||||
out_endofpacket = in_endofpacket;
|
||||
|
||||
out_channel = in_channel; //TODO delete this to avoid Quartus warnings
|
||||
|
||||
// Suppress channels that are higher than the destination's max_channel.
|
||||
if (in_channel > 0) begin
|
||||
out_valid = 0;
|
||||
// Simulation Message goes here.
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+310
@@ -0,0 +1,310 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This module implements the gearbox logic to compress the number of wire
|
||||
// connections to the IOSSM debug port.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module altera_emif_cal_gearbox
|
||||
#(parameter AXI_ADDR_WIDTH = 20,
|
||||
parameter AXI_DATA_WIDTH = 32)
|
||||
(
|
||||
|
||||
// AXI-Lite User Interface
|
||||
input logic axi_clk,
|
||||
input logic axi_rst_n,
|
||||
|
||||
input logic axi_awvalid,
|
||||
output logic axi_awready,
|
||||
input logic [AXI_ADDR_WIDTH-1:0] axi_awaddr,
|
||||
|
||||
input logic axi_arvalid,
|
||||
output logic axi_arready,
|
||||
input logic [AXI_ADDR_WIDTH-1:0] axi_araddr,
|
||||
|
||||
input logic axi_wvalid,
|
||||
output logic axi_wready,
|
||||
input logic [AXI_DATA_WIDTH-1:0] axi_wdata,
|
||||
|
||||
output logic axi_rvalid,
|
||||
input logic axi_rready,
|
||||
output logic [ 1:0] axi_rresp,
|
||||
output logic [AXI_DATA_WIDTH-1:0] axi_rdata,
|
||||
|
||||
output logic axi_bvalid,
|
||||
input logic axi_bready,
|
||||
output logic [ 1:0] axi_bresp,
|
||||
|
||||
// IOSSM C2P/P2C Interface
|
||||
output logic [5:0] ssm_c2p,
|
||||
input logic [4:0] ssm_p2c
|
||||
);
|
||||
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
|
||||
logic clk, rst_n;
|
||||
|
||||
assign clk = axi_clk;
|
||||
assign rst_n = axi_rst_n;
|
||||
|
||||
logic f2c_addr_valid, f2c_data_valid;
|
||||
logic [7:0][3:0] f2c_addr , f2c_data ;
|
||||
(* preserve *) logic [3:0] f2c_pkt;
|
||||
(* preserve *) logic f2c_pkt_valid;
|
||||
logic [7:0][3:0] f2c_rdata ;
|
||||
logic [1:0] f2c_rresp ;
|
||||
logic f2c_rvalid;
|
||||
logic axi_grant_read;
|
||||
logic [4:0] prev_ssm_p2c;
|
||||
|
||||
typedef enum bit [3:0] {
|
||||
F2C_CMD_WRITE=0,
|
||||
F2C_CMD_READ=1,
|
||||
F2C_CMD_ACK=2
|
||||
} f2c_cmd_t;
|
||||
f2c_cmd_t f2c_cmd;
|
||||
|
||||
typedef enum bit [4:0] {
|
||||
F2C_IDLE,
|
||||
F2C_CMD,
|
||||
F2C_A[8],
|
||||
F2C_D[8],
|
||||
F2C_WAIT,
|
||||
F2C_CLEAR
|
||||
} f2c_state_t;
|
||||
f2c_state_t f2c_state;
|
||||
|
||||
assign ssm_c2p[4] = f2c_pkt_valid;
|
||||
assign ssm_c2p[3:0] = f2c_pkt;
|
||||
|
||||
//////////////////////////////////////////////////////////////////
|
||||
// RESPONSE PATH
|
||||
//////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// For read response, we need to accumulate all the 8slices (of 4bits each) to a 32-bit rdata.
|
||||
// rctr: read-counter keeps a track of which slice is being recvd.
|
||||
//
|
||||
// For write response, its sent ut in the same cycle.
|
||||
//
|
||||
assign axi_rvalid = f2c_rvalid;
|
||||
assign axi_rdata = f2c_rdata;
|
||||
assign axi_rresp = f2c_rresp;
|
||||
assign axi_bvalid = ssm_p2c[4] && ssm_p2c[3:0] == F2C_CMD_ACK && (!prev_ssm_p2c);
|
||||
assign axi_bresp = 2'b0;
|
||||
logic [2:0] rctr;
|
||||
logic rctr_en;
|
||||
always @(posedge clk, negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
f2c_rresp <= '0;
|
||||
f2c_rdata <= '0;
|
||||
end else begin
|
||||
if (!rctr_en) f2c_rresp <= (ssm_p2c[4] && ssm_p2c[2]) ? ssm_p2c[1:0] : '0;
|
||||
if (rctr_en) f2c_rdata[7-rctr] <= ssm_p2c[3:0];
|
||||
end
|
||||
end
|
||||
always @(posedge clk, negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
rctr <= '0;
|
||||
rctr_en <= '0;
|
||||
end else begin
|
||||
rctr <= rctr_en? rctr + 1'b1 : rctr;
|
||||
if (ssm_p2c[4] && ssm_p2c[2] && rctr_en == 0 && !prev_ssm_p2c) begin
|
||||
rctr_en <= 1'b1;
|
||||
end else if (rctr_en==1 && &rctr) begin
|
||||
rctr_en <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk, negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
f2c_rvalid <= '0;
|
||||
end else begin
|
||||
if(!f2c_rvalid) begin
|
||||
f2c_rvalid <= &rctr;
|
||||
end
|
||||
else begin
|
||||
if(axi_rready || (ssm_p2c[4] && ssm_p2c[2] && rctr_en == 0 && !prev_ssm_p2c))
|
||||
f2c_rvalid <= '0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff@(posedge clk, negedge rst_n)begin
|
||||
if(!rst_n) begin
|
||||
prev_ssm_p2c <= 5'b11111;
|
||||
end else begin
|
||||
prev_ssm_p2c <= ssm_p2c;
|
||||
end
|
||||
end
|
||||
|
||||
//////////////////////////////////////////////////////////////////
|
||||
// COMMAND/WDATA PATH
|
||||
//////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// f2c_state
|
||||
//
|
||||
// IDLE -> CMD -> A0 -> A1 -> .... A7 ---> D0 -> D1 -> .... D7 ----> CLEAR -> IDLE
|
||||
// | |
|
||||
// v ^
|
||||
// | |
|
||||
// --------------->-----------
|
||||
// if cmd =read
|
||||
// For read request ->
|
||||
// required: a handshake on AR-channel
|
||||
// to send : CMD=1 (READ), followed by ADDR slices
|
||||
// control : f2c_state FSM controls sending out 4-bit slice at a time.
|
||||
// It jumps to CLEAR state after state A_7
|
||||
//
|
||||
// For write request,
|
||||
// required: a handshake on AW-channel and W-channel
|
||||
// to send : CMD=1 (READ), followed by ADDR slices and DATA slices
|
||||
// control : f2c_state FSM controls sending out 4-bit slice at a time.
|
||||
//
|
||||
|
||||
// If either AR/AW, then grant that.
|
||||
// If both AR/AW, then arbitrate
|
||||
assign axi_awready = !f2c_addr_valid && (!axi_arvalid || !axi_grant_read);
|
||||
assign axi_arready = !f2c_addr_valid && (!axi_awvalid || axi_grant_read);
|
||||
assign axi_wready = !f2c_data_valid;
|
||||
|
||||
// Arbitration between AR/AW
|
||||
always @(posedge clk, negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
axi_grant_read <= 1'b1;
|
||||
end else begin
|
||||
case (1)
|
||||
(axi_arvalid && axi_arready): axi_grant_read <= 1'b0; // Just allowed a read, next time prioritize write
|
||||
(axi_awvalid && axi_awready): axi_grant_read <= 1'b1; // Just allowed a write, next time prioritize read
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Store AXI (Addr/WData) signals, deassert axready/wready, if these storages are full.
|
||||
always @(posedge clk, negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
{f2c_addr_valid,f2c_addr} <= '0;
|
||||
{f2c_data_valid,f2c_data} <= '0;
|
||||
f2c_cmd <= F2C_CMD_WRITE;
|
||||
end else begin
|
||||
if (axi_arvalid && axi_arready) begin
|
||||
f2c_addr_valid <= 1'b1;
|
||||
f2c_addr <= 32'(axi_araddr);
|
||||
f2c_cmd <= F2C_CMD_READ;
|
||||
end else if (axi_awvalid && axi_awready) begin
|
||||
f2c_addr_valid <= 1'b1;
|
||||
f2c_addr <= 32'(axi_awaddr);
|
||||
f2c_cmd <= F2C_CMD_WRITE;
|
||||
end else if (f2c_state == F2C_CLEAR) begin
|
||||
f2c_addr_valid <= 1'b0;
|
||||
end
|
||||
if (axi_wvalid && axi_wready) begin
|
||||
f2c_data_valid <= 1'b1;
|
||||
f2c_data <= 32'(axi_wdata);
|
||||
end else if (f2c_state == F2C_CLEAR && f2c_cmd == F2C_CMD_WRITE) begin // A stored write data can only proceed with wr command
|
||||
f2c_data_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// F2C State Machine
|
||||
always @(posedge clk, negedge rst_n) begin
|
||||
|
||||
if (!rst_n) begin
|
||||
f2c_state <= F2C_IDLE;
|
||||
f2c_pkt <= '0;
|
||||
f2c_pkt_valid <= '0;
|
||||
|
||||
end else begin
|
||||
|
||||
case (f2c_state)
|
||||
|
||||
F2C_IDLE: begin
|
||||
if ((f2c_addr_valid && f2c_cmd==F2C_CMD_READ) || (f2c_addr_valid && f2c_data_valid)) begin
|
||||
f2c_state <= F2C_CMD;
|
||||
f2c_pkt <= f2c_cmd;
|
||||
f2c_pkt_valid <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
F2C_CMD: begin
|
||||
f2c_state <= F2C_A0;
|
||||
f2c_pkt <= f2c_addr[7];
|
||||
f2c_pkt_valid <= 1'b1;
|
||||
end
|
||||
|
||||
F2C_A0, F2C_A1, F2C_A2, F2C_A3, F2C_A4, F2C_A5, F2C_A6 : begin
|
||||
f2c_state <= f2c_state.next();
|
||||
f2c_pkt <= f2c_addr[7-(f2c_state-F2C_A0+1)];
|
||||
f2c_pkt_valid <= 1'b1;
|
||||
end
|
||||
|
||||
F2C_A7 : begin
|
||||
if (f2c_cmd == F2C_CMD_READ) begin
|
||||
f2c_state <= F2C_WAIT;
|
||||
f2c_pkt_valid <= 1'b0;
|
||||
f2c_pkt <= 4'b0;
|
||||
end else begin
|
||||
f2c_state <= F2C_D0;
|
||||
f2c_pkt_valid <= 1'b1;
|
||||
f2c_pkt <= f2c_data[7];
|
||||
end
|
||||
end
|
||||
|
||||
F2C_D0, F2C_D1, F2C_D2, F2C_D3, F2C_D4, F2C_D5, F2C_D6 : begin
|
||||
f2c_state <= f2c_state.next();
|
||||
f2c_pkt <= f2c_data[7-(f2c_state-F2C_D0+1)];
|
||||
f2c_pkt_valid <= 1'b1;
|
||||
end
|
||||
|
||||
F2C_D7 : begin
|
||||
f2c_state <= F2C_WAIT;
|
||||
f2c_pkt <= 4'b0;
|
||||
f2c_pkt_valid <= 1'b0;
|
||||
end
|
||||
|
||||
F2C_WAIT: begin
|
||||
if (f2c_rvalid || (ssm_p2c[4] && ssm_p2c[3:0] == F2C_CMD_ACK && (!prev_ssm_p2c))) begin
|
||||
f2c_state <= F2C_CLEAR;
|
||||
end else begin
|
||||
f2c_state <= F2C_WAIT;
|
||||
end
|
||||
end
|
||||
|
||||
F2C_CLEAR: begin
|
||||
f2c_state <= F2C_IDLE;
|
||||
end
|
||||
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
/*TODO
|
||||
* Assertions
|
||||
* This gearbx assumes a strict sequence. Add assertions, for the sequence.
|
||||
* Timeout?
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9zweH2gxIGgmFZi29uVbqDKevJN81vtV7b0MY+SdPO1/GwvenIhGj4zasJZZtDGJOV69mQDOzJfFPcAL9b/CLFeaM+rd7cZiZnMU25Sq6K+hgurf42ZUd4OD215FVvc8n9jSg0avPeXkpjZw0w0egMkKuWdErj36EVzvoZjpsBHf+bBb7ZXrmo5OtLof/jTX+dsaQBjKEA3CpZapj9DD/5kbtlaikRxuaRyl8TEKydIDKAkVK3U/+49DJinyc5OO7lFQ/u61nDceyKDMp+EpvuDfy5vVMt1hB3xT09atmkMTDw1HVrdpzK/w1bgM0ep9ABZz27vOsYJ5rw5U/RpfCdf1uqfNIlLRoNdXAbihsoQb5X2kGeo8HUibTZI1k5N98zkmncp1/DQazCa9s+0xLEd63hNsmlDrmL12lCNPABmn6AUgppAyKfOSYn5hutIjSNEqsOVQpZPrbw9TZl82k0g+Yvz4xDyEIA+41o1nnh9BUEnTziDsDck7dtXLHYWWD2m8tj4t7Gwfaiwr7r3pDLQnx+XN/RhYofd8t4ddRwEPcqVp4btQwqBAb2vXxaSEySdUBQXyWYjWWP5S7pwuqzet7E6jm0vIHbUI9qkMDCg8WG2m9w+1i2AG+T0J+R1vDRKBioAd2iXTds59phkbV9kstMYB83BapCuiOjGDYO7uX99MSes0rZlZ4HJdSfBdliKveRdF3yBDtVfV3kDxZt3+o7p6xUgAxn81Fp4+NI3I2DzCqC4uyXOFDJsPNw7IDtc1eOe6uSJozFInIKSDjp"
|
||||
`endif
|
||||
+1306
File diff suppressed because it is too large
Load Diff
+126
@@ -0,0 +1,126 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
`ifndef CAL_ARCH_FP_INTERFACE
|
||||
|
||||
`define CAL_ARCH_FP_INTERFACE 1
|
||||
|
||||
// altera message_off 18455
|
||||
interface AXILITE_BUS #(
|
||||
parameter int signed PORT_AXI_AXADDR_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXID_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXBURST_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXLEN_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXSIZE_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXUSER_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_DATA_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_STRB_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_RESP_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_ID_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_USER_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXQOS_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXCACHE_WIDTH = 0,
|
||||
parameter int signed PORT_AXI_AXPROT_WIDTH = 0
|
||||
);
|
||||
|
||||
typedef logic clk_t;
|
||||
typedef logic rst_n_t;
|
||||
typedef logic [PORT_AXI_AXADDR_WIDTH-1:0] addr_t;
|
||||
typedef logic [PORT_AXI_AXID_WIDTH-1:0] id_t;
|
||||
typedef logic [PORT_AXI_AXBURST_WIDTH-1:0] burst_t;
|
||||
typedef logic [PORT_AXI_AXLEN_WIDTH-1:0] len_t;
|
||||
typedef logic [PORT_AXI_AXSIZE_WIDTH-1:0] size_t;
|
||||
typedef logic [PORT_AXI_AXUSER_WIDTH-1:0] user_t;
|
||||
typedef logic [PORT_AXI_DATA_WIDTH-1:0] data_t;
|
||||
typedef logic [PORT_AXI_STRB_WIDTH-1:0] strb_t;
|
||||
typedef logic [PORT_AXI_RESP_WIDTH-1:0] resp_t;
|
||||
typedef logic [PORT_AXI_ID_WIDTH-1:0] respid_t;
|
||||
typedef logic [PORT_AXI_USER_WIDTH-1:0] respuser_t;
|
||||
typedef logic [PORT_AXI_AXQOS_WIDTH-1:0] qos_t;
|
||||
typedef logic [PORT_AXI_AXCACHE_WIDTH-1:0] cache_t;
|
||||
typedef logic [PORT_AXI_AXPROT_WIDTH-1:0] prot_t;
|
||||
|
||||
clk_t clk;
|
||||
rst_n_t rst_n;
|
||||
|
||||
id_t awid;
|
||||
addr_t awaddr;
|
||||
len_t awlen;
|
||||
size_t awsize;
|
||||
burst_t awburst;
|
||||
logic awlock;
|
||||
cache_t awcache;
|
||||
prot_t awprot;
|
||||
qos_t awqos;
|
||||
user_t awuser;
|
||||
logic awvalid;
|
||||
logic awready;
|
||||
|
||||
data_t wdata;
|
||||
strb_t wstrb;
|
||||
logic wlast;
|
||||
respuser_t wuser;
|
||||
logic wvalid;
|
||||
logic wready;
|
||||
|
||||
respid_t bid;
|
||||
resp_t bresp;
|
||||
respuser_t buser;
|
||||
logic bvalid;
|
||||
logic bready;
|
||||
|
||||
id_t arid;
|
||||
addr_t araddr;
|
||||
len_t arlen;
|
||||
size_t arsize;
|
||||
burst_t arburst;
|
||||
logic arlock;
|
||||
cache_t arcache;
|
||||
prot_t arprot;
|
||||
qos_t arqos;
|
||||
user_t aruser;
|
||||
logic arvalid;
|
||||
logic arready;
|
||||
|
||||
respid_t rid;
|
||||
data_t rdata;
|
||||
resp_t rresp;
|
||||
logic rlast;
|
||||
respuser_t ruser;
|
||||
logic rvalid;
|
||||
logic rready;
|
||||
|
||||
modport Manager (
|
||||
input clk, rst_n,
|
||||
output awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot, awqos, awuser, awvalid, input awready,
|
||||
output wdata, wstrb, wlast, wuser, wvalid, input wready,
|
||||
input bid, bresp, buser, bvalid, output bready,
|
||||
output arid, araddr, arlen, arsize, arburst, arlock, arcache, arprot, arqos, aruser, arvalid, input arready,
|
||||
input rid, rdata, rresp, rlast, ruser, rvalid, output rready
|
||||
);
|
||||
|
||||
modport Subordinate (
|
||||
output clk, rst_n,
|
||||
input awid, awaddr, awlen, awsize, awburst, awlock, awcache, awprot, awqos, awuser, awvalid, output awready,
|
||||
input wdata, wstrb, wlast, wuser, wvalid, output wready,
|
||||
output bid, bresp, buser, bvalid, input bready,
|
||||
input arid, araddr, arlen, arsize, arburst, arlock, arcache, arprot, arqos, aruser, arvalid, output arready,
|
||||
output rid, rdata, rresp, rlast, ruser, rvalid, input rready
|
||||
);
|
||||
|
||||
endinterface
|
||||
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc/6W5Qqny2fCpOXVQOmvpsKmiFg4va0lrgifHmeSzL+wii+GRD85d+GbHVAlHqpsfMSYa9G5MNXPbbxMD/ORiMV5hHv1H53UlqtQsAXtD8FNvzs25I6qXn+G+U09+bkudZYbCMfGOt6YEtXIfmbUVzxcAMKNl4cvl+ciGu0IIOolx7/2O93XVd1vpwYOIWlYz9JU3pHhtv6SJc1TpIaTMs5M5/lIjbCLLcTZvBvN1mwzvYp7AK1mFlfW/XJPIrWIBrgudTUjHn0QqGD9tkSOVVgQ8KpwU3YRpfmKcJ93XDv0G2jGLInN8X48nIhAJ/K+ez0q+lbifHxxL9OZKUZWHYz0pf4DdkGLGs9rp7tOdrTuL3MZWpWpOB1daeV+mGl9wjxc+VXy4xZwG/TjAXZw+W2DRRkdUB6M/EDExWWCaAyekzmYrdrvlYiZZSnbXQ5GSSpXbgJzTpLHCAxiP7Oo1rE3Umpy5qc9mFoiwwde81H89WF0MScHgr4O3S8D4dQyMvFM7p1+pDLPnGWPHg6EZWPGFnTgBbsTXiBAvDyV2JazzKZKhpui4JbWtHy+SfPVGoylh06gT9ByVTxKg7c0VOPs/3HhUI6G+6X0qoNiClTr4QOjx7YQe+aP6PDOQARoYjIdf2hXtbFHKwucSRpSdiM42MzOyXCd6h1iw12Xs3YtWYklbVoGv+w0IOodJd1gtgPcSWTf1OmRGARutIZGCiad7SX1pzNJTgVIgJ/pL55WQBtbW7eyDC/aXzxHmeHfyZJ/sgVSXG35FLbFxKJNibv"
|
||||
`endif
|
||||
+536
File diff suppressed because one or more lines are too long
+369
@@ -0,0 +1,369 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
// altera message_off 24541 13469
|
||||
module io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_arbitrator #(
|
||||
AMM_TO_AXIL_INTERCONNECT_ONLY = ""
|
||||
) (
|
||||
|
||||
input s0_axi4lite_clk,
|
||||
input s0_axi4lite_rst_n,
|
||||
|
||||
input [26:0] s0_axi4lite_awaddr,
|
||||
input [2:0] s0_axi4lite_awprot,
|
||||
input s0_axi4lite_awvalid,
|
||||
output s0_axi4lite_awready,
|
||||
input [31:0] s0_axi4lite_wdata,
|
||||
input [3:0] s0_axi4lite_wstrb,
|
||||
input s0_axi4lite_wvalid,
|
||||
output s0_axi4lite_wready,
|
||||
output [1:0] s0_axi4lite_bresp,
|
||||
output s0_axi4lite_bvalid,
|
||||
input s0_axi4lite_bready,
|
||||
input [26:0] s0_axi4lite_araddr,
|
||||
input [2:0] s0_axi4lite_arprot,
|
||||
input s0_axi4lite_arvalid,
|
||||
output s0_axi4lite_arready,
|
||||
output [31:0] s0_axi4lite_rdata,
|
||||
output [1:0] s0_axi4lite_rresp,
|
||||
output s0_axi4lite_rvalid,
|
||||
input s0_axi4lite_rready,
|
||||
|
||||
input [31:0] jamb_master_address,
|
||||
output [31:0] jamb_master_readdata,
|
||||
input jamb_master_read,
|
||||
input jamb_master_write,
|
||||
input [31:0] jamb_master_writedata,
|
||||
output jamb_master_waitrequest,
|
||||
output jamb_master_readdatavalid,
|
||||
input [3:0] jamb_master_byteenable,
|
||||
|
||||
output [26:0] cal_arch_0_s0_axi4lite_axi4_lite_awaddr,
|
||||
output [2:0] cal_arch_0_s0_axi4lite_axi4_lite_awprot,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_awvalid,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_awready,
|
||||
output [31:0] cal_arch_0_s0_axi4lite_axi4_lite_wdata,
|
||||
output [3:0] cal_arch_0_s0_axi4lite_axi4_lite_wstrb,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_wvalid,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_wready,
|
||||
input [1:0] cal_arch_0_s0_axi4lite_axi4_lite_bresp,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_bvalid,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_bready,
|
||||
output [26:0] cal_arch_0_s0_axi4lite_axi4_lite_araddr,
|
||||
output [2:0] cal_arch_0_s0_axi4lite_axi4_lite_arprot,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_arvalid,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_arready,
|
||||
input [31:0] cal_arch_0_s0_axi4lite_axi4_lite_rdata,
|
||||
input [1:0] cal_arch_0_s0_axi4lite_axi4_lite_rresp,
|
||||
input cal_arch_0_s0_axi4lite_axi4_lite_rvalid,
|
||||
output cal_arch_0_s0_axi4lite_axi4_lite_rready
|
||||
|
||||
);
|
||||
|
||||
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_awaddr;
|
||||
wire [1:0] mm_interconnect_0_arbit_s0_axi4lite_bresp;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_arready;
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_rdata;
|
||||
wire [3:0] mm_interconnect_0_arbit_s0_axi4lite_wstrb;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_wready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_awready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_rready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_bready;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_wvalid;
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_araddr;
|
||||
wire [2:0] mm_interconnect_0_arbit_s0_axi4lite_arprot;
|
||||
wire [1:0] mm_interconnect_0_arbit_s0_axi4lite_rresp;
|
||||
wire [2:0] mm_interconnect_0_arbit_s0_axi4lite_awprot;
|
||||
wire [31:0] mm_interconnect_0_arbit_s0_axi4lite_wdata;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_arvalid;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_bvalid;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_awvalid;
|
||||
wire mm_interconnect_0_arbit_s0_axi4lite_rvalid;
|
||||
wire [31:0] arbit_m_axi4_ruser;
|
||||
wire [31:0] arbit_m_axi4_wuser;
|
||||
wire [1:0] arbit_m_axi4_awburst;
|
||||
wire [7:0] arbit_m_axi4_arlen;
|
||||
wire [3:0] arbit_m_axi4_arqos;
|
||||
wire [10:0] arbit_m_axi4_awuser;
|
||||
wire [31:0] arbit_m_axi4_wstrb;
|
||||
wire arbit_m_axi4_wready;
|
||||
wire [6:0] arbit_m_axi4_rid;
|
||||
wire arbit_m_axi4_rready;
|
||||
wire [7:0] arbit_m_axi4_awlen;
|
||||
wire [3:0] arbit_m_axi4_awqos;
|
||||
wire [31:0] arbit_m_axi4_araddr;
|
||||
wire arbit_m_axi4_wvalid;
|
||||
wire [2:0] arbit_m_axi4_arprot;
|
||||
wire arbit_m_axi4_arvalid;
|
||||
wire [2:0] arbit_m_axi4_awprot;
|
||||
wire [255:0] arbit_m_axi4_wdata;
|
||||
wire [6:0] arbit_m_axi4_arid;
|
||||
wire arbit_m_axi4_arlock;
|
||||
wire arbit_m_axi4_awlock;
|
||||
wire [31:0] arbit_m_axi4_awaddr;
|
||||
wire arbit_m_axi4_arready;
|
||||
wire [1:0] arbit_m_axi4_bresp;
|
||||
wire [255:0] arbit_m_axi4_rdata;
|
||||
wire [1:0] arbit_m_axi4_arburst;
|
||||
wire arbit_m_axi4_awready;
|
||||
wire [2:0] arbit_m_axi4_arsize;
|
||||
wire arbit_m_axi4_rlast;
|
||||
wire arbit_m_axi4_bready;
|
||||
wire arbit_m_axi4_wlast;
|
||||
wire [1:0] arbit_m_axi4_rresp;
|
||||
wire [6:0] arbit_m_axi4_awid;
|
||||
wire [6:0] arbit_m_axi4_bid;
|
||||
wire arbit_m_axi4_bvalid;
|
||||
wire [10:0] arbit_m_axi4_aruser;
|
||||
wire arbit_m_axi4_rvalid;
|
||||
wire [2:0] arbit_m_axi4_awsize;
|
||||
wire arbit_m_axi4_awvalid;
|
||||
|
||||
altera_reset_synchronizer #(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(0)
|
||||
) reset_sync (
|
||||
.clk (s0_axi4lite_clk),
|
||||
.reset_in (~s0_axi4lite_rst_n),
|
||||
.reset_out (s0_axi4lite_rst_sync)
|
||||
);
|
||||
|
||||
ed_synth_dut_altera_mm_interconnect_1920_jmzr6ly mm_interconnect_0 (
|
||||
.jamb_master_address (jamb_master_address),
|
||||
.jamb_master_waitrequest (jamb_master_waitrequest),
|
||||
.jamb_master_byteenable (jamb_master_byteenable),
|
||||
.jamb_master_read (jamb_master_read),
|
||||
.jamb_master_readdata (jamb_master_readdata),
|
||||
.jamb_master_readdatavalid (jamb_master_readdatavalid),
|
||||
.jamb_master_write (jamb_master_write),
|
||||
.jamb_master_writedata (jamb_master_writedata),
|
||||
.arbit_s0_axi4lite_awaddr (mm_interconnect_0_arbit_s0_axi4lite_awaddr),
|
||||
.arbit_s0_axi4lite_awprot (mm_interconnect_0_arbit_s0_axi4lite_awprot),
|
||||
.arbit_s0_axi4lite_awvalid (mm_interconnect_0_arbit_s0_axi4lite_awvalid),
|
||||
.arbit_s0_axi4lite_awready (mm_interconnect_0_arbit_s0_axi4lite_awready),
|
||||
.arbit_s0_axi4lite_wdata (mm_interconnect_0_arbit_s0_axi4lite_wdata),
|
||||
.arbit_s0_axi4lite_wstrb (mm_interconnect_0_arbit_s0_axi4lite_wstrb),
|
||||
.arbit_s0_axi4lite_wvalid (mm_interconnect_0_arbit_s0_axi4lite_wvalid),
|
||||
.arbit_s0_axi4lite_wready (mm_interconnect_0_arbit_s0_axi4lite_wready),
|
||||
.arbit_s0_axi4lite_bresp (mm_interconnect_0_arbit_s0_axi4lite_bresp),
|
||||
.arbit_s0_axi4lite_bvalid (mm_interconnect_0_arbit_s0_axi4lite_bvalid),
|
||||
.arbit_s0_axi4lite_bready (mm_interconnect_0_arbit_s0_axi4lite_bready),
|
||||
.arbit_s0_axi4lite_araddr (mm_interconnect_0_arbit_s0_axi4lite_araddr),
|
||||
.arbit_s0_axi4lite_arprot (mm_interconnect_0_arbit_s0_axi4lite_arprot),
|
||||
.arbit_s0_axi4lite_arvalid (mm_interconnect_0_arbit_s0_axi4lite_arvalid),
|
||||
.arbit_s0_axi4lite_arready (mm_interconnect_0_arbit_s0_axi4lite_arready),
|
||||
.arbit_s0_axi4lite_rdata (mm_interconnect_0_arbit_s0_axi4lite_rdata),
|
||||
.arbit_s0_axi4lite_rresp (mm_interconnect_0_arbit_s0_axi4lite_rresp),
|
||||
.arbit_s0_axi4lite_rvalid (mm_interconnect_0_arbit_s0_axi4lite_rvalid),
|
||||
.arbit_s0_axi4lite_rready (mm_interconnect_0_arbit_s0_axi4lite_rready),
|
||||
.arbit_s0_axi4lite_aresetn_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.jamb_master_translator_reset_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.clk_bridge_out_clk_clk (s0_axi4lite_clk),
|
||||
.clk_bridge_out_clk_3_clk (s0_axi4lite_clk)
|
||||
);
|
||||
|
||||
|
||||
|
||||
generate
|
||||
if (!AMM_TO_AXIL_INTERCONNECT_ONLY) begin: gen_arbit
|
||||
ed_synth_dut_intel_axi4lite_injector_100_2yowc3a #(
|
||||
.NUM_ACTIVE_AXI4LITE_S_INTERFACES (2),
|
||||
.AXI4LITE_QOS (0),
|
||||
.NUM_ACTIVE_AXI4_S_INTERFACES (0),
|
||||
.BUFFER_AXI4_S_READ_RESPONSES (0),
|
||||
.AXI4_S_TRANSFER_MULTIPLE (9),
|
||||
.INIU_AXI4_ADDR_WIDTH (32)
|
||||
) arbit (
|
||||
.m_axi4_aclk (s0_axi4lite_clk),
|
||||
.m_axi4_aresetn (~s0_axi4lite_rst_sync),
|
||||
.m_axi4_arid (arbit_m_axi4_arid),
|
||||
.m_axi4_araddr (arbit_m_axi4_araddr),
|
||||
.m_axi4_arlen (arbit_m_axi4_arlen),
|
||||
.m_axi4_arsize (arbit_m_axi4_arsize),
|
||||
.m_axi4_arburst (arbit_m_axi4_arburst),
|
||||
.m_axi4_arlock (arbit_m_axi4_arlock),
|
||||
.m_axi4_arprot (arbit_m_axi4_arprot),
|
||||
.m_axi4_arqos (arbit_m_axi4_arqos),
|
||||
.m_axi4_aruser (arbit_m_axi4_aruser),
|
||||
.m_axi4_arvalid (arbit_m_axi4_arvalid),
|
||||
.m_axi4_arready (arbit_m_axi4_arready),
|
||||
.m_axi4_rid (arbit_m_axi4_rid),
|
||||
.m_axi4_rdata (arbit_m_axi4_rdata),
|
||||
.m_axi4_rresp (arbit_m_axi4_rresp),
|
||||
.m_axi4_rlast (arbit_m_axi4_rlast),
|
||||
.m_axi4_ruser (arbit_m_axi4_ruser),
|
||||
.m_axi4_rvalid (arbit_m_axi4_rvalid),
|
||||
.m_axi4_rready (arbit_m_axi4_rready),
|
||||
.m_axi4_awid (arbit_m_axi4_awid),
|
||||
.m_axi4_awaddr (arbit_m_axi4_awaddr),
|
||||
.m_axi4_awlen (arbit_m_axi4_awlen),
|
||||
.m_axi4_awsize (arbit_m_axi4_awsize),
|
||||
.m_axi4_awburst (arbit_m_axi4_awburst),
|
||||
.m_axi4_awlock (arbit_m_axi4_awlock),
|
||||
.m_axi4_awprot (arbit_m_axi4_awprot),
|
||||
.m_axi4_awqos (arbit_m_axi4_awqos),
|
||||
.m_axi4_awuser (arbit_m_axi4_awuser),
|
||||
.m_axi4_awvalid (arbit_m_axi4_awvalid),
|
||||
.m_axi4_awready (arbit_m_axi4_awready),
|
||||
.m_axi4_wdata (arbit_m_axi4_wdata),
|
||||
.m_axi4_wstrb (arbit_m_axi4_wstrb),
|
||||
.m_axi4_wlast (arbit_m_axi4_wlast),
|
||||
.m_axi4_wuser (arbit_m_axi4_wuser),
|
||||
.m_axi4_wvalid (arbit_m_axi4_wvalid),
|
||||
.m_axi4_wready (arbit_m_axi4_wready),
|
||||
.m_axi4_bid (arbit_m_axi4_bid),
|
||||
.m_axi4_bresp (arbit_m_axi4_bresp),
|
||||
.m_axi4_bvalid (arbit_m_axi4_bvalid),
|
||||
.m_axi4_bready (arbit_m_axi4_bready),
|
||||
.s0_axi4lite_aclk (s0_axi4lite_clk),
|
||||
.s0_axi4lite_aresetn (~s0_axi4lite_rst_sync),
|
||||
.s0_axi4lite_awaddr (mm_interconnect_0_arbit_s0_axi4lite_awaddr),
|
||||
.s0_axi4lite_awvalid (mm_interconnect_0_arbit_s0_axi4lite_awvalid),
|
||||
.s0_axi4lite_awready (mm_interconnect_0_arbit_s0_axi4lite_awready),
|
||||
.s0_axi4lite_wdata (mm_interconnect_0_arbit_s0_axi4lite_wdata),
|
||||
.s0_axi4lite_wstrb (mm_interconnect_0_arbit_s0_axi4lite_wstrb),
|
||||
.s0_axi4lite_wvalid (mm_interconnect_0_arbit_s0_axi4lite_wvalid),
|
||||
.s0_axi4lite_wready (mm_interconnect_0_arbit_s0_axi4lite_wready),
|
||||
.s0_axi4lite_bresp (mm_interconnect_0_arbit_s0_axi4lite_bresp),
|
||||
.s0_axi4lite_bvalid (mm_interconnect_0_arbit_s0_axi4lite_bvalid),
|
||||
.s0_axi4lite_bready (mm_interconnect_0_arbit_s0_axi4lite_bready),
|
||||
.s0_axi4lite_araddr (mm_interconnect_0_arbit_s0_axi4lite_araddr),
|
||||
.s0_axi4lite_arvalid (mm_interconnect_0_arbit_s0_axi4lite_arvalid),
|
||||
.s0_axi4lite_arready (mm_interconnect_0_arbit_s0_axi4lite_arready),
|
||||
.s0_axi4lite_rdata (mm_interconnect_0_arbit_s0_axi4lite_rdata),
|
||||
.s0_axi4lite_rresp (mm_interconnect_0_arbit_s0_axi4lite_rresp),
|
||||
.s0_axi4lite_rvalid (mm_interconnect_0_arbit_s0_axi4lite_rvalid),
|
||||
.s0_axi4lite_rready (mm_interconnect_0_arbit_s0_axi4lite_rready),
|
||||
.s0_axi4lite_awprot (mm_interconnect_0_arbit_s0_axi4lite_awprot),
|
||||
.s0_axi4lite_arprot (mm_interconnect_0_arbit_s0_axi4lite_arprot),
|
||||
.s1_axi4lite_aclk (s0_axi4lite_clk),
|
||||
.s1_axi4lite_aresetn (~s0_axi4lite_rst_sync),
|
||||
.s1_axi4lite_awaddr (s0_axi4lite_awaddr),
|
||||
.s1_axi4lite_awvalid (s0_axi4lite_awvalid),
|
||||
.s1_axi4lite_awready (s0_axi4lite_awready),
|
||||
.s1_axi4lite_wdata (s0_axi4lite_wdata),
|
||||
.s1_axi4lite_wstrb (s0_axi4lite_wstrb),
|
||||
.s1_axi4lite_wvalid (s0_axi4lite_wvalid),
|
||||
.s1_axi4lite_wready (s0_axi4lite_wready),
|
||||
.s1_axi4lite_bresp (s0_axi4lite_bresp),
|
||||
.s1_axi4lite_bvalid (s0_axi4lite_bvalid),
|
||||
.s1_axi4lite_bready (s0_axi4lite_bready),
|
||||
.s1_axi4lite_araddr (s0_axi4lite_araddr),
|
||||
.s1_axi4lite_arvalid (s0_axi4lite_arvalid),
|
||||
.s1_axi4lite_arready (s0_axi4lite_arready),
|
||||
.s1_axi4lite_rdata (s0_axi4lite_rdata),
|
||||
.s1_axi4lite_rresp (s0_axi4lite_rresp),
|
||||
.s1_axi4lite_rvalid (s0_axi4lite_rvalid),
|
||||
.s1_axi4lite_rready (s0_axi4lite_rready),
|
||||
.s1_axi4lite_awprot (s0_axi4lite_awprot),
|
||||
.s1_axi4lite_arprot (s0_axi4lite_arprot)
|
||||
);
|
||||
|
||||
ed_synth_dut_altera_mm_interconnect_1920_5sovoyi mm_interconnect_1 (
|
||||
.arbit_m_axi4_awid (arbit_m_axi4_awid),
|
||||
.arbit_m_axi4_awaddr (arbit_m_axi4_awaddr),
|
||||
.arbit_m_axi4_awlen (arbit_m_axi4_awlen),
|
||||
.arbit_m_axi4_awsize (arbit_m_axi4_awsize),
|
||||
.arbit_m_axi4_awburst (arbit_m_axi4_awburst),
|
||||
.arbit_m_axi4_awlock (arbit_m_axi4_awlock),
|
||||
.arbit_m_axi4_awprot (arbit_m_axi4_awprot),
|
||||
.arbit_m_axi4_awuser (arbit_m_axi4_awuser),
|
||||
.arbit_m_axi4_awqos (arbit_m_axi4_awqos),
|
||||
.arbit_m_axi4_awvalid (arbit_m_axi4_awvalid),
|
||||
.arbit_m_axi4_awready (arbit_m_axi4_awready),
|
||||
.arbit_m_axi4_wdata (arbit_m_axi4_wdata),
|
||||
.arbit_m_axi4_wstrb (arbit_m_axi4_wstrb),
|
||||
.arbit_m_axi4_wlast (arbit_m_axi4_wlast),
|
||||
.arbit_m_axi4_wvalid (arbit_m_axi4_wvalid),
|
||||
.arbit_m_axi4_wuser (arbit_m_axi4_wuser),
|
||||
.arbit_m_axi4_wready (arbit_m_axi4_wready),
|
||||
.arbit_m_axi4_bid (arbit_m_axi4_bid),
|
||||
.arbit_m_axi4_bresp (arbit_m_axi4_bresp),
|
||||
.arbit_m_axi4_bvalid (arbit_m_axi4_bvalid),
|
||||
.arbit_m_axi4_bready (arbit_m_axi4_bready),
|
||||
.arbit_m_axi4_arid (arbit_m_axi4_arid),
|
||||
.arbit_m_axi4_araddr (arbit_m_axi4_araddr),
|
||||
.arbit_m_axi4_arlen (arbit_m_axi4_arlen),
|
||||
.arbit_m_axi4_arsize (arbit_m_axi4_arsize),
|
||||
.arbit_m_axi4_arburst (arbit_m_axi4_arburst),
|
||||
.arbit_m_axi4_arlock (arbit_m_axi4_arlock),
|
||||
.arbit_m_axi4_arprot (arbit_m_axi4_arprot),
|
||||
.arbit_m_axi4_aruser (arbit_m_axi4_aruser),
|
||||
.arbit_m_axi4_arqos (arbit_m_axi4_arqos),
|
||||
.arbit_m_axi4_arvalid (arbit_m_axi4_arvalid),
|
||||
.arbit_m_axi4_arready (arbit_m_axi4_arready),
|
||||
.arbit_m_axi4_rid (arbit_m_axi4_rid),
|
||||
.arbit_m_axi4_rdata (arbit_m_axi4_rdata),
|
||||
.arbit_m_axi4_rresp (arbit_m_axi4_rresp),
|
||||
.arbit_m_axi4_rlast (arbit_m_axi4_rlast),
|
||||
.arbit_m_axi4_rvalid (arbit_m_axi4_rvalid),
|
||||
.arbit_m_axi4_rready (arbit_m_axi4_rready),
|
||||
.arbit_m_axi4_ruser (arbit_m_axi4_ruser),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awaddr (cal_arch_0_s0_axi4lite_axi4_lite_awaddr),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awprot (cal_arch_0_s0_axi4lite_axi4_lite_awprot),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awvalid (cal_arch_0_s0_axi4lite_axi4_lite_awvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_awready (cal_arch_0_s0_axi4lite_axi4_lite_awready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wdata (cal_arch_0_s0_axi4lite_axi4_lite_wdata),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wstrb (cal_arch_0_s0_axi4lite_axi4_lite_wstrb),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wvalid (cal_arch_0_s0_axi4lite_axi4_lite_wvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_wready (cal_arch_0_s0_axi4lite_axi4_lite_wready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_bresp (cal_arch_0_s0_axi4lite_axi4_lite_bresp),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_bvalid (cal_arch_0_s0_axi4lite_axi4_lite_bvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_bready (cal_arch_0_s0_axi4lite_axi4_lite_bready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_araddr (cal_arch_0_s0_axi4lite_axi4_lite_araddr),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_arprot (cal_arch_0_s0_axi4lite_axi4_lite_arprot),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_arvalid (cal_arch_0_s0_axi4lite_axi4_lite_arvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_arready (cal_arch_0_s0_axi4lite_axi4_lite_arready),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rdata (cal_arch_0_s0_axi4lite_axi4_lite_rdata),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rresp (cal_arch_0_s0_axi4lite_axi4_lite_rresp),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rvalid (cal_arch_0_s0_axi4lite_axi4_lite_rvalid),
|
||||
.cal_arch_0_s0_axi4lite_axi4_lite_rready (cal_arch_0_s0_axi4lite_axi4_lite_rready),
|
||||
.arbit_m_axi4_aresetn_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.cal_arch_0_s0_axi4lite_rst_n_reset_bridge_in_reset_reset (s0_axi4lite_rst_sync),
|
||||
.clk_bridge_out_clk_2_clk (s0_axi4lite_clk),
|
||||
.clk_bridge_out_clk_1_clk (s0_axi4lite_clk)
|
||||
);
|
||||
|
||||
end else begin: gen_connect_axil_output_intf
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_awaddr = mm_interconnect_0_arbit_s0_axi4lite_awaddr;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_awprot = mm_interconnect_0_arbit_s0_axi4lite_awprot;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_awvalid = mm_interconnect_0_arbit_s0_axi4lite_awvalid;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_awready = cal_arch_0_s0_axi4lite_axi4_lite_awready;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_wdata = mm_interconnect_0_arbit_s0_axi4lite_wdata;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_wstrb = mm_interconnect_0_arbit_s0_axi4lite_wstrb;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_wvalid = mm_interconnect_0_arbit_s0_axi4lite_wvalid;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_wready = cal_arch_0_s0_axi4lite_axi4_lite_wready;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_bresp = cal_arch_0_s0_axi4lite_axi4_lite_bresp;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_bvalid = cal_arch_0_s0_axi4lite_axi4_lite_bvalid;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_bready = mm_interconnect_0_arbit_s0_axi4lite_bready;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_araddr = mm_interconnect_0_arbit_s0_axi4lite_araddr;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_arprot = mm_interconnect_0_arbit_s0_axi4lite_arprot;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_arvalid = mm_interconnect_0_arbit_s0_axi4lite_arvalid;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_arready = cal_arch_0_s0_axi4lite_axi4_lite_arready;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_rdata = cal_arch_0_s0_axi4lite_axi4_lite_rdata;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_rresp = cal_arch_0_s0_axi4lite_axi4_lite_rresp;
|
||||
assign mm_interconnect_0_arbit_s0_axi4lite_rvalid = cal_arch_0_s0_axi4lite_axi4_lite_rvalid;
|
||||
assign cal_arch_0_s0_axi4lite_axi4_lite_rready = mm_interconnect_0_arbit_s0_axi4lite_rready;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
module cal_arch_fp_atom_inst_comp #(
|
||||
parameter IS_USED = 0,
|
||||
|
||||
parameter BASE_ADDRESS = 0,
|
||||
|
||||
localparam PORT_I_AVM_ADDRESS_WIDTH = 22,
|
||||
localparam PORT_I_AVM_WRITEDATA_WIDTH = 32,
|
||||
localparam PORT_O_AVM_READDATA_COMP_WIDTH = 32
|
||||
) (
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
|
||||
logic avm_clk;
|
||||
logic avm_rst_n;
|
||||
logic [PORT_I_AVM_ADDRESS_WIDTH-1:0] i_avm_address;
|
||||
logic i_avm_read;
|
||||
logic i_avm_write;
|
||||
logic [PORT_I_AVM_WRITEDATA_WIDTH-1:0] i_avm_writedata;
|
||||
logic [PORT_O_AVM_READDATA_COMP_WIDTH-1:0] o_avm_readdata_comp;
|
||||
|
||||
tennm_compensation_block # (
|
||||
.base_address (BASE_ADDRESS)
|
||||
) comp (
|
||||
.avm_clk (avm_clk),
|
||||
.avm_rst_n (avm_rst_n),
|
||||
.i_avm_address (i_avm_address),
|
||||
.i_avm_read (i_avm_read),
|
||||
.i_avm_write (i_avm_write),
|
||||
.i_avm_writedata (i_avm_writedata),
|
||||
.o_avm_readdata_comp (o_avm_readdata_comp)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9h3nWj04w/zCV+gxx1kFjPwr42c+wh9viQCcXe8AdUB+HG9kFmXLWB4teTAazeuYuyNN3cihTIPcdr6lIWE/4KmE4wPDHe1eUH8M1N4QnHBz1/623ugjhsPacmVcSgQCPcfXVtRrkty7jsn7mPRzqlvVuwhm/DBR+rATS3FHAql0W79WgG+4ojlEuu8R4oxRnMIwCs8wqdQMkxqU2gAo4z9UCTK3rRHjhZpykFv1h1DcwSCfV6L8niZh0au+/9WClx5hwgB9usGkdmNOOy4bfIQd6xkLnhzQV0CWpRFqyEW4+z59T3U8x0yETuXqBgXiCQAcpSvymtFtmhcYT1B3kbnhgmuw80H0sa4d4bCgQm3XuAQMnalCzAIu7g5sVV1Idf+za3/k8/MHu+fd0nDmd6cKAw4qTAdVQRIia2Ck4t395Ogknb+wUZ4C+7f+6kkwbTg/062nCIm6mivxfsP2NARo0ZjAMJFREWqoagsfovx33ejk+gM54L5eFupLAwFJlCzISw8+vrrlk0Uy/+oQKzE9RnHu+Afr4H8WeHoX4qyC3wopUliQxeN9/TeS10EJl7lEdY8yY5xfxthnF77iLdyE51Y3MxGmtM0Gi/wZKiM5CfoJO6+V4tGToSAXiVQYPr8C/sXuhA0loNp/B1bTYUExmP0H8tM+f4S4sshkb6AvdE/FEQiYKdo0V5tP3dTFsP7bHGTpGXOnaJaASn2CuzvVqoh44/+OxtyPmncQlMNwBNR+ot6UuXkqaGhS4146I6Rc1QmlxqiUm9Npy8Dj9+"
|
||||
`endif
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
module stdfn_inst_fa_c2p_ssm #(
|
||||
parameter IS_USED = 0,
|
||||
|
||||
parameter SSM_C2P_DATA_MODE = "SSM_C2P_DATA_MODE_BYPASS",
|
||||
parameter FA_CORE_PERIPH_CLK_SEL_DATA_MODE = "FA_CORE_PERIPH_CLK_SEL_DATA_MODE_UNUSED",
|
||||
parameter SSM_P2C_DATA_MODE = "SSM_P2C_DATA_MODE_BYPASS",
|
||||
localparam PORT_I_SSM_C2P_WIDTH = 40,
|
||||
localparam PORT_O_SSM_C2P_WIDTH = 40,
|
||||
localparam PORT_I_SSM_P2C_WIDTH = 20,
|
||||
localparam PORT_O_SSM_P2C_WIDTH = 20
|
||||
) (
|
||||
input i_core_clk,
|
||||
input [PORT_I_SSM_C2P_WIDTH-1:0] i_ssm_c2p,
|
||||
output [PORT_O_SSM_C2P_WIDTH-1:0] o_ssm_c2p,
|
||||
input i_phy_clk_fr,
|
||||
input i_phy_clk_sync,
|
||||
input [PORT_I_SSM_P2C_WIDTH-1:0] i_ssm_p2c,
|
||||
output [PORT_O_SSM_P2C_WIDTH-1:0] o_ssm_p2c
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
|
||||
tennm_ssm_c2p_fabric_adaptor # (
|
||||
.ssm_c2p_data_mode (SSM_C2P_DATA_MODE),
|
||||
.fa_core_periph_clk_sel_data_mode (FA_CORE_PERIPH_CLK_SEL_DATA_MODE)
|
||||
) fa_c2p_ssm (
|
||||
.i_core_clk (i_core_clk),
|
||||
.i_phy_clk_fr (i_phy_clk_fr),
|
||||
.i_phy_clk_sync (i_phy_clk_sync),
|
||||
.i_ssm_c2p (i_ssm_c2p),
|
||||
.o_ssm_c2p (o_ssm_c2p)
|
||||
);
|
||||
tennm_ssm_p2c_fabric_adaptor # (
|
||||
.ssm_p2c_data_mode (SSM_P2C_DATA_MODE),
|
||||
.fa_core_periph_clk_sel_data_mode (FA_CORE_PERIPH_CLK_SEL_DATA_MODE)
|
||||
) fa_p2c_ssm (
|
||||
.i_core_clk (i_core_clk),
|
||||
.i_phy_clk_fr (i_phy_clk_fr),
|
||||
.i_phy_clk_sync (i_phy_clk_sync),
|
||||
.i_ssm_p2c (i_ssm_p2c),
|
||||
.o_ssm_p2c (o_ssm_p2c)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc+96bwJRyKwPdrMtYSy7m+X0yzYshDLSxe/WLUb3qsczNZaIWpknYTeedvLKw/e1EnLil9SSlUaAB9RYBjO5BB6xCFjoi9OwEQ0Q52WST0YiB57jUOsXiyNw/1ZUY8o0YzYGzlvDXM1ty7Hn3WnJYLW1WfdBDwhyLWR1/cYX+VG7FQYJxHGlb6SN+stmztbJjnrLUj8iBoLZL+F0l5Ote0peaY0j2vY6Xv/RY2IqJsmpi1/LjrikCDY9fQjkplfr2oCqChH+5qZ+O/Ejg/hKXGxp8quekqCzbplbwa7ZY/oG3h5WhybqEhOz6R0f4UOfGoKHxTFyzuAS6htuJ9YLiBE/ZqaGWbe4S+UmGSEizMJHAmT3ZbwuyWUKqp1AvHI6WqE/hXRI6LI/3+4MaoMTern7Fy27oP8lexuJUK45PT6Mtoy/sD+ZFFP2fG2S72m7Gi9U+4EmXdAYvwVbpoesy+GrvcCBuMN6XlN2PH3XwI5kLMSLbLydOfpe1KRIMeDxktajCoUk3HKgQDT+2L/MWk9/2Pb90MRKAhGT2Ek8QmTo1w/XNHV/Z5mDb2mxm1G0YrQSyUApISqnrANcd6OC/VxLYDUhXU2Sl9KGrF+maS05FaWKomFRC8NiWqZEOYZMi/LpLbEJQLd+Jh+h+CHSTMdntEuCr2hlAJJFq9pYzFMsAOkPRW+5BpBjHCmyVxtDLpdyMXF2tnfV5qPSoO+QEbtX1HgCGMofqg38PyKPy/nsFfpcY59ZK2uphMWteiELe5CwrAxqoOFPyhYhEXkZoAz"
|
||||
`endif
|
||||
+301
@@ -0,0 +1,301 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
module io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_stdfn_inst_iossm #(
|
||||
|
||||
localparam PORT_AXIL_ARADDR_WIDTH = 27,
|
||||
localparam PORT_AXIL_AWADDR_WIDTH = 27,
|
||||
localparam PORT_AXIL_BRESP_WIDTH = 2,
|
||||
localparam PORT_AXIL_RDATA_WIDTH = 32,
|
||||
localparam PORT_AXIL_RRESP_WIDTH = 2,
|
||||
localparam PORT_AXIL_WDATA_WIDTH = 32,
|
||||
localparam PORT_AXIL_WSTRB_WIDTH = 4,
|
||||
localparam PORT_CALBUS0_ADDR_WIDTH = 22,
|
||||
localparam PORT_CALBUS0_READDATA_WIDTH = 32,
|
||||
localparam PORT_CALBUS0_WRITEDATA_WIDTH = 32,
|
||||
localparam PORT_HADDR_WIDTH = 16,
|
||||
localparam PORT_HBURST_WIDTH = 3,
|
||||
localparam PORT_HSIZE_WIDTH = 3,
|
||||
localparam PORT_HTRANS_WIDTH = 2,
|
||||
localparam PORT_HWDATA_WIDTH = 32,
|
||||
localparam PORT_IOFBRADAPT_SSM_C2P_WIDTH = 31,
|
||||
localparam PORT_IOFBRADAPT_SSM_P2C_WIDTH = 8,
|
||||
localparam PORT_I_SIM_PARAM_TABLE_WIDTH = 16384,
|
||||
localparam PORT_MC_HRDATA_WIDTH = 32,
|
||||
localparam PORT_MC_HRESP_WIDTH = 2
|
||||
|
||||
) (
|
||||
input [PORT_AXIL_ARADDR_WIDTH-1:0] axil_araddr,
|
||||
output axil_arready,
|
||||
input axil_arvalid,
|
||||
input [PORT_AXIL_AWADDR_WIDTH-1:0] axil_awaddr,
|
||||
output axil_awready,
|
||||
input axil_awvalid,
|
||||
input axil_bready,
|
||||
output [PORT_AXIL_BRESP_WIDTH-1:0] axil_bresp,
|
||||
output axil_bvalid,
|
||||
output axil_clk,
|
||||
output [PORT_AXIL_RDATA_WIDTH-1:0] axil_rdata,
|
||||
input axil_rready,
|
||||
output [PORT_AXIL_RRESP_WIDTH-1:0] axil_rresp,
|
||||
output axil_rvalid,
|
||||
input [PORT_AXIL_WDATA_WIDTH-1:0] axil_wdata,
|
||||
output axil_wready,
|
||||
input [PORT_AXIL_WSTRB_WIDTH-1:0] axil_wstrb,
|
||||
input axil_wvalid,
|
||||
|
||||
input c2p_clk,
|
||||
|
||||
output [PORT_CALBUS0_ADDR_WIDTH-1:0] calbus0_addr,
|
||||
output calbus0_clock,
|
||||
output calbus0_read,
|
||||
input [PORT_CALBUS0_READDATA_WIDTH-1:0] calbus0_readdata,
|
||||
output calbus0_rst_n,
|
||||
output calbus0_write,
|
||||
output [PORT_CALBUS0_WRITEDATA_WIDTH-1:0] calbus0_writedata,
|
||||
|
||||
output clk_en_in,
|
||||
|
||||
output [PORT_HADDR_WIDTH-1:0] haddr,
|
||||
output [PORT_HBURST_WIDTH-1:0] hburst,
|
||||
output hclk,
|
||||
output hready,
|
||||
output hresetn,
|
||||
output hsel,
|
||||
output [PORT_HSIZE_WIDTH-1:0] hsize,
|
||||
output [PORT_HTRANS_WIDTH-1:0] htrans,
|
||||
output [PORT_HWDATA_WIDTH-1:0] hwdata,
|
||||
output hwrite,
|
||||
input [PORT_MC_HRDATA_WIDTH-1:0] mc0_hrdata,
|
||||
input mc0_hreadyout,
|
||||
input [PORT_MC_HRESP_WIDTH-1:0] mc0_hresp,
|
||||
input [PORT_MC_HRDATA_WIDTH-1:0] mc1_hrdata,
|
||||
input mc1_hreadyout,
|
||||
input [PORT_MC_HRESP_WIDTH-1:0] mc1_hresp,
|
||||
|
||||
input [PORT_I_SIM_PARAM_TABLE_WIDTH-1:0] i_sim_param_table_0,
|
||||
input [PORT_I_SIM_PARAM_TABLE_WIDTH-1:0] i_sim_param_table_1,
|
||||
input mc0_irq,
|
||||
input mc1_irq,
|
||||
output mc0_rst_n,
|
||||
output mc1_rst_n,
|
||||
|
||||
output i3c_scl,
|
||||
output i3c_sda_dr_en_n,
|
||||
output i3c_sda_pp,
|
||||
input i3c_sda_rx,
|
||||
output i3c_sda_tx,
|
||||
|
||||
input [PORT_IOFBRADAPT_SSM_C2P_WIDTH-1:0] iofbradapt_ssm_c2p,
|
||||
output [PORT_IOFBRADAPT_SSM_P2C_WIDTH-1:0] iofbradapt_ssm_p2c
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
import io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_atom_attr_iossm::*;
|
||||
|
||||
tennm_ph2_iossm # (
|
||||
.iossm_mem_init_onekb_hexfile (IOSSM_MEM_INIT_ONEKB_HEXFILE),
|
||||
.iossm_mem_init_onekb (IOSSM_MEM_INIT_ONEKB),
|
||||
.iossm_mem_init_hexfile (IOSSM_MEM_INIT_HEXFILE),
|
||||
.iossm_mem_init_99 (IOSSM_MEM_INIT_UPPER[99-64]),
|
||||
.iossm_mem_init_98 (IOSSM_MEM_INIT_UPPER[98-64]),
|
||||
.iossm_mem_init_97 (IOSSM_MEM_INIT_UPPER[97-64]),
|
||||
.iossm_mem_init_96 (IOSSM_MEM_INIT_UPPER[96-64]),
|
||||
.iossm_mem_init_95 (IOSSM_MEM_INIT_UPPER[95-64]),
|
||||
.iossm_mem_init_94 (IOSSM_MEM_INIT_UPPER[94-64]),
|
||||
.iossm_mem_init_93 (IOSSM_MEM_INIT_UPPER[93-64]),
|
||||
.iossm_mem_init_92 (IOSSM_MEM_INIT_UPPER[92-64]),
|
||||
.iossm_mem_init_91 (IOSSM_MEM_INIT_UPPER[91-64]),
|
||||
.iossm_mem_init_90 (IOSSM_MEM_INIT_UPPER[90-64]),
|
||||
.iossm_mem_init_9 (IOSSM_MEM_INIT_LOWER[9]),
|
||||
.iossm_mem_init_89 (IOSSM_MEM_INIT_UPPER[89-64]),
|
||||
.iossm_mem_init_88 (IOSSM_MEM_INIT_UPPER[88-64]),
|
||||
.iossm_mem_init_87 (IOSSM_MEM_INIT_UPPER[87-64]),
|
||||
.iossm_mem_init_86 (IOSSM_MEM_INIT_UPPER[86-64]),
|
||||
.iossm_mem_init_85 (IOSSM_MEM_INIT_UPPER[85-64]),
|
||||
.iossm_mem_init_84 (IOSSM_MEM_INIT_UPPER[84-64]),
|
||||
.iossm_mem_init_83 (IOSSM_MEM_INIT_UPPER[83-64]),
|
||||
.iossm_mem_init_82 (IOSSM_MEM_INIT_UPPER[82-64]),
|
||||
.iossm_mem_init_81 (IOSSM_MEM_INIT_UPPER[81-64]),
|
||||
.iossm_mem_init_80 (IOSSM_MEM_INIT_UPPER[80-64]),
|
||||
.iossm_mem_init_8 (IOSSM_MEM_INIT_LOWER[8]),
|
||||
.iossm_mem_init_79 (IOSSM_MEM_INIT_UPPER[79-64]),
|
||||
.iossm_mem_init_78 (IOSSM_MEM_INIT_UPPER[78-64]),
|
||||
.iossm_mem_init_77 (IOSSM_MEM_INIT_UPPER[77-64]),
|
||||
.iossm_mem_init_76 (IOSSM_MEM_INIT_UPPER[76-64]),
|
||||
.iossm_mem_init_75 (IOSSM_MEM_INIT_UPPER[75-64]),
|
||||
.iossm_mem_init_74 (IOSSM_MEM_INIT_UPPER[74-64]),
|
||||
.iossm_mem_init_73 (IOSSM_MEM_INIT_UPPER[73-64]),
|
||||
.iossm_mem_init_72 (IOSSM_MEM_INIT_UPPER[72-64]),
|
||||
.iossm_mem_init_71 (IOSSM_MEM_INIT_UPPER[71-64]),
|
||||
.iossm_mem_init_70 (IOSSM_MEM_INIT_UPPER[70-64]),
|
||||
.iossm_mem_init_7 (IOSSM_MEM_INIT_LOWER[7]),
|
||||
.iossm_mem_init_69 (IOSSM_MEM_INIT_UPPER[69-64]),
|
||||
.iossm_mem_init_68 (IOSSM_MEM_INIT_UPPER[68-64]),
|
||||
.iossm_mem_init_67 (IOSSM_MEM_INIT_UPPER[67-64]),
|
||||
.iossm_mem_init_66 (IOSSM_MEM_INIT_UPPER[66-64]),
|
||||
.iossm_mem_init_65 (IOSSM_MEM_INIT_UPPER[65-64]),
|
||||
.iossm_mem_init_64 (IOSSM_MEM_INIT_UPPER[64-64]),
|
||||
.iossm_mem_init_63 (IOSSM_MEM_INIT_LOWER[63]),
|
||||
.iossm_mem_init_62 (IOSSM_MEM_INIT_LOWER[62]),
|
||||
.iossm_mem_init_61 (IOSSM_MEM_INIT_LOWER[61]),
|
||||
.iossm_mem_init_60 (IOSSM_MEM_INIT_LOWER[60]),
|
||||
.iossm_mem_init_6 (IOSSM_MEM_INIT_LOWER[6]),
|
||||
.iossm_mem_init_59 (IOSSM_MEM_INIT_LOWER[59]),
|
||||
.iossm_mem_init_58 (IOSSM_MEM_INIT_LOWER[58]),
|
||||
.iossm_mem_init_57 (IOSSM_MEM_INIT_LOWER[57]),
|
||||
.iossm_mem_init_56 (IOSSM_MEM_INIT_LOWER[56]),
|
||||
.iossm_mem_init_55 (IOSSM_MEM_INIT_LOWER[55]),
|
||||
.iossm_mem_init_54 (IOSSM_MEM_INIT_LOWER[54]),
|
||||
.iossm_mem_init_53 (IOSSM_MEM_INIT_LOWER[53]),
|
||||
.iossm_mem_init_52 (IOSSM_MEM_INIT_LOWER[52]),
|
||||
.iossm_mem_init_51 (IOSSM_MEM_INIT_LOWER[51]),
|
||||
.iossm_mem_init_50 (IOSSM_MEM_INIT_LOWER[50]),
|
||||
.iossm_mem_init_5 (IOSSM_MEM_INIT_LOWER[5]),
|
||||
.iossm_mem_init_49 (IOSSM_MEM_INIT_LOWER[49]),
|
||||
.iossm_mem_init_48 (IOSSM_MEM_INIT_LOWER[48]),
|
||||
.iossm_mem_init_47 (IOSSM_MEM_INIT_LOWER[47]),
|
||||
.iossm_mem_init_46 (IOSSM_MEM_INIT_LOWER[46]),
|
||||
.iossm_mem_init_45 (IOSSM_MEM_INIT_LOWER[45]),
|
||||
.iossm_mem_init_44 (IOSSM_MEM_INIT_LOWER[44]),
|
||||
.iossm_mem_init_43 (IOSSM_MEM_INIT_LOWER[43]),
|
||||
.iossm_mem_init_42 (IOSSM_MEM_INIT_LOWER[42]),
|
||||
.iossm_mem_init_41 (IOSSM_MEM_INIT_LOWER[41]),
|
||||
.iossm_mem_init_40 (IOSSM_MEM_INIT_LOWER[40]),
|
||||
.iossm_mem_init_4 (IOSSM_MEM_INIT_LOWER[4]),
|
||||
.iossm_mem_init_39 (IOSSM_MEM_INIT_LOWER[39]),
|
||||
.iossm_mem_init_38 (IOSSM_MEM_INIT_LOWER[38]),
|
||||
.iossm_mem_init_37 (IOSSM_MEM_INIT_LOWER[37]),
|
||||
.iossm_mem_init_36 (IOSSM_MEM_INIT_LOWER[36]),
|
||||
.iossm_mem_init_35 (IOSSM_MEM_INIT_LOWER[35]),
|
||||
.iossm_mem_init_34 (IOSSM_MEM_INIT_LOWER[34]),
|
||||
.iossm_mem_init_33 (IOSSM_MEM_INIT_LOWER[33]),
|
||||
.iossm_mem_init_32 (IOSSM_MEM_INIT_LOWER[32]),
|
||||
.iossm_mem_init_31 (IOSSM_MEM_INIT_LOWER[31]),
|
||||
.iossm_mem_init_30 (IOSSM_MEM_INIT_LOWER[30]),
|
||||
.iossm_mem_init_3 (IOSSM_MEM_INIT_LOWER[3]),
|
||||
.iossm_mem_init_29 (IOSSM_MEM_INIT_LOWER[29]),
|
||||
.iossm_mem_init_28 (IOSSM_MEM_INIT_LOWER[28]),
|
||||
.iossm_mem_init_27 (IOSSM_MEM_INIT_LOWER[27]),
|
||||
.iossm_mem_init_26 (IOSSM_MEM_INIT_LOWER[26]),
|
||||
.iossm_mem_init_25 (IOSSM_MEM_INIT_LOWER[25]),
|
||||
.iossm_mem_init_24 (IOSSM_MEM_INIT_LOWER[24]),
|
||||
.iossm_mem_init_23 (IOSSM_MEM_INIT_LOWER[23]),
|
||||
.iossm_mem_init_22 (IOSSM_MEM_INIT_LOWER[22]),
|
||||
.iossm_mem_init_21 (IOSSM_MEM_INIT_LOWER[21]),
|
||||
.iossm_mem_init_20 (IOSSM_MEM_INIT_LOWER[20]),
|
||||
.iossm_mem_init_2 (IOSSM_MEM_INIT_LOWER[2]),
|
||||
.iossm_mem_init_19 (IOSSM_MEM_INIT_LOWER[19]),
|
||||
.iossm_mem_init_18 (IOSSM_MEM_INIT_LOWER[18]),
|
||||
.iossm_mem_init_17 (IOSSM_MEM_INIT_LOWER[17]),
|
||||
.iossm_mem_init_16 (IOSSM_MEM_INIT_LOWER[16]),
|
||||
.iossm_mem_init_15 (IOSSM_MEM_INIT_LOWER[15]),
|
||||
.iossm_mem_init_14 (IOSSM_MEM_INIT_LOWER[14]),
|
||||
.iossm_mem_init_13 (IOSSM_MEM_INIT_LOWER[13]),
|
||||
.iossm_mem_init_127 (IOSSM_MEM_INIT_UPPER[127-64]),
|
||||
.iossm_mem_init_126 (IOSSM_MEM_INIT_UPPER[126-64]),
|
||||
.iossm_mem_init_125 (IOSSM_MEM_INIT_UPPER[125-64]),
|
||||
.iossm_mem_init_124 (IOSSM_MEM_INIT_UPPER[124-64]),
|
||||
.iossm_mem_init_123 (IOSSM_MEM_INIT_UPPER[123-64]),
|
||||
.iossm_mem_init_122 (IOSSM_MEM_INIT_UPPER[122-64]),
|
||||
.iossm_mem_init_121 (IOSSM_MEM_INIT_UPPER[121-64]),
|
||||
.iossm_mem_init_120 (IOSSM_MEM_INIT_UPPER[120-64]),
|
||||
.iossm_mem_init_12 (IOSSM_MEM_INIT_LOWER[12]),
|
||||
.iossm_mem_init_119 (IOSSM_MEM_INIT_UPPER[119-64]),
|
||||
.iossm_mem_init_118 (IOSSM_MEM_INIT_UPPER[118-64]),
|
||||
.iossm_mem_init_117 (IOSSM_MEM_INIT_UPPER[117-64]),
|
||||
.iossm_mem_init_116 (IOSSM_MEM_INIT_UPPER[116-64]),
|
||||
.iossm_mem_init_115 (IOSSM_MEM_INIT_UPPER[115-64]),
|
||||
.iossm_mem_init_114 (IOSSM_MEM_INIT_UPPER[114-64]),
|
||||
.iossm_mem_init_113 (IOSSM_MEM_INIT_UPPER[113-64]),
|
||||
.iossm_mem_init_112 (IOSSM_MEM_INIT_UPPER[112-64]),
|
||||
.iossm_mem_init_111 (IOSSM_MEM_INIT_UPPER[111-64]),
|
||||
.iossm_mem_init_110 (IOSSM_MEM_INIT_UPPER[110-64]),
|
||||
.iossm_mem_init_11 (IOSSM_MEM_INIT_LOWER[11]),
|
||||
.iossm_mem_init_109 (IOSSM_MEM_INIT_UPPER[109-64]),
|
||||
.iossm_mem_init_108 (IOSSM_MEM_INIT_UPPER[108-64]),
|
||||
.iossm_mem_init_107 (IOSSM_MEM_INIT_UPPER[107-64]),
|
||||
.iossm_mem_init_106 (IOSSM_MEM_INIT_UPPER[106-64]),
|
||||
.iossm_mem_init_105 (IOSSM_MEM_INIT_UPPER[105-64]),
|
||||
.iossm_mem_init_104 (IOSSM_MEM_INIT_UPPER[104-64]),
|
||||
.iossm_mem_init_103 (IOSSM_MEM_INIT_UPPER[103-64]),
|
||||
.iossm_mem_init_102 (IOSSM_MEM_INIT_UPPER[102-64]),
|
||||
.iossm_mem_init_101 (IOSSM_MEM_INIT_UPPER[101-64]),
|
||||
.iossm_mem_init_100 (IOSSM_MEM_INIT_UPPER[100-64]),
|
||||
.iossm_mem_init_10 (IOSSM_MEM_INIT_LOWER[10]),
|
||||
.iossm_mem_init_1 (IOSSM_MEM_INIT_LOWER[1]),
|
||||
.iossm_mem_init_0 (IOSSM_MEM_INIT_LOWER[0]),
|
||||
.parameter_table_hexfile (PARAMETER_TABLE_HEXFILE)
|
||||
) iossm (
|
||||
.axil_araddr (axil_araddr),
|
||||
.axil_arready (axil_arready),
|
||||
.axil_arvalid (axil_arvalid),
|
||||
.axil_awaddr (axil_awaddr),
|
||||
.axil_awready (axil_awready),
|
||||
.axil_awvalid (axil_awvalid),
|
||||
.axil_bready (axil_bready),
|
||||
.axil_bresp (axil_bresp),
|
||||
.axil_bvalid (axil_bvalid),
|
||||
.axil_clk (axil_clk),
|
||||
.axil_rdata (axil_rdata),
|
||||
.axil_rready (axil_rready),
|
||||
.axil_rresp (axil_rresp),
|
||||
.axil_rvalid (axil_rvalid),
|
||||
.axil_wdata (axil_wdata),
|
||||
.axil_wready (axil_wready),
|
||||
.axil_wstrb (axil_wstrb),
|
||||
.axil_wvalid (axil_wvalid),
|
||||
.c2p_clk (c2p_clk),
|
||||
.calbus0_addr (calbus0_addr),
|
||||
.calbus0_clock (calbus0_clock),
|
||||
.calbus0_read (calbus0_read),
|
||||
.calbus0_readdata (calbus0_readdata),
|
||||
.calbus0_rst_n (calbus0_rst_n),
|
||||
.calbus0_write (calbus0_write),
|
||||
.calbus0_writedata (calbus0_writedata),
|
||||
.clk_en_in (clk_en_in),
|
||||
.haddr (haddr),
|
||||
.hburst (hburst),
|
||||
.hclk (hclk),
|
||||
.hready (hready),
|
||||
.hresetn (hresetn),
|
||||
.hsel (hsel),
|
||||
.hsize (hsize),
|
||||
.htrans (htrans),
|
||||
.hwdata (hwdata),
|
||||
.hwrite (hwrite),
|
||||
.i3c_scl (i3c_scl),
|
||||
.i3c_sda_dr_en_n (i3c_sda_dr_en_n),
|
||||
.i3c_sda_pp (i3c_sda_pp),
|
||||
.i3c_sda_rx (i3c_sda_rx),
|
||||
.i3c_sda_tx (i3c_sda_tx),
|
||||
.iofbradapt_ssm_c2p (iofbradapt_ssm_c2p),
|
||||
.iofbradapt_ssm_p2c (iofbradapt_ssm_p2c),
|
||||
.i_sim_param_table_0 (i_sim_param_table_0),
|
||||
.i_sim_param_table_1 (i_sim_param_table_1),
|
||||
.mc0_hrdata (mc0_hrdata),
|
||||
.mc0_hreadyout (mc0_hreadyout),
|
||||
.mc0_hresp (mc0_hresp),
|
||||
.mc0_irq (mc0_irq),
|
||||
.mc0_rst_n (mc0_rst_n),
|
||||
.mc1_hrdata (mc1_hrdata),
|
||||
.mc1_hreadyout (mc1_hreadyout),
|
||||
.mc1_hresp (mc1_hresp),
|
||||
.mc1_irq (mc1_irq),
|
||||
.mc1_rst_n (mc1_rst_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+399
@@ -0,0 +1,399 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
module io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_stdfn_inst_seq #(
|
||||
localparam PORT_I_AVL_ADDRESS_WIDTH = 22,
|
||||
localparam PORT_I_AVL_READDATA_CKGEN_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_COMP_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_FBRPLL_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_IOPLL_WIDTH = 32,
|
||||
localparam PORT_I_AVL_READDATA_LANE_WIDTH = 32,
|
||||
localparam PORT_I_AVL_WRITEDATA_WIDTH = 32,
|
||||
localparam PORT_I_RB_BASE_ADDRESS_PA_WIDTH = 11,
|
||||
localparam PORT_I_SEQ_RDDATA_WIDTH = 96,
|
||||
localparam PORT_I_SEQ_RDDATA_VALID_WIDTH = 4,
|
||||
localparam PORT_O_AVL_ADDRESS_CKGEN_WIDTH = 22,
|
||||
localparam PORT_O_AVL_ADDRESS_COMP_WIDTH = 22,
|
||||
localparam PORT_O_AVL_ADDRESS_LANE_WIDTH = 22,
|
||||
localparam PORT_O_AVL_ADDRESS_PLL_WIDTH = 22,
|
||||
localparam PORT_O_AVL_READDATA_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_CKGEN_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_COMP_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_LANE_WIDTH = 32,
|
||||
localparam PORT_O_AVL_WRITEDATA_PLL_WIDTH = 32,
|
||||
localparam PORT_O_SEQ_RDDATA_EN_WIDTH = 4,
|
||||
localparam PORT_O_SEQ_RD_RANK_WIDTH = 8,
|
||||
localparam PORT_O_SEQ_SUPPRESSION_WIDTH = 12,
|
||||
localparam PORT_O_SEQ_WRDATA_WIDTH = 96,
|
||||
localparam PORT_O_SEQ_WRDATA_EN_WIDTH = 4,
|
||||
localparam PORT_O_SEQ_WR_DQS_EN_WIDTH = 4,
|
||||
localparam PORT_O_SEQ_WR_RANK_WIDTH = 8
|
||||
) (
|
||||
|
||||
input [PORT_I_AVL_ADDRESS_WIDTH-1:0] i_avl_address,
|
||||
input i_avl_clk,
|
||||
input i_avl_read,
|
||||
input [PORT_I_AVL_READDATA_CKGEN_WIDTH-1:0] i_avl_readdata_ckgen0,
|
||||
input [PORT_I_AVL_READDATA_CKGEN_WIDTH-1:0] i_avl_readdata_ckgen1,
|
||||
input [PORT_I_AVL_READDATA_COMP_WIDTH-1:0] i_avl_readdata_comp,
|
||||
input [PORT_I_AVL_READDATA_FBRPLL_WIDTH-1:0] i_avl_readdata_fbrpll,
|
||||
input [PORT_I_AVL_READDATA_IOPLL_WIDTH-1:0] i_avl_readdata_iopll0,
|
||||
input [PORT_I_AVL_READDATA_IOPLL_WIDTH-1:0] i_avl_readdata_iopll1,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane0,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane1,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane2,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane3,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane4,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane5,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane6,
|
||||
input [PORT_I_AVL_READDATA_LANE_WIDTH-1:0] i_avl_readdata_lane7,
|
||||
input i_avl_rstn,
|
||||
input i_avl_write,
|
||||
input [PORT_I_AVL_WRITEDATA_WIDTH-1:0] i_avl_writedata,
|
||||
input i_phy_clka,
|
||||
input i_phy_clkb,
|
||||
input i_phy_clksync_a,
|
||||
input i_phy_clksync_b,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa0,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa1,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa2,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa3,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa4,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa5,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa6,
|
||||
input [PORT_I_RB_BASE_ADDRESS_PA_WIDTH-1:0] i_rb_base_address_pa7,
|
||||
input i_rb_ddr_lane_mode_pa0,
|
||||
input i_rb_ddr_lane_mode_pa1,
|
||||
input i_rb_ddr_lane_mode_pa2,
|
||||
input i_rb_ddr_lane_mode_pa3,
|
||||
input i_rb_ddr_lane_mode_pa4,
|
||||
input i_rb_ddr_lane_mode_pa5,
|
||||
input i_rb_ddr_lane_mode_pa6,
|
||||
input i_rb_ddr_lane_mode_pa7,
|
||||
input i_rb_if_sel_pa0,
|
||||
input i_rb_if_sel_pa1,
|
||||
input i_rb_if_sel_pa2,
|
||||
input i_rb_if_sel_pa3,
|
||||
input i_rb_if_sel_pa4,
|
||||
input i_rb_if_sel_pa5,
|
||||
input i_rb_if_sel_pa6,
|
||||
input i_rb_if_sel_pa7,
|
||||
input i_rb_phy_clk_en_pa0,
|
||||
input i_rb_phy_clk_en_pa1,
|
||||
input i_rb_phy_clk_en_pa2,
|
||||
input i_rb_phy_clk_en_pa3,
|
||||
input i_rb_phy_clk_en_pa4,
|
||||
input i_rb_phy_clk_en_pa5,
|
||||
input i_rb_phy_clk_en_pa6,
|
||||
input i_rb_phy_clk_en_pa7,
|
||||
input i_rb_rate_conv_en_pa0,
|
||||
input i_rb_rate_conv_en_pa1,
|
||||
input i_rb_rate_conv_en_pa2,
|
||||
input i_rb_rate_conv_en_pa3,
|
||||
input i_rb_rate_conv_en_pa4,
|
||||
input i_rb_rate_conv_en_pa5,
|
||||
input i_rb_rate_conv_en_pa6,
|
||||
input i_rb_rate_conv_en_pa7,
|
||||
input i_seq_cmd_sync,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_0,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_1,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_2,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_3,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_4,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_5,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_6,
|
||||
input [PORT_I_SEQ_RDDATA_WIDTH-1:0] i_seq_rddata_7,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_0,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_1,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_2,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_3,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_4,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_5,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_6,
|
||||
input [PORT_I_SEQ_RDDATA_VALID_WIDTH-1:0] i_seq_rddata_valid_7,
|
||||
output [PORT_O_AVL_ADDRESS_CKGEN_WIDTH-1:0] o_avl_address_ckgen,
|
||||
output [PORT_O_AVL_ADDRESS_COMP_WIDTH-1:0] o_avl_address_comp,
|
||||
output [PORT_O_AVL_ADDRESS_LANE_WIDTH-1:0] o_avl_address_lane,
|
||||
output [PORT_O_AVL_ADDRESS_PLL_WIDTH-1:0] o_avl_address_pll,
|
||||
output o_avl_clk_ckgen,
|
||||
output o_avl_clk_comp,
|
||||
output o_avl_clk_lane,
|
||||
output o_avl_clk_pll,
|
||||
output [PORT_O_AVL_READDATA_WIDTH-1:0] o_avl_readdata,
|
||||
output o_avl_read_ckgen,
|
||||
output o_avl_read_comp,
|
||||
output o_avl_read_lane,
|
||||
output o_avl_read_pll,
|
||||
output o_avl_rstn_ckgen,
|
||||
output o_avl_rstn_comp,
|
||||
output o_avl_rstn_lane,
|
||||
output o_avl_rstn_pll,
|
||||
output [PORT_O_AVL_WRITEDATA_CKGEN_WIDTH-1:0] o_avl_writedata_ckgen,
|
||||
output [PORT_O_AVL_WRITEDATA_COMP_WIDTH-1:0] o_avl_writedata_comp,
|
||||
output [PORT_O_AVL_WRITEDATA_LANE_WIDTH-1:0] o_avl_writedata_lane,
|
||||
output [PORT_O_AVL_WRITEDATA_PLL_WIDTH-1:0] o_avl_writedata_pll,
|
||||
output o_avl_write_ckgen,
|
||||
output o_avl_write_comp,
|
||||
output o_avl_write_lane,
|
||||
output o_avl_write_pll,
|
||||
output o_seq_cmd_sync,
|
||||
output o_seq_en_0,
|
||||
output o_seq_en_1,
|
||||
output o_seq_en_2,
|
||||
output o_seq_en_3,
|
||||
output o_seq_en_4,
|
||||
output o_seq_en_5,
|
||||
output o_seq_en_6,
|
||||
output o_seq_en_7,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_0,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_1,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_2,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_3,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_4,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_5,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_6,
|
||||
output [PORT_O_SEQ_RDDATA_EN_WIDTH-1:0] o_seq_rddata_en_7,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_0,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_1,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_2,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_3,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_4,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_5,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_6,
|
||||
output [PORT_O_SEQ_RD_RANK_WIDTH-1:0] o_seq_rd_rank_7,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_0,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_1,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_2,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_3,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_4,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_5,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_6,
|
||||
output [PORT_O_SEQ_SUPPRESSION_WIDTH-1:0] o_seq_suppression_7,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_0,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_1,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_2,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_3,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_4,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_5,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_6,
|
||||
output [PORT_O_SEQ_WRDATA_EN_WIDTH-1:0] o_seq_wrdata_en_7,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_0,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_1,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_2,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_3,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_4,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_5,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_6,
|
||||
output [PORT_O_SEQ_WRDATA_WIDTH-1:0] o_seq_wrdata_7,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_0,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_1,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_2,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_3,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_4,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_5,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_6,
|
||||
output [PORT_O_SEQ_WR_DQS_EN_WIDTH-1:0] o_seq_wr_dqs_en_7,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_0,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_1,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_2,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_3,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_4,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_5,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_6,
|
||||
output [PORT_O_SEQ_WR_RANK_WIDTH-1:0] o_seq_wr_rank_7
|
||||
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
import io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_atom_attr_seq::*;
|
||||
|
||||
tennm_seq # (
|
||||
.base_address_ctrl (BASE_ADDRESS_CTRL)
|
||||
) seq (
|
||||
.i_avl_address (i_avl_address),
|
||||
.i_avl_clk (i_avl_clk),
|
||||
.i_avl_read (i_avl_read),
|
||||
.i_avl_readdata_ckgen0 (i_avl_readdata_ckgen0),
|
||||
.i_avl_readdata_ckgen1 (i_avl_readdata_ckgen1),
|
||||
.i_avl_readdata_comp (i_avl_readdata_comp),
|
||||
.i_avl_readdata_fbrpll (i_avl_readdata_fbrpll),
|
||||
.i_avl_readdata_iopll0 (i_avl_readdata_iopll0),
|
||||
.i_avl_readdata_iopll1 (i_avl_readdata_iopll1),
|
||||
.i_avl_readdata_lane0 (i_avl_readdata_lane0),
|
||||
.i_avl_readdata_lane1 (i_avl_readdata_lane1),
|
||||
.i_avl_readdata_lane2 (i_avl_readdata_lane2),
|
||||
.i_avl_readdata_lane3 (i_avl_readdata_lane3),
|
||||
.i_avl_readdata_lane4 (i_avl_readdata_lane4),
|
||||
.i_avl_readdata_lane5 (i_avl_readdata_lane5),
|
||||
.i_avl_readdata_lane6 (i_avl_readdata_lane6),
|
||||
.i_avl_readdata_lane7 (i_avl_readdata_lane7),
|
||||
.i_avl_rstn (i_avl_rstn),
|
||||
.i_avl_write (i_avl_write),
|
||||
.i_avl_writedata (i_avl_writedata),
|
||||
.i_phy_clka (i_phy_clka),
|
||||
.i_phy_clkb (i_phy_clkb),
|
||||
.i_phy_clksync_a (i_phy_clksync_a),
|
||||
.i_phy_clksync_b (i_phy_clksync_b),
|
||||
.i_rb_base_address_pa0 (i_rb_base_address_pa0),
|
||||
.i_rb_base_address_pa1 (i_rb_base_address_pa1),
|
||||
.i_rb_base_address_pa2 (i_rb_base_address_pa2),
|
||||
.i_rb_base_address_pa3 (i_rb_base_address_pa3),
|
||||
.i_rb_base_address_pa4 (i_rb_base_address_pa4),
|
||||
.i_rb_base_address_pa5 (i_rb_base_address_pa5),
|
||||
.i_rb_base_address_pa6 (i_rb_base_address_pa6),
|
||||
.i_rb_base_address_pa7 (i_rb_base_address_pa7),
|
||||
.i_rb_ddr_lane_mode_pa0 (i_rb_ddr_lane_mode_pa0),
|
||||
.i_rb_ddr_lane_mode_pa1 (i_rb_ddr_lane_mode_pa1),
|
||||
.i_rb_ddr_lane_mode_pa2 (i_rb_ddr_lane_mode_pa2),
|
||||
.i_rb_ddr_lane_mode_pa3 (i_rb_ddr_lane_mode_pa3),
|
||||
.i_rb_ddr_lane_mode_pa4 (i_rb_ddr_lane_mode_pa4),
|
||||
.i_rb_ddr_lane_mode_pa5 (i_rb_ddr_lane_mode_pa5),
|
||||
.i_rb_ddr_lane_mode_pa6 (i_rb_ddr_lane_mode_pa6),
|
||||
.i_rb_ddr_lane_mode_pa7 (i_rb_ddr_lane_mode_pa7),
|
||||
.i_rb_if_sel_pa0 (i_rb_if_sel_pa0),
|
||||
.i_rb_if_sel_pa1 (i_rb_if_sel_pa1),
|
||||
.i_rb_if_sel_pa2 (i_rb_if_sel_pa2),
|
||||
.i_rb_if_sel_pa3 (i_rb_if_sel_pa3),
|
||||
.i_rb_if_sel_pa4 (i_rb_if_sel_pa4),
|
||||
.i_rb_if_sel_pa5 (i_rb_if_sel_pa5),
|
||||
.i_rb_if_sel_pa6 (i_rb_if_sel_pa6),
|
||||
.i_rb_if_sel_pa7 (i_rb_if_sel_pa7),
|
||||
.i_rb_phy_clk_en_pa0 (i_rb_phy_clk_en_pa0),
|
||||
.i_rb_phy_clk_en_pa1 (i_rb_phy_clk_en_pa1),
|
||||
.i_rb_phy_clk_en_pa2 (i_rb_phy_clk_en_pa2),
|
||||
.i_rb_phy_clk_en_pa3 (i_rb_phy_clk_en_pa3),
|
||||
.i_rb_phy_clk_en_pa4 (i_rb_phy_clk_en_pa4),
|
||||
.i_rb_phy_clk_en_pa5 (i_rb_phy_clk_en_pa5),
|
||||
.i_rb_phy_clk_en_pa6 (i_rb_phy_clk_en_pa6),
|
||||
.i_rb_phy_clk_en_pa7 (i_rb_phy_clk_en_pa7),
|
||||
.i_rb_rate_conv_en_pa0 (i_rb_rate_conv_en_pa0),
|
||||
.i_rb_rate_conv_en_pa1 (i_rb_rate_conv_en_pa1),
|
||||
.i_rb_rate_conv_en_pa2 (i_rb_rate_conv_en_pa2),
|
||||
.i_rb_rate_conv_en_pa3 (i_rb_rate_conv_en_pa3),
|
||||
.i_rb_rate_conv_en_pa4 (i_rb_rate_conv_en_pa4),
|
||||
.i_rb_rate_conv_en_pa5 (i_rb_rate_conv_en_pa5),
|
||||
.i_rb_rate_conv_en_pa6 (i_rb_rate_conv_en_pa6),
|
||||
.i_rb_rate_conv_en_pa7 (i_rb_rate_conv_en_pa7),
|
||||
.i_seq_cmd_sync (i_seq_cmd_sync),
|
||||
.i_seq_rddata_0 (i_seq_rddata_0),
|
||||
.i_seq_rddata_1 (i_seq_rddata_1),
|
||||
.i_seq_rddata_2 (i_seq_rddata_2),
|
||||
.i_seq_rddata_3 (i_seq_rddata_3),
|
||||
.i_seq_rddata_4 (i_seq_rddata_4),
|
||||
.i_seq_rddata_5 (i_seq_rddata_5),
|
||||
.i_seq_rddata_6 (i_seq_rddata_6),
|
||||
.i_seq_rddata_7 (i_seq_rddata_7),
|
||||
.i_seq_rddata_valid_0 (i_seq_rddata_valid_0),
|
||||
.i_seq_rddata_valid_1 (i_seq_rddata_valid_1),
|
||||
.i_seq_rddata_valid_2 (i_seq_rddata_valid_2),
|
||||
.i_seq_rddata_valid_3 (i_seq_rddata_valid_3),
|
||||
.i_seq_rddata_valid_4 (i_seq_rddata_valid_4),
|
||||
.i_seq_rddata_valid_5 (i_seq_rddata_valid_5),
|
||||
.i_seq_rddata_valid_6 (i_seq_rddata_valid_6),
|
||||
.i_seq_rddata_valid_7 (i_seq_rddata_valid_7),
|
||||
.o_avl_address_ckgen (o_avl_address_ckgen),
|
||||
.o_avl_address_comp (o_avl_address_comp),
|
||||
.o_avl_address_lane (o_avl_address_lane),
|
||||
.o_avl_address_pll (o_avl_address_pll),
|
||||
.o_avl_clk_ckgen (o_avl_clk_ckgen),
|
||||
.o_avl_clk_comp (o_avl_clk_comp),
|
||||
.o_avl_clk_lane (o_avl_clk_lane),
|
||||
.o_avl_clk_pll (o_avl_clk_pll),
|
||||
.o_avl_readdata (o_avl_readdata),
|
||||
.o_avl_read_ckgen (o_avl_read_ckgen),
|
||||
.o_avl_read_comp (o_avl_read_comp),
|
||||
.o_avl_read_lane (o_avl_read_lane),
|
||||
.o_avl_read_pll (o_avl_read_pll),
|
||||
.o_avl_rstn_ckgen (o_avl_rstn_ckgen),
|
||||
.o_avl_rstn_comp (o_avl_rstn_comp),
|
||||
.o_avl_rstn_lane (o_avl_rstn_lane),
|
||||
.o_avl_rstn_pll (o_avl_rstn_pll),
|
||||
.o_avl_writedata_ckgen (o_avl_writedata_ckgen),
|
||||
.o_avl_writedata_comp (o_avl_writedata_comp),
|
||||
.o_avl_writedata_lane (o_avl_writedata_lane),
|
||||
.o_avl_writedata_pll (o_avl_writedata_pll),
|
||||
.o_avl_write_ckgen (o_avl_write_ckgen),
|
||||
.o_avl_write_comp (o_avl_write_comp),
|
||||
.o_avl_write_lane (o_avl_write_lane),
|
||||
.o_avl_write_pll (o_avl_write_pll),
|
||||
.o_seq_cmd_sync (o_seq_cmd_sync),
|
||||
.o_seq_en_0 (o_seq_en_0),
|
||||
.o_seq_en_1 (o_seq_en_1),
|
||||
.o_seq_en_2 (o_seq_en_2),
|
||||
.o_seq_en_3 (o_seq_en_3),
|
||||
.o_seq_en_4 (o_seq_en_4),
|
||||
.o_seq_en_5 (o_seq_en_5),
|
||||
.o_seq_en_6 (o_seq_en_6),
|
||||
.o_seq_en_7 (o_seq_en_7),
|
||||
.o_seq_rddata_en_0 (o_seq_rddata_en_0),
|
||||
.o_seq_rddata_en_1 (o_seq_rddata_en_1),
|
||||
.o_seq_rddata_en_2 (o_seq_rddata_en_2),
|
||||
.o_seq_rddata_en_3 (o_seq_rddata_en_3),
|
||||
.o_seq_rddata_en_4 (o_seq_rddata_en_4),
|
||||
.o_seq_rddata_en_5 (o_seq_rddata_en_5),
|
||||
.o_seq_rddata_en_6 (o_seq_rddata_en_6),
|
||||
.o_seq_rddata_en_7 (o_seq_rddata_en_7),
|
||||
.o_seq_rd_rank_0 (o_seq_rd_rank_0),
|
||||
.o_seq_rd_rank_1 (o_seq_rd_rank_1),
|
||||
.o_seq_rd_rank_2 (o_seq_rd_rank_2),
|
||||
.o_seq_rd_rank_3 (o_seq_rd_rank_3),
|
||||
.o_seq_rd_rank_4 (o_seq_rd_rank_4),
|
||||
.o_seq_rd_rank_5 (o_seq_rd_rank_5),
|
||||
.o_seq_rd_rank_6 (o_seq_rd_rank_6),
|
||||
.o_seq_rd_rank_7 (o_seq_rd_rank_7),
|
||||
.o_seq_suppression_0 (o_seq_suppression_0),
|
||||
.o_seq_suppression_1 (o_seq_suppression_1),
|
||||
.o_seq_suppression_2 (o_seq_suppression_2),
|
||||
.o_seq_suppression_3 (o_seq_suppression_3),
|
||||
.o_seq_suppression_4 (o_seq_suppression_4),
|
||||
.o_seq_suppression_5 (o_seq_suppression_5),
|
||||
.o_seq_suppression_6 (o_seq_suppression_6),
|
||||
.o_seq_suppression_7 (o_seq_suppression_7),
|
||||
.o_seq_wrdata_0 (o_seq_wrdata_0),
|
||||
.o_seq_wrdata_1 (o_seq_wrdata_1),
|
||||
.o_seq_wrdata_2 (o_seq_wrdata_2),
|
||||
.o_seq_wrdata_3 (o_seq_wrdata_3),
|
||||
.o_seq_wrdata_4 (o_seq_wrdata_4),
|
||||
.o_seq_wrdata_5 (o_seq_wrdata_5),
|
||||
.o_seq_wrdata_6 (o_seq_wrdata_6),
|
||||
.o_seq_wrdata_7 (o_seq_wrdata_7),
|
||||
.o_seq_wrdata_en_0 (o_seq_wrdata_en_0),
|
||||
.o_seq_wrdata_en_1 (o_seq_wrdata_en_1),
|
||||
.o_seq_wrdata_en_2 (o_seq_wrdata_en_2),
|
||||
.o_seq_wrdata_en_3 (o_seq_wrdata_en_3),
|
||||
.o_seq_wrdata_en_4 (o_seq_wrdata_en_4),
|
||||
.o_seq_wrdata_en_5 (o_seq_wrdata_en_5),
|
||||
.o_seq_wrdata_en_6 (o_seq_wrdata_en_6),
|
||||
.o_seq_wrdata_en_7 (o_seq_wrdata_en_7),
|
||||
.o_seq_wr_dqs_en_0 (o_seq_wr_dqs_en_0),
|
||||
.o_seq_wr_dqs_en_1 (o_seq_wr_dqs_en_1),
|
||||
.o_seq_wr_dqs_en_2 (o_seq_wr_dqs_en_2),
|
||||
.o_seq_wr_dqs_en_3 (o_seq_wr_dqs_en_3),
|
||||
.o_seq_wr_dqs_en_4 (o_seq_wr_dqs_en_4),
|
||||
.o_seq_wr_dqs_en_5 (o_seq_wr_dqs_en_5),
|
||||
.o_seq_wr_dqs_en_6 (o_seq_wr_dqs_en_6),
|
||||
.o_seq_wr_dqs_en_7 (o_seq_wr_dqs_en_7),
|
||||
.o_seq_wr_rank_0 (o_seq_wr_rank_0),
|
||||
.o_seq_wr_rank_1 (o_seq_wr_rank_1),
|
||||
.o_seq_wr_rank_2 (o_seq_wr_rank_2),
|
||||
.o_seq_wr_rank_3 (o_seq_wr_rank_3),
|
||||
.o_seq_wr_rank_4 (o_seq_wr_rank_4),
|
||||
.o_seq_wr_rank_5 (o_seq_wr_rank_5),
|
||||
.o_seq_wr_rank_6 (o_seq_wr_rank_6),
|
||||
.o_seq_wr_rank_7 (o_seq_wr_rank_7)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
+723
@@ -0,0 +1,723 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// This module forms the calibration IP that is responsible for calibrating
|
||||
// or reconfiguring IPs like EMIF, PHYLite and PLLs. It also provides interface
|
||||
// for any user calibration/reconfiguration IPs or debug IPs
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
//
|
||||
// AXI-L via -------------<->----------------------.
|
||||
// NOC ________ _________ ______|________ ________________
|
||||
// | | | | | | | |
|
||||
// | |-<->-| FA |-<->-| | | |-<->-PERIPH0
|
||||
// | | |_______| | | | |
|
||||
// AXI-L to -<->-| GB | _______ | IOSSM |-<->-| SEQ |-<->-PERIPH1
|
||||
// fabric | | | | | | | |
|
||||
// | |-<->-| FA |-<->-| | | |-<->-PLL0,PLL1,PLL2
|
||||
// |______| |_______| |_____________| |_______________|
|
||||
//
|
||||
//
|
||||
|
||||
`define declare_pa_signals(X) \
|
||||
logic seq_to_pa``X``__en ; \
|
||||
logic [95:0] seq_to_pa``X``__wrdata ; \
|
||||
logic [ 3:0] seq_to_pa``X``__wrdata_en ; \
|
||||
logic [ 3:0] seq_to_pa``X``__wr_dqs_en ; \
|
||||
logic [ 3:0] seq_to_pa``X``__rddata_en ; \
|
||||
logic [ 7:0] seq_to_pa``X``__wr_rank ; \
|
||||
logic [ 7:0] seq_to_pa``X``__rd_rank ; \
|
||||
logic [11:0] seq_to_pa``X``__suppression ; \
|
||||
logic [95:0] periph0_pa``X``_to_seq__rddata , periph1_pa``X``_to_seq__rddata ; \
|
||||
logic [ 3:0] periph0_pa``X``_to_seq__rddata_valid , periph1_pa``X``_to_seq__rddata_valid ; \
|
||||
logic periph0_pa``X``_to_seq__rb_if_sel , periph1_pa``X``_to_seq__rb_if_sel ; \
|
||||
logic periph0_pa``X``_to_seq__rb_phy_clk_en , periph1_pa``X``_to_seq__rb_phy_clk_en ; \
|
||||
logic periph0_pa``X``_to_seq__rb_rate_conv_en , periph1_pa``X``_to_seq__rb_rate_conv_en ; \
|
||||
logic periph0_pa``X``_to_seq__rb_ddr_lane_mode , periph1_pa``X``_to_seq__rb_ddr_lane_mode ; \
|
||||
logic [10:0] periph0_pa``X``_to_seq__rb_base_address , periph1_pa``X``_to_seq__rb_base_address ;
|
||||
|
||||
`define connect_pa(X) \
|
||||
.o_seq_en_``X`` (seq_to_pa``X``__en ), \
|
||||
.o_seq_wrdata_``X`` (seq_to_pa``X``__wrdata ), \
|
||||
.o_seq_wrdata_en_``X`` (seq_to_pa``X``__wrdata_en ), \
|
||||
.o_seq_wr_dqs_en_``X`` (seq_to_pa``X``__wr_dqs_en ), \
|
||||
.o_seq_rddata_en_``X`` (seq_to_pa``X``__rddata_en ), \
|
||||
.o_seq_wr_rank_``X`` (seq_to_pa``X``__wr_rank ), \
|
||||
.o_seq_rd_rank_``X`` (seq_to_pa``X``__rd_rank ), \
|
||||
.o_seq_suppression_``X`` (seq_to_pa``X``__suppression ), \
|
||||
.i_seq_rddata_``X`` (periph0_pa``X``_to_seq__rddata | periph1_pa``X``_to_seq__rddata ), \
|
||||
.i_seq_rddata_valid_``X`` (periph0_pa``X``_to_seq__rddata_valid | periph1_pa``X``_to_seq__rddata_valid ), \
|
||||
.i_rb_if_sel_pa``X`` ( periph1_pa``X``_to_seq__rb_if_sel ), \
|
||||
.i_rb_phy_clk_en_pa``X`` (periph0_pa``X``_to_seq__rb_phy_clk_en | periph1_pa``X``_to_seq__rb_phy_clk_en ), \
|
||||
.i_rb_rate_conv_en_pa``X`` (periph0_pa``X``_to_seq__rb_rate_conv_en | periph1_pa``X``_to_seq__rb_rate_conv_en ), \
|
||||
.i_rb_ddr_lane_mode_pa``X`` (periph0_pa``X``_to_seq__rb_ddr_lane_mode | periph1_pa``X``_to_seq__rb_ddr_lane_mode ), \
|
||||
.i_rb_base_address_pa``X`` (periph0_pa``X``_to_seq__rb_base_address | periph1_pa``X``_to_seq__rb_base_address ),
|
||||
|
||||
// altera message_off 16788
|
||||
module io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_cal_arch_fp_top #(
|
||||
|
||||
parameter NUM_CALBUS_PERIPHS = 1,
|
||||
parameter NUM_CALBUS_PLLS = 1,
|
||||
localparam PARAM_TABLE_WIDTH = 16384,
|
||||
parameter bit [ 16384-1:0] PARAMETER_TABLE_0 = 0,
|
||||
parameter bit [ 16384-1:0] PARAMETER_TABLE_1 = 0,
|
||||
parameter PORT_AXIL_ADDRESS_WIDTH = 32,
|
||||
localparam PORT_AXIL_DATA_WIDTH = 32,
|
||||
parameter PORT_M_AXIL_ENABLE = 0
|
||||
|
||||
) (
|
||||
|
||||
output [1341:0] periph_calbus_0,
|
||||
input [1314:0] periph_calbus_readdata_0,
|
||||
input [2*PARAM_TABLE_WIDTH-1:0] periph_calbus_param_table_0,
|
||||
|
||||
output [1341:0] periph_calbus_1,
|
||||
input [1314:0] periph_calbus_readdata_1,
|
||||
input [2*PARAM_TABLE_WIDTH-1:0] periph_calbus_param_table_1,
|
||||
|
||||
output [ 57:0] pll_calbus_0,
|
||||
input [ 31:0] pll_calbus_readdata_0,
|
||||
|
||||
output [ 57:0] pll_calbus_1,
|
||||
input [ 31:0] pll_calbus_readdata_1,
|
||||
|
||||
output [ 57:0] pll_calbus_2,
|
||||
input [ 31:0] pll_calbus_readdata_2,
|
||||
|
||||
input [7:0] ls_to_cal,
|
||||
output [7:0] ls_from_cal,
|
||||
input fbr_c2f_rst_n,
|
||||
//// User/Debug Interface via NoC
|
||||
input tniul_rst_n ,
|
||||
output s0_noc_axi4lite_clk ,
|
||||
output s0_noc_axi4lite_rst_n ,
|
||||
input [PORT_AXIL_ADDRESS_WIDTH-1:0] s0_noc_axi4lite_awaddr ,
|
||||
input s0_noc_axi4lite_awvalid ,
|
||||
output s0_noc_axi4lite_awready ,
|
||||
input [PORT_AXIL_ADDRESS_WIDTH-1:0] s0_noc_axi4lite_araddr ,
|
||||
input s0_noc_axi4lite_arvalid ,
|
||||
output s0_noc_axi4lite_arready ,
|
||||
input [PORT_AXIL_DATA_WIDTH-1:0] s0_noc_axi4lite_wdata ,
|
||||
input s0_noc_axi4lite_wvalid ,
|
||||
output s0_noc_axi4lite_wready ,
|
||||
output [1:0] s0_noc_axi4lite_rresp ,
|
||||
output [PORT_AXIL_DATA_WIDTH-1:0] s0_noc_axi4lite_rdata ,
|
||||
output s0_noc_axi4lite_rvalid ,
|
||||
input s0_noc_axi4lite_rready ,
|
||||
output [1:0] s0_noc_axi4lite_bresp ,
|
||||
output s0_noc_axi4lite_bvalid ,
|
||||
input s0_noc_axi4lite_bready ,
|
||||
input [2:0] s0_noc_axi4lite_awprot ,
|
||||
input [2:0] s0_noc_axi4lite_arprot ,
|
||||
input [(PORT_AXIL_DATA_WIDTH/8)-1:0] s0_noc_axi4lite_wstrb ,
|
||||
|
||||
//// User/Debug Interface directy to Fabric
|
||||
input s0_axi4lite_clk ,
|
||||
input s0_axi4lite_rst_n ,
|
||||
input [PORT_AXIL_ADDRESS_WIDTH-1:0] s0_axi4lite_awaddr ,
|
||||
input s0_axi4lite_awvalid ,
|
||||
output s0_axi4lite_awready ,
|
||||
input [PORT_AXIL_ADDRESS_WIDTH-1:0] s0_axi4lite_araddr ,
|
||||
input s0_axi4lite_arvalid ,
|
||||
output s0_axi4lite_arready ,
|
||||
input [PORT_AXIL_DATA_WIDTH-1:0] s0_axi4lite_wdata ,
|
||||
input s0_axi4lite_wvalid ,
|
||||
output s0_axi4lite_wready ,
|
||||
output [1:0] s0_axi4lite_rresp ,
|
||||
output [PORT_AXIL_DATA_WIDTH-1:0] s0_axi4lite_rdata ,
|
||||
output s0_axi4lite_rvalid ,
|
||||
input s0_axi4lite_rready ,
|
||||
output [1:0] s0_axi4lite_bresp ,
|
||||
output s0_axi4lite_bvalid ,
|
||||
input s0_axi4lite_bready ,
|
||||
|
||||
//// User Interface directy from Fabric (M)
|
||||
//output m0_axi4lite_clk ,
|
||||
output [PORT_AXIL_ADDRESS_WIDTH-1:0] m0_axi4lite_awaddr ,
|
||||
output m0_axi4lite_awvalid ,
|
||||
input m0_axi4lite_awready ,
|
||||
output [PORT_AXIL_ADDRESS_WIDTH-1:0] m0_axi4lite_araddr ,
|
||||
output m0_axi4lite_arvalid ,
|
||||
input m0_axi4lite_arready ,
|
||||
output [PORT_AXIL_DATA_WIDTH-1:0] m0_axi4lite_wdata ,
|
||||
output m0_axi4lite_wvalid ,
|
||||
input m0_axi4lite_wready ,
|
||||
input [1:0] m0_axi4lite_rresp ,
|
||||
input [PORT_AXIL_DATA_WIDTH-1:0] m0_axi4lite_rdata ,
|
||||
input m0_axi4lite_rvalid ,
|
||||
output m0_axi4lite_rready ,
|
||||
input [1:0] m0_axi4lite_bresp ,
|
||||
input m0_axi4lite_bvalid ,
|
||||
output m0_axi4lite_bready ,
|
||||
output [2:0] m0_axi4lite_awprot ,
|
||||
output [2:0] m0_axi4lite_arprot ,
|
||||
output [(PORT_AXIL_DATA_WIDTH/8)-1:0] m0_axi4lite_wstrb ,
|
||||
|
||||
|
||||
input [2:0] s0_axi4lite_awprot ,
|
||||
input [2:0] s0_axi4lite_arprot ,
|
||||
input [(PORT_AXIL_DATA_WIDTH/8)-1:0] s0_axi4lite_wstrb
|
||||
|
||||
|
||||
// Core IRQ signals
|
||||
//TODO: Enable the s0_irq port.
|
||||
|
||||
);
|
||||
timeunit 1ns;
|
||||
timeprecision 1ps;
|
||||
|
||||
logic iossm_to_seq__avl_rstn ;
|
||||
logic iossm_to_seq__avl_clk ;
|
||||
logic iossm_to_seq__avl_write ;
|
||||
logic iossm_to_seq__avl_read ;
|
||||
logic [21:0] iossm_to_seq__avl_address ;
|
||||
logic [31:0] iossm_to_seq__avl_writedata;
|
||||
wire [31:0] seq_to_iossm__avl_readdata ;
|
||||
|
||||
logic seq_to_comp__avl_rstn ;
|
||||
logic seq_to_comp__avl_clk ;
|
||||
logic seq_to_comp__avl_write ;
|
||||
logic seq_to_comp__avl_read ;
|
||||
logic [21:0] seq_to_comp__avl_address ;
|
||||
logic [31:0] seq_to_comp__avl_writedata ;
|
||||
wire [31:0] comp_to_seq__avl_readdata ;
|
||||
|
||||
logic seq_to_periph__avl_rstn ;
|
||||
logic seq_to_periph__avl_clk ;
|
||||
logic seq_to_periph__avl_write ;
|
||||
logic seq_to_periph__avl_read ;
|
||||
logic [21:0] seq_to_periph__avl_address ;
|
||||
logic [31:0] seq_to_periph__avl_writedata ;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane0 , periph1_to_seq__avl_readdata_lane0;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane1 , periph1_to_seq__avl_readdata_lane1;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane2 , periph1_to_seq__avl_readdata_lane2;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane3 , periph1_to_seq__avl_readdata_lane3;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane4 , periph1_to_seq__avl_readdata_lane4;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane5 , periph1_to_seq__avl_readdata_lane5;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane6 , periph1_to_seq__avl_readdata_lane6;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_lane7 , periph1_to_seq__avl_readdata_lane7;
|
||||
logic seq_to_pll__avl_rstn ;
|
||||
logic seq_to_pll__avl_clk ;
|
||||
logic seq_to_pll__avl_write ;
|
||||
logic seq_to_pll__avl_read ;
|
||||
logic [21:0] seq_to_pll__avl_address ;
|
||||
logic [31:0] seq_to_pll__avl_writedata;
|
||||
wire [31:0] pll0_to_seq__avl_readdata , periph0_to_seq__avl_readdata_pll ;
|
||||
wire [31:0] pll1_to_seq__avl_readdata , periph1_to_seq__avl_readdata_pll ;
|
||||
wire [31:0] pll2_to_seq__avl_readdata ;
|
||||
logic seq_to_ckgen__avl_rstn ;
|
||||
logic seq_to_ckgen__avl_clk ;
|
||||
logic seq_to_ckgen__avl_write ;
|
||||
logic seq_to_ckgen__avl_read ;
|
||||
logic [21:0] seq_to_ckgen__avl_address ;
|
||||
logic [31:0] seq_to_ckgen__avl_writedata;
|
||||
wire [31:0] periph0_to_seq__avl_readdata_ckgen , periph1_to_seq__avl_readdata_ckgen ;
|
||||
logic periph0_to_seq__phy_clk;
|
||||
logic periph0_to_seq__phy_clksync;
|
||||
logic periph1_to_seq__phy_clk;
|
||||
logic periph1_to_seq__phy_clksync;
|
||||
`declare_pa_signals(0)
|
||||
`declare_pa_signals(1)
|
||||
`declare_pa_signals(2)
|
||||
`declare_pa_signals(3)
|
||||
`declare_pa_signals(4)
|
||||
`declare_pa_signals(5)
|
||||
`declare_pa_signals(6)
|
||||
`declare_pa_signals(7)
|
||||
|
||||
logic periph0_mc0_to_iossm__irq ;
|
||||
logic periph0_mc1_to_iossm__irq ;
|
||||
logic periph1_mc0_to_iossm__irq ;
|
||||
logic periph1_mc1_to_iossm__irq ;
|
||||
logic iossm_to_mc0__rst_n ;
|
||||
logic iossm_to_mc1__rst_n ;
|
||||
logic iossm_to_mc__clk_en_in ;
|
||||
logic iossm_to_mc__hclk ;
|
||||
logic iossm_to_mc__hresetn ;
|
||||
logic [15:0] iossm_to_mc__haddr ;
|
||||
logic [31:0] iossm_to_mc__hwdata ;
|
||||
logic [2:0] iossm_to_mc__hsize ;
|
||||
logic [2:0] iossm_to_mc__hburst ;
|
||||
logic [1:0] iossm_to_mc__htrans ;
|
||||
logic iossm_to_mc__hsel ;
|
||||
logic iossm_to_mc__hready ;
|
||||
logic iossm_to_mc__hwrite ;
|
||||
logic [31:0] periph0_mc0_to_iossm__hrdata ;
|
||||
logic [1:0] periph0_mc0_to_iossm__hresp ;
|
||||
logic periph0_mc0_to_iossm__hready ;
|
||||
logic [31:0] periph0_mc1_to_iossm__hrdata ;
|
||||
logic [1:0] periph0_mc1_to_iossm__hresp ;
|
||||
logic periph0_mc1_to_iossm__hready ;
|
||||
logic [31:0] periph1_mc0_to_iossm__hrdata ;
|
||||
logic [1:0] periph1_mc0_to_iossm__hresp ;
|
||||
logic periph1_mc0_to_iossm__hready ;
|
||||
logic [31:0] periph1_mc1_to_iossm__hrdata ;
|
||||
logic [1:0] periph1_mc1_to_iossm__hresp ;
|
||||
logic periph1_mc1_to_iossm__hready ;
|
||||
logic iossm_to_pa__i3c_scl ;
|
||||
logic iossm_to_pa__i3c_sda_pp ;
|
||||
logic iossm_to_pa__i3c_sda_tx ;
|
||||
logic iossm_to_pa__i3c_sda_dr_en_n ;
|
||||
logic periph0_pa_to_iossm__i3c_sda_rx ;
|
||||
logic periph1_pa_to_iossm__i3c_sda_rx ;
|
||||
|
||||
logic [39:0] to_fa_ssm_c2p ;
|
||||
logic [39:0] from_fa_ssm_c2p ;
|
||||
logic [19:0] to_fa_ssm_p2c ;
|
||||
logic [19:0] from_fa_ssm_p2c ;
|
||||
|
||||
logic fa_to_hmc__slim_fbr_dfi_init_complete;
|
||||
logic fa_to_hmc__slim_fbr_mc_clk_en;
|
||||
logic fa_to_hmc__wide_fbr_dfi_init_complete;
|
||||
logic fa_to_hmc__wide_fbr_mc_clk_en;
|
||||
logic fa_to_seq__seq_cmd_sync;
|
||||
logic [30:0] iofbradapt_ssm_c2p;
|
||||
logic [5:0] gb_ssm_c2p;
|
||||
|
||||
logic seq_to_fa__seq_cmd_sync;
|
||||
logic [1:0] cpa_to_fa__lock;
|
||||
logic [7:0] iofbradapt_ssm_p2c;
|
||||
|
||||
logic [1:0] cpa_lock;
|
||||
logic [2:0] dummy_unused;
|
||||
logic [4:0] fa_2_gb_p2c;
|
||||
|
||||
|
||||
|
||||
logic i_phy_clk_fr ;
|
||||
logic i_phy_clk_sync ;
|
||||
logic i_core_clk ;
|
||||
|
||||
assign s0_noc_axi4lite_rst_n = tniul_rst_n;
|
||||
|
||||
|
||||
altera_emif_cal_gearbox_bidir #(
|
||||
.AXI_ADDR_WIDTH(PORT_AXIL_ADDRESS_WIDTH),
|
||||
.AXI_DATA_WIDTH(PORT_AXIL_DATA_WIDTH)
|
||||
) inst_gearbox (
|
||||
.axi_clk(s0_axi4lite_clk),
|
||||
.axi_rst_n(s0_axi4lite_rst_n),
|
||||
.c2f_rst_n(PORT_M_AXIL_ENABLE ? fbr_c2f_rst_n : s0_axi4lite_rst_n),
|
||||
|
||||
// AXI-L S INF
|
||||
.axi_awvalid(s0_axi4lite_awvalid),
|
||||
.axi_awready(s0_axi4lite_awready),
|
||||
.axi_awaddr(s0_axi4lite_awaddr),
|
||||
|
||||
.axi_arvalid(s0_axi4lite_arvalid),
|
||||
.axi_arready(s0_axi4lite_arready),
|
||||
.axi_araddr(s0_axi4lite_araddr),
|
||||
|
||||
.axi_wvalid(s0_axi4lite_wvalid),
|
||||
.axi_wready(s0_axi4lite_wready),
|
||||
.axi_wdata(s0_axi4lite_wdata),
|
||||
|
||||
.axi_rvalid(s0_axi4lite_rvalid),
|
||||
.axi_rready(s0_axi4lite_rready),
|
||||
.axi_rresp(s0_axi4lite_rresp),
|
||||
.axi_rdata(s0_axi4lite_rdata),
|
||||
|
||||
.axi_bvalid(s0_axi4lite_bvalid),
|
||||
.axi_bready(s0_axi4lite_bready),
|
||||
.axi_bresp(s0_axi4lite_bresp),
|
||||
|
||||
// AXI-L M INF
|
||||
|
||||
.m_axi_awvalid(m0_axi4lite_awvalid),
|
||||
.m_axi_awready(m0_axi4lite_awready),
|
||||
.m_axi_awaddr(m0_axi4lite_awaddr),
|
||||
|
||||
.m_axi_arvalid(m0_axi4lite_arvalid),
|
||||
.m_axi_arready(m0_axi4lite_arready),
|
||||
.m_axi_araddr(m0_axi4lite_araddr),
|
||||
|
||||
.m_axi_wvalid(m0_axi4lite_wvalid),
|
||||
.m_axi_wready(m0_axi4lite_wready),
|
||||
.m_axi_wdata(m0_axi4lite_wdata),
|
||||
|
||||
.m_axi_rvalid(m0_axi4lite_rvalid),
|
||||
.m_axi_rready(m0_axi4lite_rready),
|
||||
.m_axi_rresp(m0_axi4lite_rresp),
|
||||
.m_axi_rdata(m0_axi4lite_rdata),
|
||||
|
||||
.m_axi_bvalid(m0_axi4lite_bvalid),
|
||||
.m_axi_bready(m0_axi4lite_bready),
|
||||
.m_axi_bresp(m0_axi4lite_bresp),
|
||||
|
||||
// IOSSM C2P/P2C Interface
|
||||
.ssm_c2p(gb_ssm_c2p), //[4:0]
|
||||
.ssm_p2c(fa_2_gb_p2c[4:0])
|
||||
);
|
||||
|
||||
assign m0_axi4lite_awprot = '0;
|
||||
assign m0_axi4lite_arprot = '0;
|
||||
assign m0_axi4lite_wstrb = { (PORT_AXIL_DATA_WIDTH/8) {1'b1} };
|
||||
|
||||
assign i_phy_clk_fr = periph0_to_seq__phy_clk;
|
||||
assign i_phy_clk_sync = periph0_to_seq__phy_clksync;
|
||||
|
||||
stdfn_inst_fa_c2p_ssm #(
|
||||
.IS_USED(1),
|
||||
.SSM_C2P_DATA_MODE("SSM_C2P_DATA_MODE_BYPASS"),
|
||||
.FA_CORE_PERIPH_CLK_SEL_DATA_MODE("FA_CORE_PERIPH_CLK_SEL_DATA_MODE_CORECLK"),
|
||||
.SSM_P2C_DATA_MODE("SSM_P2C_DATA_MODE_BYPASS")
|
||||
)
|
||||
u_ssm_fa (
|
||||
.i_core_clk (ls_to_cal[5]),
|
||||
.i_ssm_c2p (to_fa_ssm_c2p ),
|
||||
.o_ssm_c2p (from_fa_ssm_c2p),
|
||||
.i_phy_clk_fr (i_phy_clk_fr),
|
||||
.i_phy_clk_sync (i_phy_clk_sync),
|
||||
.i_ssm_p2c (to_fa_ssm_p2c),
|
||||
.o_ssm_p2c (from_fa_ssm_p2c)
|
||||
);
|
||||
|
||||
|
||||
assign to_fa_ssm_c2p = { 4'h0,
|
||||
ls_to_cal[4:0],
|
||||
25'h0,
|
||||
gb_ssm_c2p
|
||||
};
|
||||
|
||||
assign { fa_to_hmc__slim_fbr_dfi_init_complete,
|
||||
fa_to_hmc__slim_fbr_mc_clk_en,
|
||||
fa_to_hmc__wide_fbr_dfi_init_complete,
|
||||
fa_to_hmc__wide_fbr_mc_clk_en,
|
||||
fa_to_seq__seq_cmd_sync,
|
||||
iofbradapt_ssm_c2p
|
||||
} = from_fa_ssm_c2p[35:0];
|
||||
|
||||
assign to_fa_ssm_p2c = { 9'h0,
|
||||
seq_to_fa__seq_cmd_sync,
|
||||
cpa_to_fa__lock,
|
||||
iofbradapt_ssm_p2c
|
||||
};
|
||||
|
||||
assign { ls_from_cal[0],
|
||||
cpa_lock,
|
||||
dummy_unused,
|
||||
fa_2_gb_p2c
|
||||
} = from_fa_ssm_p2c[10:0];
|
||||
assign ls_from_cal[7:1] = '0;
|
||||
|
||||
io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_stdfn_inst_iossm #(
|
||||
) u_iossm (
|
||||
.iofbradapt_ssm_p2c (iofbradapt_ssm_p2c),
|
||||
.iofbradapt_ssm_c2p (iofbradapt_ssm_c2p),
|
||||
.c2p_clk (s0_axi4lite_clk),
|
||||
|
||||
.axil_clk (s0_noc_axi4lite_clk ),
|
||||
.axil_wready (s0_noc_axi4lite_wready ),
|
||||
.axil_rvalid (s0_noc_axi4lite_rvalid ),
|
||||
.axil_rresp (s0_noc_axi4lite_rresp ),
|
||||
.axil_rdata (s0_noc_axi4lite_rdata ),
|
||||
.axil_bvalid (s0_noc_axi4lite_bvalid ),
|
||||
.axil_bresp (s0_noc_axi4lite_bresp ),
|
||||
.axil_awready (s0_noc_axi4lite_awready),
|
||||
.axil_arready (s0_noc_axi4lite_arready),
|
||||
.axil_wvalid (s0_noc_axi4lite_wvalid ),
|
||||
.axil_wstrb (s0_noc_axi4lite_wstrb ),
|
||||
.axil_wdata (s0_noc_axi4lite_wdata ),
|
||||
.axil_rready (s0_noc_axi4lite_rready ),
|
||||
.axil_bready (s0_noc_axi4lite_bready ),
|
||||
.axil_awvalid (s0_noc_axi4lite_awvalid),
|
||||
.axil_awaddr (s0_noc_axi4lite_awaddr ),
|
||||
.axil_arvalid (s0_noc_axi4lite_arvalid),
|
||||
.axil_araddr (s0_noc_axi4lite_araddr ),
|
||||
|
||||
.calbus0_rst_n (iossm_to_seq__avl_rstn ),
|
||||
.calbus0_clock (iossm_to_seq__avl_clk ),
|
||||
.calbus0_write (iossm_to_seq__avl_write ),
|
||||
.calbus0_read (iossm_to_seq__avl_read ),
|
||||
.calbus0_addr (iossm_to_seq__avl_address ),
|
||||
.calbus0_writedata (iossm_to_seq__avl_writedata),
|
||||
.calbus0_readdata (seq_to_iossm__avl_readdata ),
|
||||
|
||||
.mc0_irq (periph0_mc0_to_iossm__irq | periph1_mc0_to_iossm__irq ),
|
||||
.mc1_irq (periph0_mc1_to_iossm__irq | periph1_mc1_to_iossm__irq ),
|
||||
.mc0_rst_n (iossm_to_mc0__rst_n ),
|
||||
.mc1_rst_n (iossm_to_mc1__rst_n ),
|
||||
.clk_en_in (iossm_to_mc__clk_en_in ),
|
||||
.hclk (iossm_to_mc__hclk ),
|
||||
.hresetn (iossm_to_mc__hresetn ),
|
||||
.haddr (iossm_to_mc__haddr ),
|
||||
.hwdata (iossm_to_mc__hwdata ),
|
||||
.hsize (iossm_to_mc__hsize ),
|
||||
.hburst (iossm_to_mc__hburst ),
|
||||
.htrans (iossm_to_mc__htrans ),
|
||||
.hsel (iossm_to_mc__hsel ),
|
||||
.hready (iossm_to_mc__hready ),
|
||||
.hwrite (iossm_to_mc__hwrite ),
|
||||
.mc0_hrdata (periph0_mc0_to_iossm__hrdata | periph1_mc0_to_iossm__hrdata),
|
||||
.mc0_hresp (periph0_mc0_to_iossm__hresp | periph1_mc0_to_iossm__hresp ),
|
||||
.mc0_hreadyout (periph0_mc0_to_iossm__hready | periph1_mc0_to_iossm__hready),
|
||||
.mc1_hrdata (periph0_mc1_to_iossm__hrdata | periph1_mc1_to_iossm__hrdata),
|
||||
.mc1_hresp (periph0_mc1_to_iossm__hresp | periph1_mc1_to_iossm__hresp ),
|
||||
.mc1_hreadyout (periph0_mc1_to_iossm__hready | periph1_mc1_to_iossm__hready),
|
||||
|
||||
// synthesis translate_off
|
||||
.i_sim_param_table_0 (periph_calbus_param_table_0[PARAM_TABLE_WIDTH-1:0]),
|
||||
.i_sim_param_table_1 (NUM_CALBUS_PERIPHS == 1 ? periph_calbus_param_table_0[2*PARAM_TABLE_WIDTH-1:PARAM_TABLE_WIDTH] :
|
||||
periph_calbus_param_table_1[ PARAM_TABLE_WIDTH-1: 0]),
|
||||
// synthesis translate_on
|
||||
.i3c_sda_rx (periph0_pa_to_iossm__i3c_sda_rx),
|
||||
|
||||
.i3c_scl (iossm_to_pa__i3c_scl ),
|
||||
.i3c_sda_pp (iossm_to_pa__i3c_sda_pp ),
|
||||
.i3c_sda_tx (iossm_to_pa__i3c_sda_tx ),
|
||||
.i3c_sda_dr_en_n (iossm_to_pa__i3c_sda_dr_en_n)
|
||||
);
|
||||
|
||||
io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_stdfn_inst_seq #(
|
||||
) u_seq (
|
||||
.i_avl_rstn (iossm_to_seq__avl_rstn ),
|
||||
.i_avl_clk (iossm_to_seq__avl_clk ),
|
||||
.i_avl_write (iossm_to_seq__avl_write ),
|
||||
.i_avl_read (iossm_to_seq__avl_read ),
|
||||
.i_avl_address (iossm_to_seq__avl_address ),
|
||||
.i_avl_writedata (iossm_to_seq__avl_writedata),
|
||||
.o_avl_readdata (seq_to_iossm__avl_readdata ),
|
||||
|
||||
.o_avl_rstn_comp (seq_to_comp__avl_rstn ),
|
||||
.o_avl_clk_comp (seq_to_comp__avl_clk ),
|
||||
.o_avl_write_comp (seq_to_comp__avl_write ),
|
||||
.o_avl_read_comp (seq_to_comp__avl_read ),
|
||||
.o_avl_address_comp (seq_to_comp__avl_address ),
|
||||
.o_avl_writedata_comp (seq_to_comp__avl_writedata),
|
||||
.i_avl_readdata_comp (comp_to_seq__avl_readdata ),
|
||||
|
||||
.o_avl_rstn_lane (seq_to_periph__avl_rstn ),
|
||||
.o_avl_clk_lane (seq_to_periph__avl_clk ),
|
||||
.o_avl_write_lane (seq_to_periph__avl_write ),
|
||||
.o_avl_read_lane (seq_to_periph__avl_read ),
|
||||
.o_avl_address_lane (seq_to_periph__avl_address ),
|
||||
.o_avl_writedata_lane (seq_to_periph__avl_writedata),
|
||||
.i_avl_readdata_lane0 (periph0_to_seq__avl_readdata_lane0 | periph1_to_seq__avl_readdata_lane0),
|
||||
.i_avl_readdata_lane1 (periph0_to_seq__avl_readdata_lane1 | periph1_to_seq__avl_readdata_lane1),
|
||||
.i_avl_readdata_lane2 (periph0_to_seq__avl_readdata_lane2 | periph1_to_seq__avl_readdata_lane2),
|
||||
.i_avl_readdata_lane3 (periph0_to_seq__avl_readdata_lane3 | periph1_to_seq__avl_readdata_lane3),
|
||||
.i_avl_readdata_lane4 (periph0_to_seq__avl_readdata_lane4 | periph1_to_seq__avl_readdata_lane4),
|
||||
.i_avl_readdata_lane5 (periph0_to_seq__avl_readdata_lane5 | periph1_to_seq__avl_readdata_lane5),
|
||||
.i_avl_readdata_lane6 (periph0_to_seq__avl_readdata_lane6 | periph1_to_seq__avl_readdata_lane6),
|
||||
.i_avl_readdata_lane7 (periph0_to_seq__avl_readdata_lane7 | periph1_to_seq__avl_readdata_lane7),
|
||||
|
||||
.o_avl_rstn_pll (seq_to_pll__avl_rstn ),
|
||||
.o_avl_clk_pll (seq_to_pll__avl_clk ),
|
||||
.o_avl_write_pll (seq_to_pll__avl_write ),
|
||||
.o_avl_read_pll (seq_to_pll__avl_read ),
|
||||
.o_avl_address_pll (seq_to_pll__avl_address ),
|
||||
.o_avl_writedata_pll (seq_to_pll__avl_writedata),
|
||||
.i_avl_readdata_iopll0 (pll2_to_seq__avl_readdata | periph0_to_seq__avl_readdata_pll ),
|
||||
.i_avl_readdata_iopll1 (pll1_to_seq__avl_readdata | periph1_to_seq__avl_readdata_pll ),
|
||||
.i_avl_readdata_fbrpll (pll0_to_seq__avl_readdata ),
|
||||
|
||||
.o_avl_rstn_ckgen (seq_to_ckgen__avl_rstn ),
|
||||
.o_avl_clk_ckgen (seq_to_ckgen__avl_clk ),
|
||||
.o_avl_write_ckgen (seq_to_ckgen__avl_write ),
|
||||
.o_avl_read_ckgen (seq_to_ckgen__avl_read ),
|
||||
.o_avl_address_ckgen (seq_to_ckgen__avl_address ),
|
||||
.o_avl_writedata_ckgen (seq_to_ckgen__avl_writedata),
|
||||
.i_avl_readdata_ckgen0 (periph0_to_seq__avl_readdata_ckgen ),
|
||||
.i_avl_readdata_ckgen1 (periph1_to_seq__avl_readdata_ckgen ),
|
||||
|
||||
.i_phy_clka (periph0_to_seq__phy_clk),
|
||||
.i_phy_clksync_a (periph0_to_seq__phy_clksync),
|
||||
.i_phy_clkb (periph1_to_seq__phy_clk),
|
||||
.i_phy_clksync_b (periph1_to_seq__phy_clksync),
|
||||
|
||||
`connect_pa(0)
|
||||
`connect_pa(1)
|
||||
`connect_pa(2)
|
||||
`connect_pa(3)
|
||||
`connect_pa(4)
|
||||
`connect_pa(5)
|
||||
`connect_pa(6)
|
||||
`connect_pa(7)
|
||||
|
||||
.o_seq_cmd_sync (seq_to_fa__seq_cmd_sync),
|
||||
.i_seq_cmd_sync (fa_to_seq__seq_cmd_sync));
|
||||
|
||||
(* altera_attribute = {"-name PRESERVE_FANOUT_FREE_WYSIWYG ON"} *)
|
||||
tennm_compensation_block # (
|
||||
.base_address (PORT_M_AXIL_ENABLE ? 101 : 0)
|
||||
) u_comp_block (
|
||||
// synthesis translate_off
|
||||
.o_avm_readdata_comp (comp_to_seq__avl_readdata ),
|
||||
// synthesis translate_on
|
||||
.avm_clk (seq_to_comp__avl_clk ),
|
||||
.avm_rst_n (seq_to_comp__avl_rstn ),
|
||||
.i_avm_address (seq_to_comp__avl_address ),
|
||||
.i_avm_read (seq_to_comp__avl_read ),
|
||||
.i_avm_write (seq_to_comp__avl_write ),
|
||||
.i_avm_writedata (seq_to_comp__avl_writedata ));
|
||||
|
||||
logic [ 243:0] periph_calbus_0_a;
|
||||
logic [1097:0] periph_calbus_0_b;
|
||||
|
||||
assign periph_calbus_1 = periph_calbus_0;
|
||||
assign periph_calbus_0 = {periph_calbus_0_a,periph_calbus_0_b};
|
||||
|
||||
assign periph_calbus_0_a = { seq_to_periph__avl_rstn ,
|
||||
seq_to_periph__avl_clk ,
|
||||
seq_to_periph__avl_write ,
|
||||
seq_to_periph__avl_read ,
|
||||
seq_to_periph__avl_address ,
|
||||
seq_to_periph__avl_writedata ,
|
||||
seq_to_pll__avl_rstn ,
|
||||
seq_to_pll__avl_clk ,
|
||||
seq_to_pll__avl_write ,
|
||||
seq_to_pll__avl_read ,
|
||||
seq_to_pll__avl_address ,
|
||||
seq_to_pll__avl_writedata ,
|
||||
seq_to_ckgen__avl_rstn ,
|
||||
seq_to_ckgen__avl_clk ,
|
||||
seq_to_ckgen__avl_write ,
|
||||
seq_to_ckgen__avl_read ,
|
||||
seq_to_ckgen__avl_address ,
|
||||
seq_to_ckgen__avl_writedata ,
|
||||
iossm_to_mc__haddr ,
|
||||
iossm_to_mc__hburst ,
|
||||
iossm_to_mc__hclk ,
|
||||
iossm_to_mc__hready ,
|
||||
iossm_to_mc__hresetn ,
|
||||
iossm_to_mc__hsel ,
|
||||
iossm_to_mc__hsize ,
|
||||
iossm_to_mc__htrans ,
|
||||
iossm_to_mc__hwdata ,
|
||||
iossm_to_mc__hwrite ,
|
||||
iossm_to_mc__clk_en_in ,
|
||||
fa_to_hmc__slim_fbr_dfi_init_complete,
|
||||
fa_to_hmc__slim_fbr_mc_clk_en,
|
||||
fa_to_hmc__wide_fbr_dfi_init_complete,
|
||||
fa_to_hmc__wide_fbr_mc_clk_en,
|
||||
iossm_to_pa__i3c_scl ,
|
||||
iossm_to_pa__i3c_sda_pp ,
|
||||
iossm_to_pa__i3c_sda_tx ,
|
||||
iossm_to_pa__i3c_sda_dr_en_n };
|
||||
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
assign periph_calbus_0_b = { seq_to_pa7__en, seq_to_pa7__wrdata, seq_to_pa7__wrdata_en, seq_to_pa7__wr_dqs_en, seq_to_pa7__rddata_en, seq_to_pa7__wr_rank, seq_to_pa7__rd_rank, seq_to_pa7__suppression,
|
||||
seq_to_pa6__en, seq_to_pa6__wrdata, seq_to_pa6__wrdata_en, seq_to_pa6__wr_dqs_en, seq_to_pa6__rddata_en, seq_to_pa6__wr_rank, seq_to_pa6__rd_rank, seq_to_pa6__suppression,
|
||||
seq_to_pa5__en, seq_to_pa5__wrdata, seq_to_pa5__wrdata_en, seq_to_pa5__wr_dqs_en, seq_to_pa5__rddata_en, seq_to_pa5__wr_rank, seq_to_pa5__rd_rank, seq_to_pa5__suppression,
|
||||
seq_to_pa4__en, seq_to_pa4__wrdata, seq_to_pa4__wrdata_en, seq_to_pa4__wr_dqs_en, seq_to_pa4__rddata_en, seq_to_pa4__wr_rank, seq_to_pa4__rd_rank, seq_to_pa4__suppression,
|
||||
seq_to_pa3__en, seq_to_pa3__wrdata, seq_to_pa3__wrdata_en, seq_to_pa3__wr_dqs_en, seq_to_pa3__rddata_en, seq_to_pa3__wr_rank, seq_to_pa3__rd_rank, seq_to_pa3__suppression,
|
||||
seq_to_pa2__en, seq_to_pa2__wrdata, seq_to_pa2__wrdata_en, seq_to_pa2__wr_dqs_en, seq_to_pa2__rddata_en, seq_to_pa2__wr_rank, seq_to_pa2__rd_rank, seq_to_pa2__suppression,
|
||||
seq_to_pa1__en, seq_to_pa1__wrdata, seq_to_pa1__wrdata_en, seq_to_pa1__wr_dqs_en, seq_to_pa1__rddata_en, seq_to_pa1__wr_rank, seq_to_pa1__rd_rank, seq_to_pa1__suppression,
|
||||
seq_to_pa0__en, seq_to_pa0__wrdata, seq_to_pa0__wrdata_en, seq_to_pa0__wr_dqs_en, seq_to_pa0__rddata_en, seq_to_pa0__wr_rank, seq_to_pa0__rd_rank, seq_to_pa0__suppression,
|
||||
iossm_to_mc1__rst_n,
|
||||
iossm_to_mc0__rst_n};
|
||||
|
||||
assign { periph0_to_seq__avl_readdata_lane7 ,
|
||||
periph0_to_seq__avl_readdata_lane6 ,
|
||||
periph0_to_seq__avl_readdata_lane5 ,
|
||||
periph0_to_seq__avl_readdata_lane4 ,
|
||||
periph0_to_seq__avl_readdata_lane3 ,
|
||||
periph0_to_seq__avl_readdata_lane2 ,
|
||||
periph0_to_seq__avl_readdata_lane1 ,
|
||||
periph0_to_seq__avl_readdata_lane0 ,
|
||||
periph0_to_seq__avl_readdata_ckgen ,
|
||||
periph0_to_seq__phy_clk ,
|
||||
periph0_to_seq__phy_clksync ,
|
||||
periph0_to_seq__avl_readdata_pll ,
|
||||
periph0_pa7_to_seq__rddata,periph0_pa7_to_seq__rddata_valid,periph0_pa7_to_seq__rb_if_sel,periph0_pa7_to_seq__rb_phy_clk_en,periph0_pa7_to_seq__rb_rate_conv_en,periph0_pa7_to_seq__rb_ddr_lane_mode,periph0_pa7_to_seq__rb_base_address,
|
||||
periph0_pa6_to_seq__rddata,periph0_pa6_to_seq__rddata_valid,periph0_pa6_to_seq__rb_if_sel,periph0_pa6_to_seq__rb_phy_clk_en,periph0_pa6_to_seq__rb_rate_conv_en,periph0_pa6_to_seq__rb_ddr_lane_mode,periph0_pa6_to_seq__rb_base_address,
|
||||
periph0_pa5_to_seq__rddata,periph0_pa5_to_seq__rddata_valid,periph0_pa5_to_seq__rb_if_sel,periph0_pa5_to_seq__rb_phy_clk_en,periph0_pa5_to_seq__rb_rate_conv_en,periph0_pa5_to_seq__rb_ddr_lane_mode,periph0_pa5_to_seq__rb_base_address,
|
||||
periph0_pa4_to_seq__rddata,periph0_pa4_to_seq__rddata_valid,periph0_pa4_to_seq__rb_if_sel,periph0_pa4_to_seq__rb_phy_clk_en,periph0_pa4_to_seq__rb_rate_conv_en,periph0_pa4_to_seq__rb_ddr_lane_mode,periph0_pa4_to_seq__rb_base_address,
|
||||
periph0_pa3_to_seq__rddata,periph0_pa3_to_seq__rddata_valid,periph0_pa3_to_seq__rb_if_sel,periph0_pa3_to_seq__rb_phy_clk_en,periph0_pa3_to_seq__rb_rate_conv_en,periph0_pa3_to_seq__rb_ddr_lane_mode,periph0_pa3_to_seq__rb_base_address,
|
||||
periph0_pa2_to_seq__rddata,periph0_pa2_to_seq__rddata_valid,periph0_pa2_to_seq__rb_if_sel,periph0_pa2_to_seq__rb_phy_clk_en,periph0_pa2_to_seq__rb_rate_conv_en,periph0_pa2_to_seq__rb_ddr_lane_mode,periph0_pa2_to_seq__rb_base_address,
|
||||
periph0_pa1_to_seq__rddata,periph0_pa1_to_seq__rddata_valid,periph0_pa1_to_seq__rb_if_sel,periph0_pa1_to_seq__rb_phy_clk_en,periph0_pa1_to_seq__rb_rate_conv_en,periph0_pa1_to_seq__rb_ddr_lane_mode,periph0_pa1_to_seq__rb_base_address,
|
||||
periph0_pa0_to_seq__rddata,periph0_pa0_to_seq__rddata_valid,periph0_pa0_to_seq__rb_if_sel,periph0_pa0_to_seq__rb_phy_clk_en,periph0_pa0_to_seq__rb_rate_conv_en,periph0_pa0_to_seq__rb_ddr_lane_mode,periph0_pa0_to_seq__rb_base_address
|
||||
} = periph_calbus_readdata_0[1314:73];
|
||||
|
||||
assign { periph1_to_seq__avl_readdata_lane7 ,
|
||||
periph1_to_seq__avl_readdata_lane6 ,
|
||||
periph1_to_seq__avl_readdata_lane5 ,
|
||||
periph1_to_seq__avl_readdata_lane4 ,
|
||||
periph1_to_seq__avl_readdata_lane3 ,
|
||||
periph1_to_seq__avl_readdata_lane2 ,
|
||||
periph1_to_seq__avl_readdata_lane1 ,
|
||||
periph1_to_seq__avl_readdata_lane0 ,
|
||||
periph1_to_seq__avl_readdata_ckgen ,
|
||||
periph1_to_seq__phy_clk ,
|
||||
periph1_to_seq__phy_clksync ,
|
||||
periph1_to_seq__avl_readdata_pll ,
|
||||
periph1_pa7_to_seq__rddata,periph1_pa7_to_seq__rddata_valid,periph1_pa7_to_seq__rb_if_sel,periph1_pa7_to_seq__rb_phy_clk_en,periph1_pa7_to_seq__rb_rate_conv_en,periph1_pa7_to_seq__rb_ddr_lane_mode,periph1_pa7_to_seq__rb_base_address,
|
||||
periph1_pa6_to_seq__rddata,periph1_pa6_to_seq__rddata_valid,periph1_pa6_to_seq__rb_if_sel,periph1_pa6_to_seq__rb_phy_clk_en,periph1_pa6_to_seq__rb_rate_conv_en,periph1_pa6_to_seq__rb_ddr_lane_mode,periph1_pa6_to_seq__rb_base_address,
|
||||
periph1_pa5_to_seq__rddata,periph1_pa5_to_seq__rddata_valid,periph1_pa5_to_seq__rb_if_sel,periph1_pa5_to_seq__rb_phy_clk_en,periph1_pa5_to_seq__rb_rate_conv_en,periph1_pa5_to_seq__rb_ddr_lane_mode,periph1_pa5_to_seq__rb_base_address,
|
||||
periph1_pa4_to_seq__rddata,periph1_pa4_to_seq__rddata_valid,periph1_pa4_to_seq__rb_if_sel,periph1_pa4_to_seq__rb_phy_clk_en,periph1_pa4_to_seq__rb_rate_conv_en,periph1_pa4_to_seq__rb_ddr_lane_mode,periph1_pa4_to_seq__rb_base_address,
|
||||
periph1_pa3_to_seq__rddata,periph1_pa3_to_seq__rddata_valid,periph1_pa3_to_seq__rb_if_sel,periph1_pa3_to_seq__rb_phy_clk_en,periph1_pa3_to_seq__rb_rate_conv_en,periph1_pa3_to_seq__rb_ddr_lane_mode,periph1_pa3_to_seq__rb_base_address,
|
||||
periph1_pa2_to_seq__rddata,periph1_pa2_to_seq__rddata_valid,periph1_pa2_to_seq__rb_if_sel,periph1_pa2_to_seq__rb_phy_clk_en,periph1_pa2_to_seq__rb_rate_conv_en,periph1_pa2_to_seq__rb_ddr_lane_mode,periph1_pa2_to_seq__rb_base_address,
|
||||
periph1_pa1_to_seq__rddata,periph1_pa1_to_seq__rddata_valid,periph1_pa1_to_seq__rb_if_sel,periph1_pa1_to_seq__rb_phy_clk_en,periph1_pa1_to_seq__rb_rate_conv_en,periph1_pa1_to_seq__rb_ddr_lane_mode,periph1_pa1_to_seq__rb_base_address,
|
||||
periph1_pa0_to_seq__rddata,periph1_pa0_to_seq__rddata_valid,periph1_pa0_to_seq__rb_if_sel,periph1_pa0_to_seq__rb_phy_clk_en,periph1_pa0_to_seq__rb_rate_conv_en,periph1_pa0_to_seq__rb_ddr_lane_mode,periph1_pa0_to_seq__rb_base_address
|
||||
} = periph_calbus_readdata_1[1314:73];
|
||||
// synthesis translate_on
|
||||
|
||||
assign { periph0_mc1_to_iossm__irq ,
|
||||
periph0_mc1_to_iossm__hrdata ,
|
||||
periph0_mc1_to_iossm__hready ,
|
||||
periph0_mc1_to_iossm__hresp ,
|
||||
periph0_mc0_to_iossm__irq ,
|
||||
periph0_mc0_to_iossm__hrdata ,
|
||||
periph0_mc0_to_iossm__hready ,
|
||||
periph0_mc0_to_iossm__hresp ,
|
||||
periph0_pa_to_iossm__i3c_sda_rx } = periph_calbus_readdata_0[72:0];
|
||||
|
||||
assign { periph1_mc1_to_iossm__irq ,
|
||||
periph1_mc1_to_iossm__hrdata ,
|
||||
periph1_mc1_to_iossm__hready ,
|
||||
periph1_mc1_to_iossm__hresp ,
|
||||
periph1_mc0_to_iossm__irq ,
|
||||
periph1_mc0_to_iossm__hrdata ,
|
||||
periph1_mc0_to_iossm__hready ,
|
||||
periph1_mc0_to_iossm__hresp ,
|
||||
periph1_pa_to_iossm__i3c_sda_rx } = periph_calbus_readdata_1[72:0];
|
||||
|
||||
assign pll_calbus_0 = pll_calbus_2;
|
||||
assign pll_calbus_1 = pll_calbus_2;
|
||||
assign pll_calbus_2 = { seq_to_pll__avl_rstn ,
|
||||
seq_to_pll__avl_clk ,
|
||||
seq_to_pll__avl_write ,
|
||||
seq_to_pll__avl_read ,
|
||||
seq_to_pll__avl_address ,
|
||||
seq_to_pll__avl_writedata };
|
||||
|
||||
// synthesis translate_off
|
||||
assign pll0_to_seq__avl_readdata = pll_calbus_readdata_0;
|
||||
assign pll1_to_seq__avl_readdata = pll_calbus_readdata_1;
|
||||
assign pll2_to_seq__avl_readdata = pll_calbus_readdata_2;
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for(i = 0; i < 32; i++) begin: gen_pll_pulldowns
|
||||
pulldown (weak0) (comp_to_seq__avl_readdata[i]);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
/* TODO
|
||||
*
|
||||
* user-interface
|
||||
* Review MC connections/ports
|
||||
* IOSSM parameters (meminit 512KB, 1KB)
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
+83
@@ -0,0 +1,83 @@
|
||||
// emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa.v
|
||||
|
||||
// Generated using ACDS version 26.1 110
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa #(
|
||||
parameter USE_PLI = 0,
|
||||
parameter PLI_PORT = 50000,
|
||||
parameter FIFO_DEPTHS = 2
|
||||
) (
|
||||
input wire clk_clk, // clk.clk, Clock Input
|
||||
input wire clk_reset_reset, // clk_reset.reset, Reset Input
|
||||
output wire master_reset_reset, // master_reset.reset, Reset Output
|
||||
output wire [31:0] master_address, // master.address, Address output of Avalon Memory Mapped Host
|
||||
input wire [31:0] master_readdata, // .readdata, Read Data input to Avalon Memory Mapped Host
|
||||
output wire master_read, // .read, Read command from Avalon Memory Mapped Host
|
||||
output wire master_write, // .write, Write command from Avalon Memory Mapped Host
|
||||
output wire [31:0] master_writedata, // .writedata, Write Data from Avalon Memory Mapped Host
|
||||
input wire master_waitrequest, // .waitrequest, Wait request from Avalon Memory Mapped Agent, indicates agent is not ready
|
||||
input wire master_readdatavalid, // .readdatavalid, Valid read data indication from Avalon Memory Mapped Agent
|
||||
output wire [3:0] master_byteenable // .byteenable, Indicates valid write data/read data location
|
||||
);
|
||||
|
||||
generate
|
||||
// If any of the display statements (or deliberately broken
|
||||
// instantiations) within this generate block triggers then this module
|
||||
// has been instantiated this module with a set of parameters different
|
||||
// from those it was generated for. This will usually result in a
|
||||
// non-functioning system.
|
||||
if (USE_PLI != 0)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
use_pli_check ( .error(1'b1) );
|
||||
end
|
||||
if (PLI_PORT != 50000)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
pli_port_check ( .error(1'b1) );
|
||||
end
|
||||
if (FIFO_DEPTHS != 2)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
fifo_depths_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_alt_mem_if_jtag_master_191_2xbfrbi #(
|
||||
.USE_PLI (0),
|
||||
.PLI_PORT (50000),
|
||||
.FIFO_DEPTHS (2)
|
||||
) jamb (
|
||||
.clk_clk (clk_clk), // input, width = 1, clk.clk
|
||||
.clk_reset_reset (clk_reset_reset), // input, width = 1, clk_reset.reset
|
||||
.master_reset_reset (master_reset_reset), // output, width = 1, master_reset.reset
|
||||
.master_address (master_address), // output, width = 32, master.address
|
||||
.master_readdata (master_readdata), // input, width = 32, .readdata
|
||||
.master_read (master_read), // output, width = 1, .read
|
||||
.master_write (master_write), // output, width = 1, .write
|
||||
.master_writedata (master_writedata), // output, width = 32, .writedata
|
||||
.master_waitrequest (master_waitrequest), // input, width = 1, .waitrequest
|
||||
.master_readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
|
||||
.master_byteenable (master_byteenable) // output, width = 4, .byteenable
|
||||
);
|
||||
|
||||
endmodule
|
||||
+1109
File diff suppressed because it is too large
Load Diff
+184
@@ -0,0 +1,184 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_bytes_to_packets
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0 )
|
||||
(
|
||||
input clk,
|
||||
input reset_n,
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data,
|
||||
output reg [CHANNEL_WIDTH-1: 0] out_channel,
|
||||
output reg out_startofpacket,
|
||||
output reg out_endofpacket,
|
||||
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data
|
||||
);
|
||||
|
||||
|
||||
reg received_esc, received_channel, received_varchannel;
|
||||
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
|
||||
|
||||
wire [7:0] data_out;
|
||||
|
||||
|
||||
assign sop_char = (in_data == 8'h7a);
|
||||
assign eop_char = (in_data == 8'h7b);
|
||||
assign channel_char = (in_data == 8'h7c);
|
||||
assign escape_char = (in_data == 8'h7d);
|
||||
|
||||
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
|
||||
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
if (out_ready) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
|
||||
end else begin
|
||||
assign varchannelesc_char = in_data[7];
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
received_esc <= 0;
|
||||
received_channel <= 0;
|
||||
received_varchannel <= 0;
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end else begin
|
||||
if (in_valid & in_ready) begin
|
||||
if (received_esc) begin
|
||||
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
|
||||
end else begin
|
||||
if (escape_char) received_esc <= 1;
|
||||
if (sop_char) out_startofpacket <= 1;
|
||||
if (eop_char) out_endofpacket <= 1;
|
||||
if (channel_char & ENCODING ) received_varchannel <= 1;
|
||||
if (channel_char & ~ENCODING) received_channel <= 1;
|
||||
end
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
|
||||
received_channel <= 0;
|
||||
end
|
||||
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
received_varchannel <= 0;
|
||||
end
|
||||
if (out_ready & out_valid) begin
|
||||
out_startofpacket <= 0;
|
||||
out_endofpacket <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = out_ready;
|
||||
out_valid = 0;
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
out_valid = 1;
|
||||
if (received_esc) begin
|
||||
if (received_channel | received_varchannel) out_valid = 0;
|
||||
end else begin
|
||||
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
|
||||
end
|
||||
end
|
||||
out_data = data_out;
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (CHANNEL_WIDTH == 0) begin
|
||||
always @(posedge clk) begin
|
||||
out_channel <= 'h0;
|
||||
end
|
||||
|
||||
end else if (CHANNEL_WIDTH < 8) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
out_channel <= 'h0;
|
||||
end else begin
|
||||
if (in_ready & in_valid) begin
|
||||
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
|
||||
out_channel <= data_out;
|
||||
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
|
||||
out_channel <= 'h0;
|
||||
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
|
||||
out_channel <= out_channel <<7;
|
||||
out_channel[6:0] <= data_out[6:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FjZ6PhPa/ugBMTMfMVHMQR2C8/f/MZmxemf9lgbUBptxwWGvhsI17eMKAlzYHmhLwmLBjUP4tTHPXP1w7xbVA2PKny6QLUBaU4oXuRnyJn99ehRr7AOtK6Qp1zq2deglgqzxoTMsSozGkPa70lyoig5lsYeqkDO7Qic9T3Xs/II2KR0wZ3Tqhq87oEF0tSYvNfBpJqdvlUvdTPaeNOHV6YhCgi+AKH8WpuwL6ze5+hTvflmk8e5vjhqCLIxFYVeTUvWOBecN6lPXB7S661HZz01XBtSZvGbIlzjAPM6lSXCpLfEGQ6C8UPNO4P/VdK+1TyduHQcSYHTZ0Rsz9P2sZSvdwoLqwthDTu8/r2U0WQ+ssQFnlEKJ6Pviui8TjRt0a0jPn8fiYv1OyKQME9+GRgZ7MtosVWyFSq0XbcQvdhJIqUdk8Sl3sNihdgrEUnKvxUfME0sL3Z91q0vi1RVt6PSqY/YA02Vq1MqQdKA1nf0uZAEqcq77AiDreLrVDxCR2oDzZ+avCOvP4zLBn/nkYxzoFNZEB2GLxaHp8cfxuBqHoO2jjH6qK6ZhG0DRl67ctc7swzKnJs+Y71Jrye9GJwRBVZsdR/gR75qutFj9Sy1gM3OfCLLdy2NDmy6jA8euthrUbizzJ7Rfd0KA4vg3EZYRTbisMdbl5gV8ILqDBO2gNNR55u7CsIWjSYnzoBa8Xyq5vX3VJn+Ujo9KquLwr+Wn7oH0D8N9sqk2tHEtIh2pp7oSOPtZiJ70upVbojx8EywKNB5eQDD01CS+W/08b4v"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9xd6cTHCfxqDhwZ5RVPYcLcJS6903KBCNRIBkDfzrNI0GHJUI+VlhCFTNloDHNQriag3AH68+ft0p59FMTcWpXTQRuwqju4RkIb+jTh16mWzpCSoMgdiM7kdgxNmx7GmkwTLB28IkvN09SKPYAaH5klbA47+EeBdr+NGdaaY5pC9zqrK88zvZhhDJdSIr+v6cqgsuCuSJuzGuhx7ZAjgxIjfPZXrwDFS9gNwSyMhfVjnM3Eudn+sGFHOePrVOPRfe8gctt4zkRSJYKu5d0AmV882klm5i9M+L45G6yDyWscQVOKok+V1kPKSttBH+oHh10ZIGz2FD2MdBZoSzN2P2CK78TZe0WUTfk9C2g3DR/BljyiB0K9xG7UrQ4tMOsAtpR2I+NBE1Pr5mvxi/tlxsJCb9wBcPnkjIy3Y+BAdb+keuPqNKjBgHxR7E1pcAImk7B+kiRVAnBCR54beEs0c5lMxJf3hh04OOHP2ud9lCSooSlccFTU0r6zLevZiq7RjtFtoE3sDQMXil/AJ35/AlVVO10jisQ8BucNyOnEM5sgpMlMAO89S/PS4UdJIcW65maGdbrJEgut8sxR+Uf8kr6aTyDvEI6iDu39TmXlMkgdkMKMDU+rsYZrpFjTC1j+b+pQEPVXXExnuC+bBOkacFJDBU/3cYjYxFLgiM1quAggejmpcOU1Q6+WmaJivsW3t87YTb5X8Cv1KFiTo7CIj9IF3oM6wNMo/S9SXJv0Ym8NFTQ6LXbXXMpRQQfRfWdQC4dTrb6qVbbu4peSw8RLYJ5"
|
||||
`endif
|
||||
+188
@@ -0,0 +1,188 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_clock_crosser(
|
||||
in_clk,
|
||||
in_reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_clk,
|
||||
out_reset,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter FORWARD_SYNC_DEPTH = 2;
|
||||
parameter BACKWARD_SYNC_DEPTH = 2;
|
||||
parameter USE_OUTPUT_PIPELINE = 1;
|
||||
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input in_clk;
|
||||
input in_reset;
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_clk;
|
||||
input out_reset;
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
|
||||
reg [DATA_WIDTH-1:0] out_data_buffer;
|
||||
|
||||
reg in_data_toggle;
|
||||
wire in_data_toggle_returned;
|
||||
wire out_data_toggle;
|
||||
reg out_data_toggle_flopped, out_data_toggle_1, out_data_toggle_flopped_n;
|
||||
|
||||
wire take_in_data;
|
||||
wire out_data_taken;
|
||||
|
||||
wire out_valid_internal;
|
||||
wire out_ready_internal;
|
||||
wire reset_merged;
|
||||
wire out_reset_merged;
|
||||
wire in_reset_merged;
|
||||
|
||||
assign in_ready = (in_data_toggle_returned ^ in_data_toggle);
|
||||
assign take_in_data = in_valid & in_ready;
|
||||
assign out_valid_internal = out_data_toggle_1 ^ out_data_toggle_flopped;
|
||||
assign out_data_taken = out_ready_internal & out_valid_internal;
|
||||
|
||||
assign reset_merged = in_reset | out_reset;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_in_rst
|
||||
(
|
||||
.clk (in_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (in_reset_merged)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (2),
|
||||
.ASYNC_RESET(1'b1)
|
||||
)
|
||||
alt_rst_req_sync_out_rst
|
||||
(
|
||||
.clk (out_clk),
|
||||
.reset_in (reset_merged),
|
||||
.reset_out (out_reset_merged)
|
||||
);
|
||||
|
||||
always @(posedge in_clk or posedge in_reset_merged) begin
|
||||
if (in_reset_merged) begin
|
||||
in_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
in_data_toggle <= 1'b0;
|
||||
end else begin
|
||||
if (take_in_data) begin
|
||||
in_data_toggle <= ~in_data_toggle;
|
||||
in_data_buffer <= in_data;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_1 <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_1 <= out_data_toggle;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped <= 1'b0;
|
||||
out_data_buffer <= {DATA_WIDTH{1'b0}};
|
||||
end else begin
|
||||
out_data_buffer <= in_data_buffer;
|
||||
if (out_data_taken) begin
|
||||
out_data_toggle_flopped <= out_data_toggle_1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge out_clk or posedge out_reset_merged) begin
|
||||
if (out_reset_merged) begin
|
||||
out_data_toggle_flopped_n <= 1'b0;
|
||||
end else begin
|
||||
out_data_toggle_flopped_n <= ~out_data_toggle_flopped;
|
||||
end
|
||||
end
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
|
||||
.clk(out_clk),
|
||||
.reset_n(~out_reset_merged),
|
||||
.din(in_data_toggle),
|
||||
.dout(out_data_toggle)
|
||||
);
|
||||
|
||||
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
|
||||
.clk(in_clk),
|
||||
.reset_n(~in_reset_merged),
|
||||
.din(out_data_toggle_flopped_n),
|
||||
.dout(in_data_toggle_returned)
|
||||
);
|
||||
|
||||
|
||||
generate if (USE_OUTPUT_PIPELINE == 1) begin
|
||||
|
||||
altera_avalon_st_pipeline_base
|
||||
#(
|
||||
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
|
||||
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
|
||||
) output_stage (
|
||||
.clk(out_clk),
|
||||
.reset(out_reset_merged),
|
||||
.in_ready(out_ready_internal),
|
||||
.in_valid(out_valid_internal),
|
||||
.in_data(out_data_buffer),
|
||||
.out_ready(out_ready),
|
||||
.out_valid(out_valid),
|
||||
.out_data(out_data)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign out_valid = out_valid_internal;
|
||||
assign out_ready_internal = out_ready;
|
||||
assign out_data = out_data_buffer;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "+AbvKNif4wIR5q/igDfM4DePC0l9exDgETX/dMtFAe71y0qcBHKGD6iKoAonAc18tp3+n/dPcXHqqPQcDPaTTmk7OKjrFa3Pkst/YjYx7bmo6SUfrzaVl9kc3zT+f1aRSGKf5IVl/Ez3tpEbJU8K9v/gNVYnzYrHsEy/PmUF70jGx1Y0gg9VJp9ZA4cKQBHvpOeIQDAu1e1V9vqrigbcMJYaagQ8BdQNgGlG54uA9jkcDvaJINvasYg8JaK3ZKKS0VHmn7SyrcYbthL2ydwkAw+ZxblESbPihzayM3N2ympFKG5lwbv86+4EQoJr3v3AhbWhBhjJKCVNIxg6IKYzvISROWIcIy1PJfIgUGEpsxKHw4NTh5aKPgmw70/7AX0bVu/fx5jlvAti7awFnONy0i6OciLLP7MxaeOnj7dtx54Jq7vXG/ZKaKvb9MgmMJnYug+Ddo0B89+2piW6h2SfN5hnpBV/p+0LeCl0QsZfIaxVCQ1KSw1ZztUdlVcldTfvunqP7sj8j8v1X8D+Ofdm6gsexkRp2EzIqjlYc7Q9aJlBkREFFVtd0lBa2WPJ3cyBasvvH3ef9seVQqDOBIWtWaPXbbi9boNcC0A6xv/uVV0Q8yBRQuMW7DuzwKxuSjsv7fP3gaqJ5Md5scSHqMW6Rqy+RkMiK/mq0wBJ6j0gachGEmApnoOcX8kOGk5NLxjoOJs4FWcGYDcbOue4kP/iD+XJGmrSDQPcHNLXnh3gMccNX0Ivv5SzuXq0P12JK6RYRpe370D1KFadq1CmDmJFeBjbicc46JOH2ryRk9V+1+VRtcM1kILumm9qZmTd4XJAIVOEnzNmNMwFWofQvRLwuo2JLOHbQ3BDpQxFLoY8dNkql5hEVRPiNl7CuPyDcYxzN+5AWA6oFmsPGvcXcA2s5XJ9T3PVGoH+sVhRzYFXY7LsDoQApQjLzakcUiGhkTCmrBx5RK0i9lcHjE7mXgY0cDP2ZWom4Q7ICPJD9Pu8EvtaVFJaSdh1MjH6dckOcP3T"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc8K/YlMaCrJ6VXYmpZRlmm/ohkaGbD8Jy1VegZ3omEmWfUL20jR6wlZ2MbEkOdlx5KzfuXo352wXNjxvFsQ6y2Az8bJNl5sKMdJd8+WbCM37RcOrIBO6w39yqnlPnSLIgw8FZCpi5cahRU2L2ExOXsAt84wktM8ttxsVBScIS48Ij3aBy2dYi+rBVj+ctrESujxroHurK/8yXJ2lPGhulKwYT73Hy1a8XUawe1OFYG87qx90S87Er8zWOdqA0Wm8qZ+V9jTdvhsd9xvaU3Swxj4vIs23L85XsDQ89KgVnCtwQenXx9BuHP+QPGUm36i0xIzKN2mLgDm/IlxQU9av8lMWzuBzSr9x2hME7fPT0C88d4427abIb72G6SYTqCb+ML4/k+pfqHgvGVHmqaxS8hgjE2QdjVmC/WyJU3RakOBti1PqNY+Zsjpm9Dv6bJ/eMBOCcU/ClPqU5O0RNSYBFB4dOGkfnFrThMNzf1Wh0gtGb+U/xf56z5ue1DTTU0M9JE8SxSv3ShKjzjnTGCNc3Nxr5F4/PTrlQUpmXmzNYoXCYTlTEOLVdpKwU+HjW/hxMQwcZuU/7ZtywLriiV4akITa8Zn/kWBiCx8B59kgRIl7VHWzxi3PvkfjMe/GRqnfdOiSjhz4g2vZEx1rIDolBZaIDmDqc7NKzE/s31CdKhk/s/ImTYUGBVLt6yQwS2FSg9XLz5fo+H7Baby9JTmZ40YJXoJ53NM0KqQuTJES76GdNimeASvCKIYdw7JkL7JkLIY+pg9K7Yj6nFxqumPByx0"
|
||||
`endif
|
||||
+241
@@ -0,0 +1,241 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
module altera_avalon_st_packets_to_bytes
|
||||
#( parameter CHANNEL_WIDTH = 8,
|
||||
parameter ENCODING = 0)
|
||||
(
|
||||
input clk,
|
||||
input reset_n,
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input [7: 0] in_data,
|
||||
input [CHANNEL_WIDTH-1: 0] in_channel,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output reg [7: 0] out_data
|
||||
);
|
||||
|
||||
|
||||
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
|
||||
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
|
||||
reg sent_esc, sent_sop, sent_eop;
|
||||
reg sent_channel_char, channel_escaped, sent_channel;
|
||||
reg [CHANNEL_WIDTH-1:0] stored_channel;
|
||||
reg [4:0] channel_count;
|
||||
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
|
||||
reg channel_needs_esc;
|
||||
|
||||
|
||||
|
||||
wire need_sop, need_eop, need_esc, need_channel;
|
||||
|
||||
|
||||
// synthesis read_comments_as_HDL on
|
||||
//assign need_esc = (in_data == 8'h7a | in_data == 8'h7b | in_data == 8'h7c | in_data == 8'h7d );
|
||||
// synthesis read_comments_as_HDL off
|
||||
|
||||
// synthesis translate_off
|
||||
assign need_esc = (in_data === 8'h7a | in_data === 8'h7b | in_data === 8'h7c | in_data === 8'h7d );
|
||||
// synthesis translate_on
|
||||
|
||||
|
||||
assign need_eop = (in_endofpacket);
|
||||
assign need_sop = (in_startofpacket);
|
||||
|
||||
|
||||
generate
|
||||
if( CHANNEL_WIDTH > 0) begin
|
||||
wire channel_changed;
|
||||
assign channel_changed = (in_channel != stored_channel);
|
||||
assign need_channel = (need_sop | channel_changed);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
channel_count <= 0;
|
||||
channel_needs_esc <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
channel_count <= CHN_COUNT[4:0];
|
||||
stored_varchannel <= in_channel;
|
||||
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
|
||||
channel_needs_esc <= (in_channel == 8'h7a |
|
||||
in_channel == 8'h7b |
|
||||
in_channel == 8'h7c |
|
||||
in_channel == 8'h7d );
|
||||
end
|
||||
end else if (channel_needs_esc & ~channel_escaped) begin
|
||||
out_data <= 8'h7d;
|
||||
channel_escaped <= 1;
|
||||
end else if (~sent_channel) begin
|
||||
if (ENCODING) begin
|
||||
if (channel_count > 0) begin
|
||||
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
stored_varchannel <= stored_varchannel<<7;
|
||||
|
||||
channel_count <= channel_count - 1'b1;
|
||||
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
|
||||
channel_needs_esc <=
|
||||
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
|
||||
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
|
||||
end
|
||||
end else begin
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
|
||||
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else begin
|
||||
if (channel_needs_esc) begin
|
||||
channel_needs_esc <= 0;
|
||||
out_data <= in_channel ^ 8'h20;
|
||||
end else out_data <= in_channel;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
sent_channel <= 0;
|
||||
channel_escaped <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
stored_channel <= {CHANNEL_WIDTH{1'b1}};
|
||||
end else begin
|
||||
if (sent_channel) stored_channel <= in_channel;
|
||||
end
|
||||
end
|
||||
always @* begin
|
||||
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
|
||||
end else begin
|
||||
|
||||
assign need_channel = (need_sop);
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (!reset_n) begin
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
out_data <= 0;
|
||||
out_valid <= 0;
|
||||
sent_channel <= 0;
|
||||
sent_channel_char <= 0;
|
||||
end else begin
|
||||
|
||||
if (out_ready )
|
||||
out_valid <= 0;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid )
|
||||
out_valid <= 1;
|
||||
|
||||
if ((out_ready | ~out_valid) && in_valid) begin
|
||||
if (need_channel & ~sent_channel) begin
|
||||
if (~sent_channel_char) begin
|
||||
sent_channel_char <= 1;
|
||||
out_data <= 8'h7c;
|
||||
end else if (~sent_channel) begin
|
||||
out_data <= 'h0;
|
||||
sent_channel <= 1;
|
||||
end
|
||||
end else if (need_sop & ~sent_sop) begin
|
||||
sent_sop <= 1;
|
||||
out_data <= 8'h7a;
|
||||
end else if (need_eop & ~sent_eop) begin
|
||||
sent_eop <= 1;
|
||||
out_data <= 8'h7b;
|
||||
end else if (need_esc & ~sent_esc) begin
|
||||
sent_esc <= 1;
|
||||
out_data <= 8'h7d;
|
||||
end else begin
|
||||
if (sent_esc) out_data <= in_data ^ 8'h20;
|
||||
else out_data <= in_data;
|
||||
sent_esc <= 0;
|
||||
sent_sop <= 0;
|
||||
sent_eop <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
|
||||
& (~need_sop | sent_sop)
|
||||
& (~need_eop | sent_eop)
|
||||
& (~need_channel | sent_channel);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1Fig3TUJuloNCYSplZZPpOt6ID9qIdlWSlYE/EQHQ4Ky0MdnTvNp4UN2Aq5Q8Ji6GA1rRK7Eddd+jwCFm5/ibjNxL2L2ly/rGOWWHjQb3P2DZpYJHBbq1HeNQlWt9EuBYB8woM1byrDxGAySNv3cXzrfo08ZL+4AqiHT5/QKszSpMOdWEqQ8FEWn0sC4i+HyHAqhfHveRwxRAy0Y0HInc5kVNnuy7kAFzr/ntlETft3R3IehE2kOXxF+I1wu/ufRXMAwAjZ7nfQF1dOkljcrdtxNSCTiBWDFf1CCbS75CXQxA+QhW2+Lkuq3ux6FjzDWXKCWfXheD6PrqAtG8JNSdXIOWso7rYUCxeS7f0TCze/W1X5/0v5OVP4Wun1cyPWeOXRveYY2IUYBkMbA0WP2QRGhrYS7QKeRCJ4B2kH6gXVwaHhbdk7D6r7eX804biwxC8kN38fbsQW8sGP6pHTd9Apnq43bCmnGq/q/0TwSqSpOGrFGcN2L22nlsYnGSAJXwt+QWooBRxVctjgZUy+lBl65qkyXlvissvdMwVuxI4hSIcGpacz3OyEDq3FpEr35wbivbJj54Pv/Q/IHz8QiUhFqmrJfP3alz66Xmfm+vFPkj9mDGsSMGWLRxkFI3WQwyS+bn2LUrUmu3ByBJhCceze0TMpDILkdflPBsZzCZAV6hpEJCh9VHkdir3K5f1xz3ShmPACKt6tZYX0pDULc4bWpxIbDtmsHtkS7YotMWCe8bCFEOZHiFcSLi93z+OFaKeLDJMVBSqwfeo8LJeHw+2ah"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9ZeQv/NEcGo3z2nWE+/OgXgc+u0VmPIAQFniyXV4OMu56r+oPL6XJgceBm2+Z2vf2i14RkJ1QxQ6c2VBeV5Galz6uzCQf6A/wkcVGzzTtkPqRWc8WnjsiuwBkKHY4YvQnJS7NXHYv2daRpwYZ5RLwJyiBHLXAAMrnLS0ZfO/8dx5vP0ZF5f9fyZQMZhRBrZe86uLFF6fHC02UWcVuAiW6/bEdPkz31+g9tBwQODuYS+ebRwMTxhCK82UcMWTrGT5/hwMaLaVh2e7kZ9BEXrrscNAT5siNE5Gmdz8VZpkpArfOYFqIRIIrQ/BKCMyBVIGkcVTa9vR+/SzmUzWEA5IzLVGyOL2QGtPcl6WjHHABeznGXR8e6ym5TQgLnWZiBQ3SVEW0heEvo5azPt5y+qCg8Yi8oJpjzwG9YuYbpnaEps5O0hIU2UavdY5ZQMoS6Yc2P9U2hKX3yC7CXvVZiyhodpURBOuf2CqQCP2W9uhqipn4sa0VsgdlUOENuQ1s7SlfacoUnPoMPFFast2COEGnFawq1JHOf6uFnCILt+rAnFkdcHLv9lXo9ktJxuVWK2iw2RRGWX7th2NBe3iAygO3fYCkgHGaIvN2dCN9LXPmoz4M86gBG9ka4rSu9jr3Fb5f7hLCaHVJfOEWpCMl4cbKap5L8aQIb07LA+fbrUl7qtkXmJGZt+jjezskQaiCr/Rqn1QXmuM9L1fe7BKnJbWq1nh2qi3yUy3iJaGj3/HLyckSeoVSeqPlhU78JvBKfJDUhWufX0cyJHHmMgoDf7Czf"
|
||||
`endif
|
||||
+190
@@ -0,0 +1,190 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_avalon_st_pipeline_base (
|
||||
clk,
|
||||
reset,
|
||||
in_ready,
|
||||
in_valid,
|
||||
in_data,
|
||||
out_ready,
|
||||
out_valid,
|
||||
out_data
|
||||
);
|
||||
|
||||
parameter SYMBOLS_PER_BEAT = 1;
|
||||
parameter BITS_PER_SYMBOL = 8;
|
||||
parameter PIPELINE_READY = 1;
|
||||
parameter SYNC_RESET = 0;
|
||||
parameter BACKPRESSURE_DURING_RESET = 0;
|
||||
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
|
||||
|
||||
input clk;
|
||||
input reset;
|
||||
|
||||
output in_ready;
|
||||
input in_valid;
|
||||
input [DATA_WIDTH-1:0] in_data;
|
||||
|
||||
input out_ready;
|
||||
output out_valid;
|
||||
output [DATA_WIDTH-1:0] out_data;
|
||||
|
||||
reg full0;
|
||||
reg full1;
|
||||
reg [DATA_WIDTH-1:0] data0;
|
||||
reg [DATA_WIDTH-1:0] data1;
|
||||
|
||||
assign out_valid = full1;
|
||||
assign out_data = data1;
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (PIPELINE_READY == 1)
|
||||
begin : REGISTERED_READY_PLINE
|
||||
|
||||
assign in_ready = !full0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~full0)
|
||||
data0 <= in_data;
|
||||
if (~full1 || (out_ready && out_valid)) begin
|
||||
if (full0)
|
||||
data1 <= data0;
|
||||
else
|
||||
data1 <= in_data;
|
||||
end
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst0
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (full1 & full0) begin
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
full0 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
full1 <= 1'b0;
|
||||
end else begin
|
||||
if(~full1 & full0)begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
|
||||
if (~full0 & ~full1) begin
|
||||
if (in_valid) begin
|
||||
full1 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
if (full1 & ~full0) begin
|
||||
if (in_valid & ~out_ready) begin
|
||||
full0 <= 1'b1;
|
||||
end
|
||||
if (~in_valid & out_ready) begin
|
||||
full1 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (full1 & full0) begin
|
||||
if (out_ready) begin
|
||||
full0 <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
begin : UNREGISTERED_READY_PLINE
|
||||
|
||||
assign in_ready = (~full1) | out_ready;
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst1
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
data1 <= 'b0;
|
||||
full1 <= BACKPRESSURE_DURING_RESET ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (in_ready) begin
|
||||
data1 <= in_data;
|
||||
full1 <= in_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "+AbvKNif4wIR5q/igDfM4DePC0l9exDgETX/dMtFAe71y0qcBHKGD6iKoAonAc18tp3+n/dPcXHqqPQcDPaTTmk7OKjrFa3Pkst/YjYx7bmo6SUfrzaVl9kc3zT+f1aRSGKf5IVl/Ez3tpEbJU8K9v/gNVYnzYrHsEy/PmUF70jGx1Y0gg9VJp9ZA4cKQBHvpOeIQDAu1e1V9vqrigbcMJYaagQ8BdQNgGlG54uA9jkeuJGToVB/w0SRZv7vWkHAzy4Kt1CiWFvCd6zJYjSPeLWe6moaY3yNeegErACTuP3xEjI2JtzMm8lHEhSvib+52ZRzcmWf2HX/qHTq3KZeVNAUJF1boYeN2B2s+TtPz2xamQ+itIWJbO7S4C1bxDFEXrZ/rX3Oc8rgPhPCXIx/SwLiXYUuVc+SjdO95Zb1ydeqQh3HEI8j7i+RAy76jv1/E+Ph7e1BWey1tf0MBbI06N3r7cz+VvAdRaUlhViAR2KN/Givzdxrab6o84xhLxO/VSKtbwP2okPpu/ULYd0o2MIgs+tktL1UK8kk8Om0zW8JbYIQLNTYJcI3uGkAJPWWyshRZdliDtKdfiXndHDvCD+feDG/iJ6sLfsHmIAUZZXiWC4HqeCW1hwS44DMPV86WYBmwe0c1QsIG9wlK9QyEy0fZeaKcVOTbiinTRtCSgyCTZUR8BoY5d/PhDcm0vXNEgRWs5B6QNU9U5nSnOoT0AhMtiDrc+2+U1KggIpWPTzAP72cJpXim6RCQlcw67LtY2+CWVwjVeDO8Z0OTrCInuJZs5ZX/HH00Z5DDSHJjqxzaBA1e658Q8pVZzSaQbSOv3TwrFZj42AADRs38L41S26w7XuP0bt0pyH1ZIZXqHWWVYs5jhJJkzObhEq1PPmoUGLamtr7sYO05bvAdWBlqSuYHJBY3/Mi+P8lFn1XolhFrsKIKApYzvVFpLJiqmX3atA2rM1WQMJ2l1n3Jv54co7gFk/s2Wczerlxny75seicGEiBISvmsuWJPoqVG21f"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc8n4bUWfkkdkXRV8T7DTOfYI0ktNYxtMfo0H5CQED9dfFplt2eZI0Yjjlx/MMvMKk5LErDLB+2NLH+gD0Sj6PZN5+LN6vDC6qOnW/VbmXXmjPXEKwSX1loaIyRpLzMc4ne8ygzVpLV0FdimHmdYqrhG6YmDwMnzEziymtPhcVUJLEZKbjTYldYmFWhWzdvdvEhjH2MqqVWZxHRZb3Cq59NKvGoxoUY3L8AbC7ZuRT4IPUg8SzKAumnpxtsCoMV4jNqAIOAMjcOFEeGZ5Ty2sAnC34a7Awp22KSDkvbHIzIV2MZmykkSC56D+56JuVgsmmGuJeVuG8L42e/Tz/1bWQQOefUBpvVEdfPDS0VN50i/pcNiLaiBEVxs6gOC4pCAQuL6Lkm28rFfpDNpICouj2JVq+tcOxtwa2A/9H2uHsWw1QVp5tCUW/BaBE8gO1SNg3YzenVff3bh5/1Jw/dfa3bm5RGDv2egGhUJWVRuKS7HLGtcQpTKEI5INV1Ib3ug9kLBfYDbugBpNkBayr6Tu0BuV53fY4XtHjYcgX3R3vNUlzCttfU31Pl9Lok25tdbbJyzlHcym3qZRmHsql3WAb/WH8VJJb54LFaVmgjEtNrcSM3OHQf4puU1Xb8edWPG5VCdXh1nIv2HBkuT2tcRiw+a14NGUIuHJ7f6wsCrWQ3vzXeUP9NmqRbdxEmGWRytCz0ssspcPEfIkvOJhKoq46HULSMu28ZOLFyPitdLcxdeOqyia7gJLDey4evIt6SgdlLBmlrN6LgwjHtHw2IA9V56"
|
||||
`endif
|
||||
+173
@@ -0,0 +1,173 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_default_burst_converter
|
||||
#(
|
||||
parameter PKT_BURST_TYPE_W = 2,
|
||||
parameter PKT_BURSTWRAP_W = 5,
|
||||
parameter PKT_ADDR_W = 12,
|
||||
parameter PKT_BURST_SIZE_W = 3,
|
||||
parameter IS_AXI_SLAVE = 0,
|
||||
parameter LEN_W = 2,
|
||||
parameter SYNC_RESET = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
input enable,
|
||||
|
||||
input [PKT_BURST_TYPE_W - 1 : 0] in_bursttype,
|
||||
input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg,
|
||||
input [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_value,
|
||||
input [PKT_ADDR_W - 1 : 0] in_addr,
|
||||
input [PKT_ADDR_W - 1 : 0] in_addr_reg,
|
||||
input [LEN_W - 1 : 0] in_len,
|
||||
input [PKT_BURST_SIZE_W - 1 : 0] in_size_value,
|
||||
|
||||
input in_is_write,
|
||||
|
||||
output reg [PKT_ADDR_W - 1 : 0] out_addr,
|
||||
output reg [LEN_W - 1 : 0] out_len,
|
||||
|
||||
output reg new_burst
|
||||
);
|
||||
|
||||
typedef enum bit [1:0]
|
||||
{
|
||||
FIXED = 2'b00,
|
||||
INCR = 2'b01,
|
||||
WRAP = 2'b10,
|
||||
RESERVED = 2'b11
|
||||
} AxiBurstType;
|
||||
|
||||
wire [LEN_W - 1 : 0] unit_len = {{LEN_W - 1 {1'b0}}, 1'b1};
|
||||
reg [LEN_W - 1 : 0] next_len;
|
||||
reg [LEN_W - 1 : 0] remaining_len;
|
||||
reg [PKT_ADDR_W - 1 : 0] next_incr_addr;
|
||||
reg [PKT_ADDR_W - 1 : 0] incr_wrapped_addr;
|
||||
reg [PKT_ADDR_W - 1 : 0] extended_burstwrap_value;
|
||||
reg [PKT_ADDR_W - 1 : 0] addr_incr_variable_size_value;
|
||||
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (IS_AXI_SLAVE == 1)
|
||||
begin : axi_slave_out_len
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
out_len <= (in_bursttype == FIXED) ? in_len : unit_len;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
begin : non_axi_slave_out_len
|
||||
always_comb begin
|
||||
out_len = unit_len;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
always_comb begin : proc_extend_burstwrap
|
||||
extended_burstwrap_value = {{(PKT_ADDR_W - PKT_BURSTWRAP_W){in_burstwrap_reg[PKT_BURSTWRAP_W - 1]}}, in_burstwrap_value};
|
||||
addr_incr_variable_size_value = {{(PKT_ADDR_W - 1){1'b0}}, 1'b1} << in_size_value;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
next_incr_addr <= next_incr_addr + addr_incr_variable_size_value;
|
||||
if (new_burst) begin
|
||||
next_incr_addr <= in_addr + addr_incr_variable_size_value;
|
||||
end
|
||||
out_addr <= incr_wrapped_addr;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
always_comb begin
|
||||
incr_wrapped_addr = in_addr;
|
||||
if (!new_burst) begin
|
||||
incr_wrapped_addr = (in_addr_reg & ~extended_burstwrap_value) | (next_incr_addr & extended_burstwrap_value);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire [LEN_W - 1 : 0] min_len;
|
||||
generate if (IS_AXI_SLAVE == 1)
|
||||
begin : axi_slave_min_len
|
||||
assign min_len = (!in_is_write && (in_bursttype == FIXED)) ? in_len : unit_len;
|
||||
end
|
||||
else
|
||||
begin : non_axi_slave_min_len
|
||||
assign min_len = unit_len;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire last_beat = (remaining_len == min_len);
|
||||
|
||||
always_comb begin
|
||||
remaining_len = in_len;
|
||||
if (!new_burst) remaining_len = next_len;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
next_len <= remaining_len - unit_len;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : async_rst3
|
||||
|
||||
always_ff @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
new_burst <= 1'b1;
|
||||
end
|
||||
else if (enable) begin
|
||||
new_burst <= last_beat;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (internal_sclr) begin
|
||||
new_burst <= 1'b1;
|
||||
end
|
||||
else if (enable) begin
|
||||
new_burst <= last_beat;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1Fi3emJ/3DhUHBwp+viQ8wX7rfUszlzZvPgXm/L0/Au+4wai5tm2rGGkx7EO5ADdZS8WfpqCP/8Gp68p+C4qSbOZgYGRt5a7lDmV2azCku2hSb9BYEJ2qA95AOKoXmWn969v9aGj6kye2uSQgvjHdlQfzac4rXIXX+lH2hQbFJEib7oLDoarAhMbEut9Tfa0NerYk8d0+3EqLqaS9UuEhe5zVnme6K7hdME8FcLiB6MUltWm8Ih5QKSi/klOl2GunuCzSCM0gPWHSlhFHA4/WIcosxCMsOaesvxtejS5Uw+JISm65HBAo2viB4QB3oYnVjQdRt3YmEIY7TznnVDA5y6dimG5vkgmwtwqYciD0+PUwpy/YT1Msoxd225DKZU74n+/jJ4g4CAzx5/Jh/GOW+9Y1ts1g2Yxa/IVZLikIo2alpYXTx2u5GUqC7xAdh6G5f7icvR+xYU6v+gb0e5XVMO4c46KAJ3vhBZzQ9MIip5tjS2Rl4k9h94okEhpYVOE0tTXYRcUNwnThy0uWgU3+rV23ePyBEW8and42rnUgyPxG7jGNu8LolU/tCEjdzGQRGkPtiwB4U2B/P76HMj+6IufuMG3SXoB88fQvh36oZEumqoUNhv6WAbPNNHd5+IXOWSILGlTZLMsRYQbAXW3hfNvP1MfIJXWjD5OiEBVTYO3DUrxC5KrJq9qki8lf2KcNiLdoa+XAe8OirVvvxfBOixdFb5+4eL4Yf4VhkOApBIz4zcK0e+L/xdX5IMjlo6vI2AMuFNYwpb3vBVJ1+nDZqQA"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9f9PCyAxPJ8dEoo0ZpbR+U0iSPSEqu00zSUp9BnyfGqYe6JQ643M+X7VcXDPB8/QK/y8bkOtiwIQ9hc9jvqlafZIrfR4laIF8CjBwkYfkDnyGGCj6k+vySlqpIDCWFHhrtn078cP3cJmZzs6w82iHnq8W2BEXNs330El9FtCptb2zlr+FZr9CO9C+9daR5vCqBiEpXFANJ+EDVDaHu//v1ntZ1deHzBTXbPWlCatUKchlGc5yw0pHLVeDPLmiN+svhAcS9rVW9J/53Ls+/9Em+CYx2CeRSY3kFNFE4qSPrw9JB6orULLCtJAUvLYDHX9egxLayEQ2n3cF4DVcLBP+KFJwqGEZ0OmFzSmZtxunLnxdL8E79U9N5kZG5PVls23hgD0F42W6p2rr62ZVz+w+7DTncsNyoemYX1SUJaKT1dRRSPL+rJGF665Qik13Dio4tV04GTpXx1B5ILH9T8DvgdmAOsm9IDSnGKOCXY4P+oWletWtsYanm2wJ+J3ZGfFhrEjVk9uqqbz3B1uTzwA9Lo/lDkqrvGcolUTc7zaTRc12l8MYXtiwSzKECTNTeLxDKf1k1P4Vovgdk1A8mLFrFejd+6nw4doUIIRadz0C35jfdycudOCTJEpxuBrnfAy6iVyTX5U0i+Kxwp6gHWGQsk8d9dgivcRmPqgLHB7h8EDC5vNXALH/P/1z42fuostd3ygehyKVW42THlaEPN19THd9eOtyqx6xno/ucSa/KIkBjvRFuUAmzGqudAfBr1cihbMaDRnOIHKXKIQ7WVx4v"
|
||||
`endif
|
||||
+294
@@ -0,0 +1,294 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_incr_burst_converter
|
||||
#(
|
||||
parameter
|
||||
MAX_IN_LEN = 16,
|
||||
MAX_OUT_LEN = 4,
|
||||
NUM_SYMBOLS = 4,
|
||||
ADDR_WIDTH = 12,
|
||||
BNDRY_WIDTH = 12,
|
||||
BURSTSIZE_WIDTH = 3,
|
||||
IN_NARROW_SIZE = 0,
|
||||
PURELY_INCR_AVL_SYS = 0,
|
||||
SYNC_RESET = 0,
|
||||
LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1,
|
||||
OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1,
|
||||
LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
input enable,
|
||||
|
||||
input is_write,
|
||||
input [LEN_WIDTH - 1 : 0] in_len,
|
||||
input in_sop,
|
||||
|
||||
input [ADDR_WIDTH - 1 : 0] in_addr,
|
||||
input [ADDR_WIDTH - 1 : 0] in_addr_reg,
|
||||
input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg,
|
||||
input [BURSTSIZE_WIDTH - 1 : 0] in_size_t,
|
||||
input [BURSTSIZE_WIDTH - 1 : 0] in_size_reg,
|
||||
|
||||
output reg [LEN_WIDTH - 1 : 0] out_len,
|
||||
output reg [LEN_WIDTH - 1 : 0] uncompr_out_len,
|
||||
output reg [ADDR_WIDTH - 1 : 0] out_addr,
|
||||
output reg new_burst_export
|
||||
);
|
||||
|
||||
reg [LEN_WIDTH - 1 : 0] remaining_len;
|
||||
reg [LEN_WIDTH - 1 : 0] next_out_len;
|
||||
reg [LEN_WIDTH - 1 : 0] next_rem_len;
|
||||
reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len;
|
||||
reg [LEN_WIDTH - 1 : 0] next_uncompr_remaining_len;
|
||||
reg [LEN_WIDTH - 1 : 0] next_uncompr_rem_len;
|
||||
reg new_burst;
|
||||
reg uncompr_sub_burst;
|
||||
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire [OUT_LEN_WIDTH - 1 : 0] max_out_length;
|
||||
assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
|
||||
|
||||
always_comb begin
|
||||
new_burst_export = new_burst;
|
||||
end
|
||||
|
||||
|
||||
always_comb begin : proc_uncompressed_remaining_len
|
||||
if ((in_len <= max_out_length) && is_write) begin
|
||||
uncompr_remaining_len = in_len;
|
||||
end else begin
|
||||
uncompr_remaining_len = max_out_length;
|
||||
end
|
||||
|
||||
if (uncompr_sub_burst)
|
||||
uncompr_remaining_len = next_uncompr_rem_len;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
next_uncompr_rem_len <= uncompr_remaining_len - 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
always_comb begin : proc_compressed_remaining_len
|
||||
remaining_len = in_len;
|
||||
if (!new_burst)
|
||||
remaining_len = next_rem_len;
|
||||
end
|
||||
|
||||
always_ff@(posedge clk) begin : proc_next_uncompressed_remaining_len
|
||||
if (enable) begin
|
||||
if (in_sop) begin
|
||||
next_uncompr_remaining_len <= in_len - max_out_length;
|
||||
end
|
||||
else if (!uncompr_sub_burst)
|
||||
next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_comb begin
|
||||
next_out_len = max_out_length;
|
||||
if (remaining_len < max_out_length) begin
|
||||
next_out_len = remaining_len;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
if (new_burst)
|
||||
next_rem_len <= in_len - max_out_length;
|
||||
else
|
||||
next_rem_len <= next_rem_len - max_out_length;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin: async_rst3
|
||||
|
||||
always_ff @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
uncompr_sub_burst <= 0;
|
||||
end
|
||||
else if (enable && is_write) begin
|
||||
uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (internal_sclr) begin
|
||||
uncompr_sub_burst <= 0;
|
||||
end
|
||||
else if (enable && is_write) begin
|
||||
uncompr_sub_burst <= (uncompr_remaining_len > 1'b1);
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire end_compressed_sub_burst;
|
||||
assign end_compressed_sub_burst = (remaining_len == next_out_len);
|
||||
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : async_rst4
|
||||
always_ff @(posedge clk, posedge reset) begin
|
||||
if (reset)
|
||||
new_burst <= 1;
|
||||
else if (enable)
|
||||
new_burst <= end_compressed_sub_burst;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (internal_sclr)
|
||||
new_burst <= 1;
|
||||
else if (enable)
|
||||
new_burst <= end_compressed_sub_burst;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
out_len <= next_out_len;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
uncompr_out_len <= uncompr_remaining_len;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
reg [ADDR_WIDTH - 1 : 0] addr_incr_sel;
|
||||
reg [ADDR_WIDTH - 1 : 0] addr_incr_sel_reg;
|
||||
reg [ADDR_WIDTH - 1 : 0] addr_incr_full_size;
|
||||
|
||||
localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
|
||||
|
||||
generate
|
||||
if (IN_NARROW_SIZE) begin : narrow_addr_incr
|
||||
reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size;
|
||||
reg [ADDR_WIDTH - 1 : 0] addr_incr_variable_size_reg;
|
||||
|
||||
assign addr_incr_variable_size = MAX_OUT_LEN << in_size_t;
|
||||
assign addr_incr_variable_size_reg = MAX_OUT_LEN << in_size_reg;
|
||||
|
||||
assign addr_incr_sel = addr_incr_variable_size;
|
||||
assign addr_incr_sel_reg = addr_incr_variable_size_reg;
|
||||
end
|
||||
else begin : full_addr_incr
|
||||
assign addr_incr_full_size = ADDR_INCR[ADDR_WIDTH - 1 : 0];
|
||||
assign addr_incr_sel = addr_incr_full_size;
|
||||
assign addr_incr_sel_reg = addr_incr_full_size;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
reg [ADDR_WIDTH - 1 : 0] next_out_addr;
|
||||
reg [ADDR_WIDTH - 1 : 0] incremented_addr;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
out_addr <= (next_out_addr);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
generate
|
||||
if (!PURELY_INCR_AVL_SYS) begin : incremented_addr_normal
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
if (new_burst) begin
|
||||
incremented_addr <= (next_out_addr + addr_incr_sel);
|
||||
end
|
||||
else begin
|
||||
incremented_addr <= (next_out_addr + addr_incr_sel_reg);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_comb begin
|
||||
next_out_addr = in_addr;
|
||||
if (!new_burst) begin
|
||||
next_out_addr = incremented_addr;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin : incremented_addr_pure_av
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable) begin
|
||||
incremented_addr <= (next_out_addr + addr_incr_sel_reg);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
always_comb begin
|
||||
next_out_addr = in_addr;
|
||||
if (!new_burst) begin
|
||||
next_out_addr = (incremented_addr);
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
function integer log2ceil;
|
||||
input integer val;
|
||||
reg[31:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i[30:0] << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FiKhaYqqrSNY3qdBFG9sHBPMTANMRO2i7vUxt8LXMxJFLeX6DAqWooNfg3JYN27ZG7VKIOfOaquBZrljNixqQtU+Ts8B/Ud/8cxzl+AIbgQiESlD+wfvrXmBxLgKAvGJvD6PUJr83QIDl6HW38Bb0xcRPMbb8rqFeSRZDL8G4gZZXDPUCYGgnncyxKfnDwTJfzv7gxZQ/XLnvMiriU5P5TCJKuF2ZS0mNPmL76uQszLEI1uj+xIzLwFZQ/Hw/i6/jUKw9RTS0bFB/+rmjLD353vqC8MWR/2pFZSIZOiDpgc3AYSQ1C9ChiLYiitiN+atcxonIWhthf/+Tju7Il3984VyYvKYVL5jPYcIoNul/2U8g4qyQIHNkq3VINgqBxTMoFzresUHJPgZahr+Ir6mWwL0lvcY5q9edfoxfVd1R8ga+RdMxkJF0h97Yqqdxr7taOsrKoPa+4jNS3wWG11y2UQ/OkMMOdxt3GralcYlbNr7mZGWRXclpM00wxkttpg9Ug7GWRd1Hu9v9QOSXC8gMnB3LzXE/ObaStEncHtOZD7SL0NgBcTcRuqZNL2S5Fpw6bkXImtOtSfub59EF1fIqCOa+k6mJtfYQ8hDUavXkpCK4upmU0r4IZljPwmTw3kIG6p03Gw2bVPRZFXGgBRglDam+fMwYfu7by0YpmO9ikknqpdmkVA6hurn4JGxBppCSKYFvRZteY79CtXLUOyHRGFjhKfAg5LwOxjwhvI8inSLfuOA2VJreqdGameq8oRqkMywy9pzBspQ/yopwRgVgYR"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc+eNa3iWAXK24GOhVjquO/p9Ft24MSC5CH+FxjLV3CJYR+gkiJk4CHQcMA7JcWy+kLPF5kcMDdruDL4JmDpk/480W+hn9D5FVw0+eON27hl9ZX3j8/ldptgK+kIbPnr0vwodazP5Vr8NKy8kEONq7idTv68pSUymr4aJcibbnigAzuFizsK7gJ68+SVD18c/ZJQqTb/Jtrtq4JffjBKJWON6JqBMQCvU3gwkV/N0jaR8JCVLOPsdPGNopElhrLZgUAzPiEaUdtHitbWjXtSaNtjqGZ3sWSsYnYaXlqdNHMHAGa+eL5gay6nYgjjOfoU7turwc8oyGu7LTiNJCger6LHJBTxK4iY6GGPA7WHiFq71Ld92ux97tehkc77xvMBjzQ1UPaQsLIb5LLlnPR/UaVg4vppKCmfjd7rd2SyWWgKjZ7/WHHdvnN4gwcs9gVCX9jDev6I8Z3kTfLie2lR+aMJwB+FsVnRu0OxCrYWh5eN+Bv1pxohjYVPpZErJZ+ixCbw+tYhl0FwgfChvh3PjjVH8gOQz78SclBY1v0aw7pCBFFlASVrm4rIe3N3hBVPOA1nEsZACIAkUDDdeKJBbVyEa973p0okILURXTH5FxqQ26E27NV4mLN5EGwQXYOdMqYKGxB2XLLpLjELqLrFdirN4lHb5KcjN/1wpoIlmaCUhwGFJiFWJavaJUCwWEoa2NFooJzf8k62JY5wEZVQ1epmJxqksHQ7rszHCEyqEcffOmzH1AXuMtwfpTQAZPTvrkw0ywCpKXo5pEA2xIdTeqx0"
|
||||
`endif
|
||||
+243
@@ -0,0 +1,243 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_address_alignment
|
||||
#(
|
||||
parameter
|
||||
ADDR_W = 12,
|
||||
BURSTWRAP_W = 12,
|
||||
TYPE_W = 2,
|
||||
SIZE_W = 3,
|
||||
INCREMENT_ADDRESS = 1,
|
||||
NUMSYMBOLS = 8,
|
||||
SELECT_BITS = log2(NUMSYMBOLS),
|
||||
IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
|
||||
OUT_DATA_W = ADDR_W + SELECT_BITS,
|
||||
SYNC_RESET = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [IN_DATA_W-1:0] in_data,
|
||||
input in_valid,
|
||||
input in_sop,
|
||||
input in_eop,
|
||||
|
||||
output reg [OUT_DATA_W-1:0] out_data,
|
||||
input out_ready
|
||||
|
||||
);
|
||||
typedef enum bit [1:0]
|
||||
{
|
||||
FIXED = 2'b00,
|
||||
INCR = 2'b01,
|
||||
WRAP = 2'b10,
|
||||
RESERVED = 2'b11
|
||||
} AxiBurstType;
|
||||
|
||||
function reg[9:0] bytes_in_transfer;
|
||||
input [SIZE_W-1:0] axsize;
|
||||
case (axsize)
|
||||
4'b0000: bytes_in_transfer = 10'b0000000001;
|
||||
4'b0001: bytes_in_transfer = 10'b0000000010;
|
||||
4'b0010: bytes_in_transfer = 10'b0000000100;
|
||||
4'b0011: bytes_in_transfer = 10'b0000001000;
|
||||
4'b0100: bytes_in_transfer = 10'b0000010000;
|
||||
4'b0101: bytes_in_transfer = 10'b0000100000;
|
||||
4'b0110: bytes_in_transfer = 10'b0001000000;
|
||||
4'b0111: bytes_in_transfer = 10'b0010000000;
|
||||
4'b1000: bytes_in_transfer = 10'b0100000000;
|
||||
4'b1001: bytes_in_transfer = 10'b1000000000;
|
||||
default: bytes_in_transfer = 10'b0000000001;
|
||||
endcase
|
||||
endfunction
|
||||
|
||||
AxiBurstType write_burst_type;
|
||||
|
||||
function AxiBurstType burst_type_decode
|
||||
(
|
||||
input [1:0] axburst
|
||||
);
|
||||
AxiBurstType burst_type;
|
||||
begin
|
||||
case (axburst)
|
||||
2'b00 : burst_type = FIXED;
|
||||
2'b01 : burst_type = INCR;
|
||||
2'b10 : burst_type = WRAP;
|
||||
2'b11 : burst_type = RESERVED;
|
||||
default : burst_type = INCR;
|
||||
endcase
|
||||
return burst_type;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function integer log2;
|
||||
input integer value;
|
||||
|
||||
value = value - 1;
|
||||
for(log2 = 0; value > 0; log2 = log2 + 1)
|
||||
value = value >> 1;
|
||||
|
||||
endfunction
|
||||
|
||||
|
||||
function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
|
||||
input [ADDR_W-1:0] address;
|
||||
input [SIZE_W-1:0] size;
|
||||
|
||||
integer i;
|
||||
reg [SELECT_BITS-1:0] mask_address;
|
||||
reg [SELECT_BITS-1:0] check_unaligned;
|
||||
mask_address = '1;
|
||||
check_unaligned = '0;
|
||||
for(i = 0; i < SELECT_BITS ; i = i + 1) begin
|
||||
if (i < size) begin
|
||||
check_unaligned[i] = address[i];
|
||||
mask_address[i] = 1'b0;
|
||||
end
|
||||
end
|
||||
mask_select_and_align_address = {check_unaligned,mask_address};
|
||||
endfunction
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= ~reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
reg [ADDR_W-1 : 0] in_address;
|
||||
reg [ADDR_W-1 : 0] first_address_aligned;
|
||||
reg [SIZE_W-1 : 0] in_size;
|
||||
reg [(SELECT_BITS*2)-1 : 0] output_masks;
|
||||
assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
|
||||
assign in_size = in_data[SIZE_W-1 : 0];
|
||||
|
||||
always_comb
|
||||
begin
|
||||
output_masks = mask_select_and_align_address(in_address, in_size);
|
||||
end
|
||||
|
||||
|
||||
generate
|
||||
if (SELECT_BITS == 0)
|
||||
assign first_address_aligned = in_address;
|
||||
else begin
|
||||
wire [SELECT_BITS-1 : 0] aligned_address_bits;
|
||||
if (SELECT_BITS == 1)
|
||||
assign aligned_address_bits = in_address[0] & output_masks[0];
|
||||
else
|
||||
assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
|
||||
assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
generate
|
||||
if (INCREMENT_ADDRESS)
|
||||
begin
|
||||
reg [ADDR_W-1 : 0] increment_address;
|
||||
reg [ADDR_W-1 : 0] out_aligned_address_burst;
|
||||
reg [ADDR_W-1 : 0] address_burst;
|
||||
reg [ADDR_W-1 : 0] base_address;
|
||||
reg [9 : 0] number_bytes_transfer;
|
||||
reg [ADDR_W-1 : 0] burstwrap_mask;
|
||||
reg [ADDR_W-1 : 0] burst_address_high;
|
||||
reg [ADDR_W-1 : 0] burst_address_low;
|
||||
reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
|
||||
reg [TYPE_W-1 : 0] in_type;
|
||||
assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
|
||||
assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
|
||||
assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
|
||||
assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask;
|
||||
assign burst_address_low = out_aligned_address_burst;
|
||||
assign number_bytes_transfer = bytes_in_transfer(in_size);
|
||||
assign write_burst_type = burst_type_decode(in_type);
|
||||
|
||||
always @*
|
||||
begin
|
||||
if (in_sop)
|
||||
begin
|
||||
out_aligned_address_burst = in_address;
|
||||
base_address = first_address_aligned;
|
||||
end
|
||||
else
|
||||
begin
|
||||
out_aligned_address_burst = address_burst;
|
||||
base_address = out_aligned_address_burst;
|
||||
end
|
||||
case (write_burst_type)
|
||||
INCR:
|
||||
increment_address = base_address + number_bytes_transfer;
|
||||
WRAP:
|
||||
increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
|
||||
FIXED:
|
||||
increment_address = out_aligned_address_burst;
|
||||
default:
|
||||
increment_address = base_address + number_bytes_transfer;
|
||||
endcase
|
||||
end
|
||||
|
||||
if (SYNC_RESET == 0) begin : async_rst0
|
||||
always_ff @(posedge clk, negedge reset)
|
||||
begin
|
||||
if (!reset)
|
||||
begin
|
||||
address_burst <= '0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (in_valid & out_ready)
|
||||
address_burst <= increment_address;
|
||||
end
|
||||
end
|
||||
end : async_rst0
|
||||
|
||||
else begin : sync_rst0
|
||||
always_ff @(posedge clk)
|
||||
begin
|
||||
if (internal_sclr)
|
||||
begin
|
||||
address_burst <= '0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (in_valid & out_ready)
|
||||
address_burst <= increment_address;
|
||||
end
|
||||
end
|
||||
end : sync_rst0
|
||||
|
||||
assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
|
||||
end
|
||||
else
|
||||
begin
|
||||
assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
|
||||
end
|
||||
|
||||
endgenerate
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1Fhf1L1JHMW8nvKeWDdk4Zb6ejbK0ZGu/sDEZe5yq+7YUKvI59sYca7MB3EoYbGoT+bMnLpG8xoxKo2i8R827BVo4NGOJeeAMSOcJSaM4A2E1b5MWjRwoH1euB+ajqagEtjXbWiI6jDYLASqIlAq3X6/tvYZgRLuiXXP9m6hBBezLl1oxGBxXIyFAV3WeU6Q1HCHQVhEDCYeGQ2eeLXo8eeqQBixK8UulIdMj/dByQgUvmTCa9lTLSxbJsZzDi1Fv8hEfdTpZMBRWqNaDBdikoLOeV1BJIq+yMqvwBCE/U5GVDZ77mjJfkF7Wl1ZZP2o/e/4ueWwtPd3/CbAMH57RuuYoKnbrEu5YAK9/Mlr6+DBnTl9KuFOLNWRuEdOvH85WSSassU1vwdMVPCyPX9argBnAsk4lmKEJ4sP/uC/kyfNIZT2r03q6wRSx/UYGK5Z9KysD/8bOfgdCrAFKUidiRK0hYWXIPLbgJfxDd09GEMbA2oZeFGcLJulMtp1RM5+c4a+IuW7OOO9q5+vPHJh4/MrUurgH1MAqbz4WeaMGgm4YKijfxT9yH7o7w8gVkNAoTbjsmUhfMFnRAjfZotDgPeV/Vt2pUDOB+ACGrdZSJgdqEd+gOx07mwh4f9Ch/Ck3ALoSrZkgq8LZ44nbDn8ZFoba9pfluHW/IP3Qs1WTGj5no2aovavTqEOO6Cz6dcsLVfnNbKwe5ujga1HAioyU+wCBTRmfcu1ZJOrnyEn6RR7C4K0qYOTo0ST6sMGtNkksCTn+dCsEIZvkeVqD2O8BQY8"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc877Kgy2/VfB7/Iyw0SWnSuKgFAaz08doMaeBAWvppnWqy/zO8/qPyNAeynJgv4LngdnbYI3vpzDr/l1jb+NVE8EchhGQvm/vZFduiiVAyDBv+LxMtqj8ZBMV/iAtAdN/qz5j6k8g0PNeS0AmbIpmpfZHLA4wxs2BADUlitFU1qPy/DqdY8OBT2UeYdeWk7cmJptbC5Q676H23pPfh21lfc79J2XhTWoyXQfuMblkarplhuunSHGIgtarnlxlm+gpiHz8R23yfTTKrQOIaGA7pLR6tY9QmJwza7wlvopbFupCSvP5YGvVD7AukuzdBqQ50LSG1CPM/HQV4sp+1i7AorkFgPIeM1T0HT6XSmxKeQVktSLxKyCifgFjEwIwGBV/laTenBx/HSmBxKcjLjT0b19n0ERyXRZMpNt9+GVr+oMugqp7ogSe9MSiZcKn6C/G2pb+PbK+RuTqnO4oC2t3urA8l1enXBBH8W48n6eji7/h7q6ovcyMA1yO37iKkbQnwFAksT0SPHh4Xc8PuqcurnBx+A1gFtVSR6ZJwkR6Zggrwo3K0+vvgBENY1y/FmHZOcmu3A9uyjB0gW738Mw5QdAEs4uW2PixUGCRzu82dm397Ip2LR4ENo+ep04krvbROJa23eVcD8Bvc3ZePtrudUFw5lEdXFjg0CIcdX78NhSeD+20++4rvlzu8qecVVCRhNhhIWv7g33PAJpPeTkOz+6aSUVtYnaP16GNqpo3UyqQcEUlLp2BbGPIjZFlgHdqy1xahQaGfoZYi/CNjNcPjR"
|
||||
`endif
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
Round-robin/fixed arbitration implementation.
|
||||
|
||||
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
|
||||
|
||||
A: M = X & (~X + 1)
|
||||
|
||||
Example: X = 101000100
|
||||
101000100 &
|
||||
010111011 + 1 =
|
||||
|
||||
101000100 &
|
||||
010111100 =
|
||||
-----------
|
||||
000000100
|
||||
|
||||
The method can be generalized to find the first set-bit
|
||||
at a bit index no lower than bit-index N, simply by adding
|
||||
2**N rather than 1.
|
||||
|
||||
|
||||
Q: how does this relate to round-robin arbitration?
|
||||
A:
|
||||
Let X be the concatenation of all request signals.
|
||||
Let the number to be added to X (hereafter called the
|
||||
top_priority) initialize to 1, and be assigned from the
|
||||
concatenation of the previous saved-grant, left-rotated
|
||||
by one position, each time arbitration occurs. The
|
||||
concatenation of grants is then M.
|
||||
|
||||
Problem: consider this case:
|
||||
|
||||
top_priority = 010000
|
||||
request = 001001
|
||||
~request + top_priority = 000110
|
||||
next_grant = 000000 <- no one is granted!
|
||||
|
||||
There was no "set bit at a bit index no lower than bit-index 4", so
|
||||
the result was 0.
|
||||
|
||||
We need to propagate the carry out from (~request + top_priority) to the LSB, so
|
||||
that the sum becomes 000111, and next_grant is 000001. This operation could be
|
||||
called a "circular add".
|
||||
|
||||
A bit of experimentation on the circular add reveals a significant amount of
|
||||
delay in exiting and re-entering the carry chain - this will vary with device
|
||||
family. Quartus also reports a combinational loop warning. Finally,
|
||||
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
|
||||
Modelsim _doesn't_ report a combinational loop!)
|
||||
|
||||
An alternate solution: concatenate the request vector with itself, and OR
|
||||
corresponding bits from the top and bottom halves to determine next_grant.
|
||||
|
||||
Example:
|
||||
|
||||
top_priority = 010000
|
||||
{request, request} = 001001 001001
|
||||
{~request, ~request} + top_priority = 110111 000110
|
||||
result of & operation = 000001 000000
|
||||
next_grant = 000001
|
||||
|
||||
Notice that if request = 0, the sum operation will overflow, but we can ignore
|
||||
this; the next_grant result is 0 (no one granted), as you might expect.
|
||||
In the implementation, the last-granted value must be maintained as
|
||||
a non-zero value - best probably simply not to update it when no requests
|
||||
occur.
|
||||
|
||||
----------------------------------------------------------------------- */
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_arbitrator
|
||||
#(
|
||||
parameter NUM_REQUESTERS = 8,
|
||||
parameter SCHEME = "round-robin",
|
||||
parameter PIPELINE = 0,
|
||||
parameter SYNC_RESET = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [NUM_REQUESTERS-1:0] request,
|
||||
|
||||
output [NUM_REQUESTERS-1:0] grant,
|
||||
|
||||
input increment_top_priority,
|
||||
input save_top_priority
|
||||
);
|
||||
|
||||
wire [NUM_REQUESTERS-1:0] top_priority;
|
||||
reg [NUM_REQUESTERS-1:0] top_priority_reg;
|
||||
reg [NUM_REQUESTERS-1:0] last_grant;
|
||||
wire [2*NUM_REQUESTERS-1:0] result;
|
||||
|
||||
generate
|
||||
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
|
||||
assign top_priority = top_priority_reg;
|
||||
end
|
||||
else begin
|
||||
assign top_priority = 1'b1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
altera_merlin_arb_adder
|
||||
#(
|
||||
.WIDTH (2 * NUM_REQUESTERS)
|
||||
)
|
||||
adder
|
||||
(
|
||||
.a ({ ~request, ~request }),
|
||||
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
|
||||
.sum (result)
|
||||
);
|
||||
|
||||
|
||||
generate if (SCHEME == "no-arb") begin
|
||||
|
||||
assign grant = request;
|
||||
|
||||
end else begin
|
||||
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
|
||||
assign grant_double_vector = {request, request} & result;
|
||||
|
||||
assign grant =
|
||||
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
|
||||
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : async_rst0
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
top_priority_reg <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (PIPELINE) begin
|
||||
if (increment_top_priority) begin
|
||||
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1]} : top_priority_reg;
|
||||
end
|
||||
end else begin
|
||||
if (increment_top_priority) begin
|
||||
if (|request)
|
||||
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1] };
|
||||
else
|
||||
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
|
||||
end
|
||||
else if (save_top_priority) begin
|
||||
top_priority_reg <= grant;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end : async_rst0
|
||||
|
||||
else begin : sync_rst0
|
||||
always @(posedge clk) begin
|
||||
if (internal_sclr) begin
|
||||
top_priority_reg <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if (PIPELINE) begin
|
||||
if (increment_top_priority) begin
|
||||
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1]} : top_priority_reg;
|
||||
end
|
||||
end else begin
|
||||
if (increment_top_priority) begin
|
||||
if (|request)
|
||||
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
|
||||
grant[NUM_REQUESTERS-1] };
|
||||
else
|
||||
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
|
||||
end
|
||||
else if (save_top_priority) begin
|
||||
top_priority_reg <= grant;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end : sync_rst0
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module altera_merlin_arb_adder
|
||||
#(
|
||||
parameter WIDTH = 8
|
||||
)
|
||||
(
|
||||
input [WIDTH-1:0] a,
|
||||
input [WIDTH-1:0] b,
|
||||
|
||||
output [WIDTH-1:0] sum
|
||||
);
|
||||
|
||||
wire [WIDTH:0] sum_lint;
|
||||
genvar i;
|
||||
generate if (WIDTH <= 8) begin : full_adder
|
||||
|
||||
wire cout[WIDTH-1:0];
|
||||
|
||||
assign sum[0] = (a[0] ^ b[0]);
|
||||
assign cout[0] = (a[0] & b[0]);
|
||||
|
||||
for (i = 1; i < WIDTH; i = i+1) begin : arb
|
||||
|
||||
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
|
||||
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
|
||||
|
||||
end
|
||||
|
||||
end else begin : carry_chain
|
||||
|
||||
assign sum_lint = a + b;
|
||||
assign sum = sum_lint[WIDTH-1:0];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FjTCeZ6k5epRRQm1jaEO9dtTZPvYIpxyd134ionjya/bVJZC8amlVu7xw6nw3zmLA1YXsGvsrgRxdtnwASNxo8VwrMgUzkqZbNZk98MBRqu4Q7oqcuwSPQV6A+A3vU0+JTGoVwSYdQD3THXjk+vZ9vkzTdX26x1e1R1KlDOj2R0YCIvkYx0QwtnVI6PAo9CqEs68fLS7n6Tf8nhjnL2qfettSmlS5perH5fHR9wfUuouYoOYs7oTjocPspLbltpXaPp3F7D548c8VhK4PlIen5Z+UTXwcX114RMxcacpOFYxDvM6w+vs7YtMb5TiaKX2F79Ml3pG8BvnTUtYxbIrWnpoPKMiUt1LvMDh+iDXHZwAhcvUe9MiijBreEf0b6kyzlwvuwFRWFBgjcM6vx4tMgmpc6SZ8m3QVNsXXV6MkppqsqI4lJog94aEtzSmK3iDUZFhJGA4Vxomo1S2M6e4F9SAamJ0dFTMVksXzPREwd79VFFTR5L4yd7Zo9Z2KxtQcKvjgR5nQmO9ZVC83Mynmro57c0fUFqUVPOAqTxXZI8o0p6hmT6ZIyw6x3M71/OjXsR5c5S0L63qyE3DOqfdWDFiXQcSttGKgRuyIbOFlg4pRL7laywvSxnDIM1mFEJ1q5EQMz9ek8L/0kuWOg7YBa/GT6eYghYtce/STHdiaMY4XsxYlHDPN6wqdKHGKPL20Wcnv9Y/SQUx7mGfijXc5MUV8/F8fsaYOgsswMCoNhJAkjFjQaOR/38ab3jKVt+qwYy2LXO1HwZNgkBPfyeZzXy"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc+nr35Cm6IExALKpLcnO+UJrc0+skjtaPXUa+NG52LD9HT9MnpDgbfPP6uunEv9O8yVoBTSVWt7ZWG98fzRBp7oQAiZPYaNfRZnhKWJ6Yi8nx76EbIJOLk4+Djvvm9GIPpkovw97zRHmKbp6pmMQBuPsatu5gE3MCbCy3seMK08vUzdMji+SJU0waIoXCUTbZY0XK0cq23gqIDpHk9Q1eNj2jaDRc5u8WTInC7QbItIKV7eswJpttGO1INoPa8XXiCHvA0eNu5KBvY4CIXtnkB4p4FWxU0512+77e5GStAiVF1AHjF8Td/Yz7c2vqC2x1sxvbr6T7A+WNK/n/wVGAhqNJ73eSpaNINazsQ0NsV3NEmLYlWFc5Z/cpY3MUx7ZopjTm31NBuT6YRCsHq9vdprpbTxoEQzC7rgJFH+1xOLAyVfd78KN3LMQQJItlVKSSoOLMjg3zZMAvf0xta3sv6NsfkHkw/dJXkOimztc7QNxyCxlt2pQh1Go17/JHhL/gfNLWxenAnpa53ZM5OAKpjafXnJTD6EREPpzvZqoeGHGv29Kt73edtPIld/eUrl8s3cq38K1ZuO2UQnfOwFENgCee8+mcpRYbiw0Tvl+jvJwv0lAUOuDB75Q3RFNrf4twTZ5NLmbpqKuT56QH9ZqcqJR7qX/rfqw7x2UON6iJGhP/UE24qt73JlFn8ia5of6d9cbUN0YguBPTMnIwL1tEmN0eYqslBIcJJz3KscENGWXhbQo7+DEBgh0+BJM9CgYH+Loi+LxCukriAWU0V8i0fE"
|
||||
`endif
|
||||
+1311
File diff suppressed because it is too large
Load Diff
+1921
File diff suppressed because it is too large
Load Diff
+76
@@ -0,0 +1,76 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_burst_adapter_uncompressed_only
|
||||
#(
|
||||
parameter
|
||||
PKT_BYTE_CNT_H = 5,
|
||||
PKT_BYTE_CNT_L = 0,
|
||||
PKT_BYTEEN_H = 83,
|
||||
PKT_BYTEEN_L = 80,
|
||||
ST_DATA_W = 84,
|
||||
ST_CHANNEL_W = 8
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input sink0_valid,
|
||||
input [ST_DATA_W-1 : 0] sink0_data,
|
||||
input [ST_CHANNEL_W-1 : 0] sink0_channel,
|
||||
input sink0_startofpacket,
|
||||
input sink0_endofpacket,
|
||||
output reg sink0_ready,
|
||||
|
||||
output reg source0_valid,
|
||||
output reg [ST_DATA_W-1 : 0] source0_data,
|
||||
output reg [ST_CHANNEL_W-1 : 0] source0_channel,
|
||||
output reg source0_startofpacket,
|
||||
output reg source0_endofpacket,
|
||||
input source0_ready
|
||||
);
|
||||
localparam
|
||||
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
|
||||
NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
|
||||
|
||||
wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS[PKT_BYTE_CNT_W - 1 : 0];
|
||||
|
||||
always_comb begin : source0_data_assignments
|
||||
source0_valid = sink0_valid;
|
||||
source0_channel = sink0_channel;
|
||||
source0_startofpacket = sink0_startofpacket;
|
||||
source0_endofpacket = sink0_endofpacket;
|
||||
|
||||
source0_data = sink0_data;
|
||||
source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = num_symbols_sig;
|
||||
|
||||
sink0_ready = source0_ready;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FjJp8tUNyGN5irle4fz/y2QTsWcrhIYoCIt4ca9rsOt8zTmSoCaF6Wk3PYpIpjZzy7szRzA3jVL7YTrarTQyEw2yEKVpCgrU1L/kJ3XmV59srSbkqwzq3BaqRV8wZkfhwddnynQcLwl1NcqL5ICISVrd51J88zo3Hy0u+e8VX7fW7I6WsSxQsBTAEOHRgrqJ3+N+/pd7aO+MnpV+Q/CSjEF3iwQBIzR0Z5QmjaGhjd+YJkRWU/UCJu+snoqsjxoEA+9YmZoFpd4mpVYF7dz1MZddOkfQKYo6G5NExQbHbjiJLVj31g6B0hx0ru7mvVibMW6002OvpBXd4aqhE7xJAsaQhiQukgPjMVQTHPBFipmhHO9f1Se33puTWOJMPTtqUN9uGR/5/gal69Lqgjx+5HASBGL2N6wHzdoa8Bvl2xInNRabImbano0omE9Uqa/WGMzVVyye/a+V3A/5kWBigsAoGO95uNY65M9f+cw4VPEYfvXoTV+Kkm51HXs9q7XvGJyGDeTE70mu9STNU8/0WXzBlFgm6x97JsPtT4+LD4mynyDfDRyzs/ZtYHFVnpY7O4LRKhy0RmC+zJmZjX/f+ZPz9+PaCX0sJ/EpuXbjUIiny3DAkWaQVU3yRA0HHSDU9Wj859Vlq6H4xP+VqBAzkGedXDsanEV6B1mf3YslCunHLRob0WFQAyVJ5RtytcLFSCrZ4PEI6hxt6MnGRlVHj5hGQAU4nPC6jlp9x9nJUKqLUBWTGTN6hAKw1zgf8zkp345V6YPRqEl+pENIzggxEig"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9WCv23ZsM10w8ViIrJnVQOmIGdVjCt2XNn+JdAhvlIpKL7ugR+gmtIlNL5EdiDj8LdVDuv/aI5kJjBEG1rx6c5M1MIU+R7OoAsDq5aFGzkOVrJjZUF37yBgSjCIXf18rz9kARvE7F3SJ9+wEQPEYYJnCnA11zvGqFm5KLceFz4ObZDcrBApUf5Wi+GgNZBqw5HOkJn2dAta1RJHTvF28TJEKZ0DOPzU1aLPacpYy53ohQ7E9PEPZo/bZzgdrNj6XoXPZTDjeSqzGQJcXrXfm3ehTpHUSmIhehot7997uG881ctA1TzhJWi3QfUheZVE5QlyabjdncCt2AC3YidBk1IBCHgqSAhf7xAi1k289vnirWsHDDklaDCB/PWZSB5xnaiDGFKtituB096oR93usuC87Ji6uVxqvGfGG8gKnlzcJEdEWrv8Nx+A212o1TR2SqR1Qdt+vBHJaKLS3Vvw2PDnw8LYHFsKj9uh382HFeAHGs2TpWXUmNulxhg/NeCDnfRikU/t6RkNVepEyE/ppODu3Vq29kWjCgqJ+juVVCsLPgI0bzm5GKWxBVPC9Nui+P8WonQRMi/zwNa67hEpgr24UrB6rzAQEY6KJTt9+oIqwRJoeWOfvRiWjAGxNQbkenECJ2GhQGSNY9oRdWYwFTJnlK16ZnM3RinqNFqVkfYJ9J0wbsd0TSMGrpdWycVQZqH8UmKYB99hVamicZIiObvoK4qfZo00Ln0BBXy8rD8Sbi2Vr5+/NYBZsi/mRCx9MjhSho8pqeb0e6LRRiaVCLT"
|
||||
`endif
|
||||
+225
@@ -0,0 +1,225 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_merlin_burst_uncompressor
|
||||
#(
|
||||
parameter ADDR_W = 16,
|
||||
parameter BURSTWRAP_W = 3,
|
||||
parameter BYTE_CNT_W = 4,
|
||||
parameter PKT_SYMBOLS = 4,
|
||||
parameter BURST_SIZE_W = 3,
|
||||
parameter SYNC_RESET = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input sink_startofpacket,
|
||||
input sink_endofpacket,
|
||||
input sink_valid,
|
||||
output sink_ready,
|
||||
|
||||
input [ADDR_W - 1: 0] sink_addr,
|
||||
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
|
||||
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
|
||||
input sink_is_compressed,
|
||||
input [BURST_SIZE_W-1 : 0] sink_burstsize,
|
||||
|
||||
output source_startofpacket,
|
||||
output source_endofpacket,
|
||||
output source_valid,
|
||||
input source_ready,
|
||||
|
||||
output [ADDR_W - 1: 0] source_addr,
|
||||
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
|
||||
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
|
||||
|
||||
output source_is_compressed,
|
||||
output [BURST_SIZE_W-1 : 0] source_burstsize
|
||||
);
|
||||
|
||||
function reg[63:0] bytes_in_transfer;
|
||||
input [BURST_SIZE_W-1:0] axsize;
|
||||
case (axsize)
|
||||
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
|
||||
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
|
||||
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
|
||||
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
|
||||
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
|
||||
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
|
||||
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
|
||||
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
|
||||
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
|
||||
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
|
||||
endcase
|
||||
|
||||
endfunction
|
||||
|
||||
localparam LG_PKT_SYMBOLS = $clog2(PKT_SYMBOLS);
|
||||
|
||||
wire [31:0] int_num_symbols = PKT_SYMBOLS;
|
||||
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
|
||||
|
||||
|
||||
reg burst_uncompress_busy;
|
||||
reg [BYTE_CNT_W : LG_PKT_SYMBOLS] burst_uncompress_byte_counter;
|
||||
wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
|
||||
wire first_packet_beat;
|
||||
wire last_packet_beat;
|
||||
|
||||
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
|
||||
assign burst_uncompress_byte_counter_lint = {burst_uncompress_byte_counter[BYTE_CNT_W - 1 : LG_PKT_SYMBOLS], {LG_PKT_SYMBOLS{1'b0}}};
|
||||
|
||||
assign source_byte_cnt =
|
||||
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
|
||||
assign source_valid = sink_valid;
|
||||
|
||||
assign last_packet_beat = ~sink_is_compressed |
|
||||
(
|
||||
burst_uncompress_busy ?
|
||||
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
|
||||
sink_valid & (sink_byte_cnt == num_symbols)
|
||||
);
|
||||
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : async_rst0
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_valid & source_ready & sink_valid) begin
|
||||
if (last_packet_beat) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
end
|
||||
else begin
|
||||
burst_uncompress_busy <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk ) begin
|
||||
if (internal_sclr) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
end
|
||||
else begin
|
||||
if (source_valid & source_ready & sink_valid) begin
|
||||
if (last_packet_beat) begin
|
||||
burst_uncompress_busy <= '0;
|
||||
end
|
||||
else begin
|
||||
burst_uncompress_busy <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (source_valid & source_ready & sink_valid) begin
|
||||
if (burst_uncompress_busy) begin
|
||||
burst_uncompress_byte_counter <= (burst_uncompress_byte_counter_lint[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS]) ;
|
||||
end
|
||||
else begin
|
||||
burst_uncompress_byte_counter <= sink_byte_cnt[BYTE_CNT_W-1:LG_PKT_SYMBOLS] - num_symbols[BYTE_CNT_W-1:LG_PKT_SYMBOLS];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
|
||||
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
|
||||
|
||||
wire [63:0] decoded_burstsize_wire;
|
||||
wire [ADDR_W-1:0] decoded_burstsize;
|
||||
|
||||
|
||||
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
|
||||
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
|
||||
generate
|
||||
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
|
||||
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
|
||||
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
|
||||
end
|
||||
else begin
|
||||
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (first_packet_beat & source_ready) begin
|
||||
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize);
|
||||
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0];
|
||||
|
||||
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
|
||||
(
|
||||
(first_packet_beat ?
|
||||
sink_addr :
|
||||
burst_uncompress_address_offset) + decoded_burstsize
|
||||
) &
|
||||
addr_width_burstwrap[ADDR_W-1:0];
|
||||
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (source_ready & source_valid) begin
|
||||
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign source_addr = first_packet_beat ? sink_addr :
|
||||
burst_uncompress_address_base | burst_uncompress_address_offset;
|
||||
assign source_burstwrap = sink_burstwrap;
|
||||
assign source_burstsize = sink_burstsize;
|
||||
|
||||
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
|
||||
assign source_endofpacket = sink_endofpacket & last_packet_beat;
|
||||
assign sink_ready = source_valid & source_ready & last_packet_beat;
|
||||
|
||||
assign source_is_compressed = 1'b0;
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FjCZ6EOCE8nGqnpNm7MFeLT3VsJGcOKET65CTIU/DyqHNIiknt0v+j5m0Lti6cjKQPS0454Wvq4G8xVDDmv9Qw357JkDz4Wa0fnla+hAeR+t6tAFcYV1ll+W3Jab/+TWhtNNVMcWtFAIr2E1tqubmGB412amTRsTpiSoytOueMC6KMd0Hzs2Da/oXc5sY89rsZ8s5ecFZSq9qf+na8CYLyUH6PCyMSKYVYRPNbLfdwltC/Rur/p0UGVFIkD26Li0I1TWra9pjpSuMlp05aZL0eeV+72LMPP2I7Iy1CeFyN8uZO6G1xSbFCT++LJNYK/whi+ODkbpCn8w5vZBUfUllvVejYrtzkEsu4SCIf5P+FsUn8PSvjtaZiQN44lXsTW12/ThPnUSh3e0qXVUuOa3RI8YKJuu4FVgpeFbYtkhUdE3672+Aq22EbP61O+Zt1Zx9NDYqTw6ETUT9CMI9/ekta1cCeyinKX92ITDjfd6D8goJhtD7J/Ii/Ip056gpO4cRJIB2pq/22f3B2dOs0Y4ggSZcEvwp/UAv6kj/fMjvxTqcYCIfX0/LhjNkckLlRc/vB8xWjtGWeD4+dJzXGxwgCNFOpbx0n+PIIHgPM2cxKoUVja199t8ORGrxeFc0Ln6kZfif0K57ayp/Zr/9uFHTT39fnBvGwFmCwptHIhWlwY77Hftbch+Z4/mhGFmljcZXynR+eyxUrhihRKPzOLo8vVa6JuGJ935I3iPDIpQA4BV0K1JuhpNgg83WLgeBDwnstCNfAgQE8RrBvMyNYLarI2"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc8uD44TTHYyehBVbu78YgMFYn3/KEapBIiX9P1XTAgAg7502qrWHHbXR6gSlLmNkc8iGL1BL24dMYV+udRkbItDFtrpx4UuEL1+KhP8eYTNOImCXgxI3DpUOYthzI3/fP1HE34bbVvc5wxiwP6PbTsoNuxOneZm49+3OO/Fa/XtWS9RG7awAr+cQbKIvZMks5hRYW1Xb8WqPIU0j3ZC3guR6XMMnnYEBN7Gp6lxWMpZYNf5RvM71qogowzDFZMArvWa9u0lqBDfB5BraawIsdZWVtCKy9/esY9tGkDFoIok73DBcoRezpzJNSO/eEZr50iVqZlG7UbEf6wxCRrhjgAmSG8YiFQWH2j2g3jEzE3nwCaoruF/k8ajJlfYxIEIvpcVWrP2EBHfkuTa2lTlShzVdZGhRhU9xWiBmgkHf1SaqkNz0Kl4J7W1+XRz9uIYuzSOqvGk9nMUnyXN9AjgKK3fKsRN2pJiD/PkqYA9oGZFty0fU6v3zlLU+J0Dz08YDsQFKstM0OIwYApDgqlOhdypwBze3li/7AAejHkqdIu/k1JCBm/l8a1OCRePUtSzyJytCGyESTLwlLDGIwqsIdF57Gdyq1WcD8ybc0zOeSikpVknjgCaSghi1eptxSuIrwg6EHJaMI3jbJyRogw1csiiDmXzjKWI6zKIyvCOeWJtgO8plAyAXCvfVY9Qo+Ohr1p9I05dqPYPVb3YLhpHAVD7XGC02+NEa9rQU8maDDE1xI2qC+i8hCGqYGvjuKuyQI2sZ46+CUxJi6uh3vwcr2O8"
|
||||
`endif
|
||||
+298
@@ -0,0 +1,298 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
module altera_merlin_reorder_memory
|
||||
#(
|
||||
parameter DATA_W = 32,
|
||||
ADDR_H_W = 4,
|
||||
ADDR_L_W = 4,
|
||||
VALID_W = 4,
|
||||
NUM_SEGMENT = 4,
|
||||
SYNC_RESET = 0,
|
||||
DEPTH = 16,
|
||||
USE_FIFO = 0
|
||||
|
||||
)
|
||||
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
input [DATA_W - 1 : 0] in_data,
|
||||
input in_valid,
|
||||
output in_ready,
|
||||
|
||||
output reg [DATA_W - 1 : 0] out_data,
|
||||
output reg out_valid,
|
||||
input out_ready,
|
||||
input [ADDR_H_W - 1 : 0] wr_segment,
|
||||
input [ADDR_H_W - 1 : 0] rd_segment
|
||||
|
||||
);
|
||||
|
||||
localparam SEGMENT_W = ADDR_H_W;
|
||||
|
||||
wire [ADDR_H_W + ADDR_L_W - 1 : 0] mem_wr_addr;
|
||||
reg [ADDR_H_W + ADDR_L_W - 1 : 0] mem_rd_addr;
|
||||
wire [ADDR_L_W - 1 : 0] mem_wr_ptr;
|
||||
wire [ADDR_L_W - 1 : 0] mem_rd_ptr;
|
||||
reg [ADDR_L_W - 1 : 0] mem_next_rd_ptr;
|
||||
reg [DATA_W - 1 : 0] out_payload;
|
||||
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_ready;
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_valid;
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_valid;
|
||||
wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_ready;
|
||||
wire [ADDR_L_W - 1 : 0] pointer_ctrl_wr_ptr [NUM_SEGMENT];
|
||||
wire [ADDR_L_W - 1 : 0] pointer_ctrl_rd_ptr [NUM_SEGMENT];
|
||||
wire [ADDR_L_W - 1 : 0] pointer_ctrl_next_rd_ptr [NUM_SEGMENT];
|
||||
|
||||
|
||||
(* ramstyle="no_rw_check" *) reg [DATA_W - 1 : 0] mem [DEPTH - 1 : 0];
|
||||
always @(posedge clk) begin
|
||||
if (in_valid && in_ready)
|
||||
mem[mem_wr_addr] = in_data;
|
||||
out_payload = mem[mem_rd_addr];
|
||||
end
|
||||
|
||||
assign mem_wr_ptr = pointer_ctrl_wr_ptr[wr_segment];
|
||||
|
||||
assign mem_wr_addr = {wr_segment, mem_wr_ptr};
|
||||
|
||||
wire endofpacket;
|
||||
wire [ADDR_H_W - 1: 0] next_rd_segment;
|
||||
assign next_rd_segment = ((rd_segment + 1'b1) == NUM_SEGMENT) ? '0 : rd_segment + 1'b1;
|
||||
|
||||
genvar j;
|
||||
generate
|
||||
if (USE_FIFO == 1) begin
|
||||
reg [ADDR_H_W-1:0]rd_segment_d1;
|
||||
always@(posedge clk) begin
|
||||
rd_segment_d1 <= rd_segment;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
out_valid = (rd_segment_d1 == NUM_SEGMENT) ? 1'b0 : pointer_ctrl_out_valid[rd_segment_d1];
|
||||
out_data = out_payload;
|
||||
end
|
||||
assign endofpacket = out_data[0];
|
||||
always_comb begin
|
||||
mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
|
||||
mem_rd_addr = {rd_segment, mem_next_rd_ptr};
|
||||
end
|
||||
|
||||
for (j = 0; j < NUM_SEGMENT; j = j + 1) begin : pointer_signal
|
||||
assign pointer_ctrl_in_valid[j] = (wr_segment == j) && in_valid;
|
||||
assign pointer_ctrl_out_ready[j] = (rd_segment_d1 == j) && out_ready;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always_comb begin
|
||||
out_data = out_payload;
|
||||
out_valid = pointer_ctrl_out_valid[rd_segment];
|
||||
end
|
||||
assign endofpacket = out_payload[0];
|
||||
always_comb begin
|
||||
if (out_valid && out_ready && endofpacket) begin
|
||||
mem_next_rd_ptr = pointer_ctrl_rd_ptr[next_rd_segment];
|
||||
mem_rd_addr = {next_rd_segment, mem_next_rd_ptr};
|
||||
end
|
||||
else begin
|
||||
mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
|
||||
mem_rd_addr = {rd_segment, mem_next_rd_ptr};
|
||||
end
|
||||
end
|
||||
|
||||
for (j = 0; j < NUM_SEGMENT; j = j + 1)
|
||||
begin : pointer_signal
|
||||
assign pointer_ctrl_in_valid[j] = (wr_segment == j) && in_valid;
|
||||
assign pointer_ctrl_out_ready[j] = (rd_segment == j) && out_ready;
|
||||
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
assign in_ready = pointer_ctrl_in_ready[wr_segment];
|
||||
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < NUM_SEGMENT; i = i + 1)
|
||||
begin : each_segment_pointer_controller
|
||||
memory_pointer_controller
|
||||
#(
|
||||
.SYNC_RESET (SYNC_RESET),
|
||||
.ADDR_W (ADDR_L_W)
|
||||
) reorder_memory_pointer_controller
|
||||
(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (pointer_ctrl_in_ready[i]),
|
||||
.in_valid (pointer_ctrl_in_valid[i]),
|
||||
.out_ready (pointer_ctrl_out_ready[i]),
|
||||
.out_valid (pointer_ctrl_out_valid[i]),
|
||||
.wr_pointer (pointer_ctrl_wr_ptr[i]),
|
||||
.rd_pointer (pointer_ctrl_rd_ptr[i]),
|
||||
.next_rd_pointer (pointer_ctrl_next_rd_ptr[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
|
||||
module memory_pointer_controller
|
||||
#(
|
||||
parameter SYNC_RESET = 0,
|
||||
parameter ADDR_W = 4
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
output reg in_ready,
|
||||
input in_valid,
|
||||
input out_ready,
|
||||
output reg out_valid,
|
||||
output [ADDR_W - 1 : 0] wr_pointer,
|
||||
output [ADDR_W - 1 : 0] rd_pointer,
|
||||
output [ADDR_W - 1 : 0] next_rd_pointer
|
||||
);
|
||||
|
||||
reg [ADDR_W - 1 : 0] incremented_wr_ptr;
|
||||
reg [ADDR_W - 1 : 0] incremented_rd_ptr;
|
||||
reg [ADDR_W - 1 : 0] wr_ptr;
|
||||
reg [ADDR_W - 1 : 0] rd_ptr;
|
||||
reg [ADDR_W - 1 : 0] next_wr_ptr;
|
||||
reg [ADDR_W - 1 : 0] next_rd_ptr;
|
||||
reg full, empty, next_full, next_empty;
|
||||
reg read, write, internal_out_ready, internal_out_valid;
|
||||
|
||||
assign incremented_wr_ptr = wr_ptr + 1'b1;
|
||||
assign incremented_rd_ptr = rd_ptr + 1'b1;
|
||||
assign next_wr_ptr = write ? incremented_wr_ptr : wr_ptr;
|
||||
assign next_rd_ptr = read ? incremented_rd_ptr : rd_ptr;
|
||||
assign wr_pointer = wr_ptr;
|
||||
assign rd_pointer = rd_ptr;
|
||||
assign next_rd_pointer = next_rd_ptr;
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign read = internal_out_ready && !empty;
|
||||
assign write = in_ready && in_valid;
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : aysnc_reg0
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
wr_ptr <= 0;
|
||||
rd_ptr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
wr_ptr <= next_wr_ptr;
|
||||
rd_ptr <= next_rd_ptr;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
|
||||
always_ff @(posedge clk )
|
||||
begin
|
||||
if (internal_sclr)
|
||||
begin
|
||||
wr_ptr <= 0;
|
||||
rd_ptr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
wr_ptr <= next_wr_ptr;
|
||||
rd_ptr <= next_rd_ptr;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
always_comb
|
||||
begin
|
||||
next_full = full;
|
||||
next_empty = empty;
|
||||
if (read && !write)
|
||||
begin
|
||||
next_full = 1'b0;
|
||||
if (incremented_rd_ptr == wr_ptr)
|
||||
next_empty = 1'b1;
|
||||
end
|
||||
if (write && !read)
|
||||
begin
|
||||
next_empty = 1'b0;
|
||||
if (incremented_wr_ptr == rd_ptr)
|
||||
next_full = 1'b1;
|
||||
end
|
||||
end
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : aysnc_reg1
|
||||
always_ff @(posedge clk or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
empty <= 1;
|
||||
full <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
empty <= next_empty;
|
||||
full <= next_full;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
else begin
|
||||
|
||||
always_ff @(posedge clk )
|
||||
begin
|
||||
if (internal_sclr)
|
||||
begin
|
||||
empty <= 1;
|
||||
full <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
empty <= next_empty;
|
||||
full <= next_full;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
always_comb
|
||||
begin
|
||||
in_ready = !full;
|
||||
out_valid = !empty;
|
||||
internal_out_ready = out_ready;
|
||||
end
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FgNOzQxIiBqloeezeBLMvtkKUBhxMD3+Oo3xN1J0G8wxw3m2tfBIK+PZfw0dM+aODPW4BrHQ8jXT/rxpkBlJSU9VIe3l+0sa8oec+KlgheFD4eeLOxkhJLkj35H8K3uNhDhppXo2aGgKhhiKjPCdJGoKhjdBWrpKatiVsxckYfOqBQDYJB2LzNHlX0duhj7sI78Fw9FFfyt2aWmHcMIpgbcsSvu40Cy7XvwomDz+kKLQepfFp5KEZcpE4a99GTQbMUeCjvvDlZvnR//1gIKMVg6+2ptfDOrCilgK1rkKD365XT7ixV+Zjp0ScGmbe7XFca90gPJBhbNPGcZNPdBhEIA/l3ZAQ11Ula6DVXlUNQjKr9OPRCqJN/mSMkJKyOlAxua2AZJlh3fklRMWqcBkZ3XuX3ZjaiNuf3N7KiNgvQFBD+6c/OVivw0N1yhHHM9iOyTlQ1oXXbgdMahTIAYgS9EXT6T2JV6YNswczQsmN7RNaaACftG1b68gBf6VtleBRK0qcg1Hpq7dw++/HkO8uyIaj4S7sjgpabarqoonnFvtmSxWSXZ6MyasoAMgYosSldiAwBbgvpH4fA1Jo+c7BKunjaAIOWZDtO6724wchS9Nvl2BNVcUKwvI0Ki/SJzIkZ+vVeckd4dTLigRvlHjE9r7JIAs4pvQvAWzoQ1In9BZ8Qpx3HLOPZiQ23pTK299zf0P4CanxCI8nGPYaLuNbZ4mAe5rvwby98ys2rOLgLsPBllktDC/UTdu32qUlfH2GrED9hmwj3pB6Yj9bQu8tVg"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc8q+Rn1IqaPVmfJEmIgovsCaxdbX6aYotRNqalpl5/M0FhgttWMq2oQKFgpLEi2PNlhjj8IKLVYgd9lh23bTVukLZnJ24MyKR5wz2CuvQ82c1MRiTQTFR8in8/XJ13JKg48C7//OO8/gw3CJmH33WUEyu4sUaXznEEwzDVD/5KlsT/rGvyle2KZpIacou3PpyrmZWQVAf4BoAYjhg9xla4dktt6g3Z3X8m+VS1jsrKqwWk4CDMYDi1COvqHX/Z3sZI6r1InBkrfzapG7w1BUo/u+iYVHItmcPGqHIrcHuN/fnEPhYAC2jy/wUKuHTNn99czpkFDZBv9EOjlMHUz/IiGGiLg7RguMS86tHhMLqoDYcljFBitSg/4nKB4afFJNqf0/Bv/ITD24ioY6Rd49r/awW/AicnbA9QUOUeqe3tiBPqqdNt/pCYd1YjWhkt3yxj/Syuwf6AHsylNJ9lLfChxq/hrMQbeC3oDQhIqDckCX25U6WEqZlxWjnkDhZvSvCm9XOKBLDVQHLkuomun39g+98gQO96XK/c1HQY2VJ0vRJwhf8eulICik0kxJ27nfvDdnr2WFlODD0BPV2LGydSRr/JHixqyP4nTGnO6/1n40iGMgP+RTEAyzIOS8gk4KFw3ecVDF+9+LdGa8L84LX4KNKQ0g8bkS+aisFiba/QM6FpGeVGYhl3/5MCTpFm0F5D+IZC49E/uUmcBnVkBiCimL0K9yIHRaqFj3NuV5WQ5cOLEqweDZYNZ2tm1oVGuweHfRpSEoIA1mizhC5H6uE0i"
|
||||
`endif
|
||||
+287
@@ -0,0 +1,287 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_controller
|
||||
#(
|
||||
parameter NUM_RESET_INPUTS = 6,
|
||||
parameter USE_RESET_REQUEST_IN0 = 0,
|
||||
parameter USE_RESET_REQUEST_IN1 = 0,
|
||||
parameter USE_RESET_REQUEST_IN2 = 0,
|
||||
parameter USE_RESET_REQUEST_IN3 = 0,
|
||||
parameter USE_RESET_REQUEST_IN4 = 0,
|
||||
parameter USE_RESET_REQUEST_IN5 = 0,
|
||||
parameter USE_RESET_REQUEST_IN6 = 0,
|
||||
parameter USE_RESET_REQUEST_IN7 = 0,
|
||||
parameter USE_RESET_REQUEST_IN8 = 0,
|
||||
parameter USE_RESET_REQUEST_IN9 = 0,
|
||||
parameter USE_RESET_REQUEST_IN10 = 0,
|
||||
parameter USE_RESET_REQUEST_IN11 = 0,
|
||||
parameter USE_RESET_REQUEST_IN12 = 0,
|
||||
parameter USE_RESET_REQUEST_IN13 = 0,
|
||||
parameter USE_RESET_REQUEST_IN14 = 0,
|
||||
parameter USE_RESET_REQUEST_IN15 = 0,
|
||||
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
|
||||
parameter SYNC_DEPTH = 2,
|
||||
parameter RESET_REQUEST_PRESENT = 0,
|
||||
parameter RESET_REQ_WAIT_TIME = 3,
|
||||
parameter MIN_RST_ASSERTION_TIME = 11,
|
||||
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
|
||||
parameter ADAPT_RESET_REQUEST = 0
|
||||
)
|
||||
(
|
||||
input reset_in0,
|
||||
input reset_in1,
|
||||
input reset_in2,
|
||||
input reset_in3,
|
||||
input reset_in4,
|
||||
input reset_in5,
|
||||
input reset_in6,
|
||||
input reset_in7,
|
||||
input reset_in8,
|
||||
input reset_in9,
|
||||
input reset_in10,
|
||||
input reset_in11,
|
||||
input reset_in12,
|
||||
input reset_in13,
|
||||
input reset_in14,
|
||||
input reset_in15,
|
||||
input reset_req_in0,
|
||||
input reset_req_in1,
|
||||
input reset_req_in2,
|
||||
input reset_req_in3,
|
||||
input reset_req_in4,
|
||||
input reset_req_in5,
|
||||
input reset_req_in6,
|
||||
input reset_req_in7,
|
||||
input reset_req_in8,
|
||||
input reset_req_in9,
|
||||
input reset_req_in10,
|
||||
input reset_req_in11,
|
||||
input reset_req_in12,
|
||||
input reset_req_in13,
|
||||
input reset_req_in14,
|
||||
input reset_req_in15,
|
||||
|
||||
|
||||
input clk,
|
||||
output reg reset_out,
|
||||
output reg reset_req
|
||||
);
|
||||
|
||||
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
|
||||
|
||||
localparam MIN_METASTABLE = 3;
|
||||
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
|
||||
|
||||
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
|
||||
|
||||
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
|
||||
MIN_RST_ASSERTION_TIME + 1 :
|
||||
(
|
||||
(MIN_RST_ASSERTION_TIME > LARGER)?
|
||||
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
|
||||
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
|
||||
);
|
||||
|
||||
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
|
||||
|
||||
wire merged_reset;
|
||||
wire merged_reset_req_in;
|
||||
wire reset_out_pre;
|
||||
wire reset_req_pre;
|
||||
|
||||
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
|
||||
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
|
||||
reg r_sync_rst;
|
||||
reg r_early_rst;
|
||||
|
||||
assign merged_reset = (
|
||||
reset_in0 |
|
||||
reset_in1 |
|
||||
reset_in2 |
|
||||
reset_in3 |
|
||||
reset_in4 |
|
||||
reset_in5 |
|
||||
reset_in6 |
|
||||
reset_in7 |
|
||||
reset_in8 |
|
||||
reset_in9 |
|
||||
reset_in10 |
|
||||
reset_in11 |
|
||||
reset_in12 |
|
||||
reset_in13 |
|
||||
reset_in14 |
|
||||
reset_in15
|
||||
);
|
||||
|
||||
assign merged_reset_req_in = (
|
||||
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
|
||||
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
|
||||
);
|
||||
|
||||
|
||||
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
|
||||
|
||||
assign reset_out_pre = merged_reset;
|
||||
assign reset_req_pre = merged_reset_req_in;
|
||||
|
||||
end else begin
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
|
||||
)
|
||||
alt_rst_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset),
|
||||
.reset_out (reset_out_pre)
|
||||
);
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_req_sync_uq1
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (merged_reset_req_in),
|
||||
.reset_out (reset_req_pre)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
|
||||
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
|
||||
always @* begin
|
||||
reset_out = reset_out_pre;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
|
||||
|
||||
wire reset_out_pre2;
|
||||
|
||||
altera_reset_synchronizer
|
||||
#(
|
||||
.DEPTH (SYNC_DEPTH+1),
|
||||
.ASYNC_RESET(0)
|
||||
)
|
||||
alt_rst_sync_uq2
|
||||
(
|
||||
.clk (clk),
|
||||
.reset_in (reset_out_pre),
|
||||
.reset_out (reset_out_pre2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
reset_out = reset_out_pre2;
|
||||
reset_req = reset_req_pre;
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
|
||||
// synthesis translate_off
|
||||
initial
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
// synthesis translate_on
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
|
||||
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
|
||||
begin
|
||||
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
|
||||
end
|
||||
else
|
||||
begin
|
||||
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
|
||||
3'b000: r_sync_rst <= 1'b0;
|
||||
3'b001: r_sync_rst <= 1'b0;
|
||||
3'b010: r_sync_rst <= 1'b0;
|
||||
3'b011: r_sync_rst <= 1'b1;
|
||||
3'b100: r_sync_rst <= 1'b1;
|
||||
3'b101: r_sync_rst <= 1'b1;
|
||||
3'b110: r_sync_rst <= 1'b1;
|
||||
3'b111: r_sync_rst <= 1'b1;
|
||||
default: r_sync_rst <= 1'b1;
|
||||
endcase
|
||||
|
||||
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
|
||||
2'b00: r_early_rst <= 1'b0;
|
||||
2'b01: r_early_rst <= 1'b1;
|
||||
2'b10: r_early_rst <= 1'b0;
|
||||
2'b11: r_early_rst <= 1'b1;
|
||||
default: r_early_rst <= 1'b1;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @* begin
|
||||
reset_out = r_sync_rst;
|
||||
reset_req = r_early_rst;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FjQ5TwTkkYxaDN9I9CSPzuDTd87Wnu0FwZHNbtwNNuU3y829+BCYy2eudOAj1LWYek3IiZRMRvE61afAkXZzSUJjtlCTKElF7lmX5q6u3zedoC9dYFN1+Rt02eFjYzM9Bzt/+NtaFeknqOY6CycMNjwwcturqyn7znp12BJqJJH51UHxUijPYYyq3gGxCHQTMgvzTMZJdTVrGOoUivoFsuhS2AnfhiPAfJ9AH9UGEV//IIA3dEeQlfx4uN+B0dpHY8ynv3gWDslyARveYyWKPYt7f9Bbm+In6XhtNJzGB4NgK1r587QyTYEFe5iBrf4t7Yp01VB1dnCKf1sRIHep3Mm6CVw3Uy1C//6M43ZMLxNNHMZU7kYSP/OOp1jkUBJY/AzWYIg+UgIwtNBFY4KM3gR9ftS54h7uG/m3Sfxo4VTVLu+a1HIQSd88DkCRAnqUdKgWd/tEACVq2s1AZLMz6erv7a3TMGu9nyXITksC8zZBIVZyFBNEpDPRaVBN8WZLTvsPYe6BozsaSm8mxdVF5tLRUBg98Zsw3j8t/p5JBLWWSLtTqaXM+7GKkRQuw5DWz76iz9X8UlCxLe1J26xrbt+NYdV3hxVvj9enTfoljNeAYy9z1DB4yKDAVS09NG2cy21sAnZQ3+5zrgl+xcfW1XHFwAuKz94Hral9cNZZx7XBLlp0GzQlkflbPl6bM0Pjkeqf7oxH6Cog7iOqPAMpqQCaCwiOVNFvcZPQW3EBvyrS9hnp+SuQz95h1PkELOMA6xGO89XouFv5/aGb9tOkCM0"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc/lND3DiMvmZqoiv9GS51K8t28/QnQ4HzVfs/vIEHN5TJn7dUxjPGNHYWdqkt4lj3VbRNvo1T5k4BGHywuy+7KwhBExBctCPSuFZjLCRXMeyCCBurSertYAKT1BtQMcOuaQv8h5BnDfmgH2JUZEeFcAN11c5LBGnBA1FmylVJqvSbFlH74fzBP08DIHX3rjjl86dHwp47l1t2lrjg9mVwV1nbth8edBBX95misrXyKJDnFnnaeoWrwIKoMu3eW1Qle5WrnaPJt/4Pij66wtM6UUVgxUYzo0z2Ypj2FroHQ08kX1tAfKmrV8eQCidrdQDXCVligr8a76qgcPwgqrojdwLpzWlUh22LO02fLAW+tpn2Kw5lQ0NF9JRtKSIidnPAbeE2iHnEIPeecE2BCZclKfc0K71o9Di00flBJlxMQOywd90bu9KSJJtNEazPdZiAaL3vr/Ie2Wh0RPf5kkMbm3kDFKkgmtad0I8bMRFIZsnhQdJriFFAGIT+jpu45jR1/wWvvrNw2eQ76GU8XuRVkyb662f+PVg3UZv7WIspoo6E5A/JdfoRhIbVIrSWVbQ24F/6zy+NGWgjKUAf15yJLzKb8ZlqMZ4R+5iIis4RX+TjMVUwSoK3cRnjEZFGAC52cnWEF5DdeiX038VTvUWQE3LKfvHpZDhCJwAM4smx/vFv+hoJgrXbNcsmrc9StyjXrSpPUFsgZ4+kBAV8LaCpG8wvFHH561orplJM3lsDTMHuhBxrcEIKjMfcUjdQxnnOFPyuh7fbmCc65Y0iUt2O1f"
|
||||
`endif
|
||||
+70
@@ -0,0 +1,70 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_reset_synchronizer
|
||||
#(
|
||||
parameter ASYNC_RESET = 1,
|
||||
parameter DEPTH = 2
|
||||
)
|
||||
(
|
||||
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
|
||||
|
||||
input clk,
|
||||
output reset_out
|
||||
);
|
||||
|
||||
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
|
||||
reg altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
generate if (ASYNC_RESET) begin
|
||||
|
||||
always @(posedge clk or posedge reset_in) begin
|
||||
if (reset_in) begin
|
||||
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
|
||||
altera_reset_synchronizer_int_chain_out <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end else begin
|
||||
|
||||
always @(posedge clk) begin
|
||||
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
|
||||
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
|
||||
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
|
||||
end
|
||||
|
||||
assign reset_out = altera_reset_synchronizer_int_chain_out;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1Fht4277Y+91VJnUrh/5hrFqOADwKRqiLsdt/cqGLEzhQQcrWmg51Yy5mXnSiw6FfImIkgD8Ck/ZT4cliEkfBJ8MvlFHiucF4gjdNZhvvfZU3j81OpYa3tPH5H2W4J0+SkdP2DPeAapjXi9YkQVQjsI0v4dbWpeIG8fZzNZQb9r7IdLCqtnNFCmiFw1vqqzdGnE27id82+iufRydCYAVk76+AWQbaZyosgkUXLqY4VRCSoh4OJxErbAAjmhklcR3qbZtNBCdqCF9bqryWupZkMpklXsfe5G7KRiw8bMAjFvuAkGQdFiOzIojPkWtODBv1c3i4gjsuZE3PgHhRr39wn7obP7Zbf3zLQj/+o5QqVZOBuvsEIcRop+a6TucmMyF05/Unhp5C8/X3pneoq2+xZlVNyoTAWvXxsJsJerJ6mVoXwgs0Z3s450Mwxyi5f58hSPcUlD0U5YH1oljVxcbGyTA/kGzhItzAQlqjUK8Y6PiM7sgNM8c2LCi+syVlvevi00Di4+5Yflxzgid71tikJyvSLR2JIWvDyEwfW1F979kr7GG6qPKwZe6wFqkahaYAqD1kRkCW5dk+TcXzoc1iadVqlx0CgQIAleg7RoO0x/ejjgjSGMJ+kMMBQjDfpp8ulvK+sQlLhAx4dAtyXhMd1yE2XZo2y0Cet2gTSahyRCLfrD8ATSo+QfCgxeAyrOgC1PLuBivxvInziHwS9gnXV4igXcvshPg1Ix27cLQaYhmSMa44reiY9GfUxWuPfMvegh30ope1L7aenwCK7bSPmwX"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc/5PJSo8DpGzONbGXw06KOOJeXx0rtSi+pZ+YjYrtPEe+XIJQcDqqtlWzxg9z3BVgyItoC7gBmv6m14y5UN59zUVhEJXrlMlnJytLXvG4KamX/u/j3GC09c4lyFyMwKJhT6Nnp/zqR9BdvpBLmHhkjkjtee5msl8Sl8qBRET8aoi5DGCSNbpyFqCKRQnHlow/sbgPezscukFkf5igyPC1KRcRq7IJ3AMrFa2dc25qTOucf27bmprzcxeus7tMrlXl+ahKUJVNVwvjmcMViw69fnyTF1gW47a6MnSn1XSxauBSdxzVwwrPK5byRpcou5LlD44VWZCOcf1qTlIvjZ/1R94LEO7K5cE02LIC65Ipjwpq8RL56CISxK5HhcVZ2qWgHznVqAQ6IVKNCTvf54v3vfNlzmU2INgUc4hIVoP8k/M6wUOQi1H6bIFbBhdcUfa/6HJ2uv0PjjAu66fpQFJErWAcd5x0/SH/jtbKtmojjNK7Mt+H7OX+3dNZ1Q3irw6jh8OBsrJnM76PnQpuYvEqg/9sYsP4ocjIhUBgwyESFgTH3/uzhdbCgW4Vy4+XCYWHWajIu8c3Mp2Tepi9qzxEuVXd/9iBxTFspzm7W6j7YIslXv667OqVZYen4r014HQI25UaJl9R7AvqNXAsw2eFTxIXqNC7MphEaTJMo11icuOdPIcy29Ahms/Je746xjmv2Kh0gfyCD25eDTkoL2aOSvJsCSoTdH9kXbmVKoHVseAH4X6t34q/8haMVtq8oTD+bbiyz8KvPTQivCpf9Q0+VC"
|
||||
`endif
|
||||
+233
@@ -0,0 +1,233 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module altera_std_synchronizer_nocut (
|
||||
clk,
|
||||
reset_n,
|
||||
din,
|
||||
dout
|
||||
);
|
||||
|
||||
parameter depth = 3;
|
||||
parameter rst_value = 0;
|
||||
|
||||
parameter retiming_reg_en = 0;
|
||||
|
||||
input clk;
|
||||
input reset_n;
|
||||
input din;
|
||||
output dout;
|
||||
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
|
||||
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
|
||||
|
||||
// synthesis translate_off
|
||||
`ifndef QUARTUS_CDC
|
||||
initial begin
|
||||
if (retiming_reg_en == 0 ) begin
|
||||
if (depth <2) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (depth <4) begin
|
||||
$display("%m: Error: synchronizer length: %0d less than 4 with retiming enabled.", depth);
|
||||
end
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM
|
||||
|
||||
reg[31:0] RANDOM_SEED = 123456;
|
||||
wire next_din_s1;
|
||||
wire dout;
|
||||
reg din_last;
|
||||
reg random;
|
||||
event metastable_event;
|
||||
|
||||
initial begin
|
||||
$display("%m: Info: Metastable event injection simulation mode enabled");
|
||||
random = $random;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset_n == 0)
|
||||
random <= $random(RANDOM_SEED);
|
||||
else
|
||||
random <= $random;
|
||||
end
|
||||
|
||||
assign next_din_s1 = (din_last ^ din) ? random : din;
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_last <= din;
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
|
||||
else
|
||||
din_s1 <= next_din_s1;
|
||||
end
|
||||
|
||||
`else
|
||||
|
||||
// synthesis translate_on
|
||||
generate if (rst_value == 0)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b0;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (rst_value == 1)
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
din_s1 <= 1'b1;
|
||||
else
|
||||
din_s1 <= din;
|
||||
end
|
||||
endgenerate
|
||||
// synthesis translate_off
|
||||
|
||||
`endif
|
||||
|
||||
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
|
||||
always @(*) begin
|
||||
if (reset_n && (din_last != din) && (random != din)) begin
|
||||
$display("%m: Verbose Info: metastable event @ time %t", $time);
|
||||
->metastable_event;
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
generate if (rst_value == 0) begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b0}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b0}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
else begin
|
||||
if (retiming_reg_en == 0) begin
|
||||
if (depth < 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= din_s1;
|
||||
end
|
||||
end else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg <= {dreg[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg[depth-2];
|
||||
end
|
||||
|
||||
else begin
|
||||
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [1:0] dreg1;
|
||||
reg [depth-4:0] dreg2;
|
||||
wire [depth-2:0] dreg3;
|
||||
|
||||
assign dreg3 = {dreg2,dreg1};
|
||||
|
||||
if (depth <= 3) begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
dreg1 <= {depth-1{1'b1}};
|
||||
else
|
||||
dreg1 <= din_s1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always @(posedge clk or negedge reset_n) begin
|
||||
if (reset_n == 0)
|
||||
{dreg2,dreg1} <= {depth-1{1'b1}};
|
||||
else
|
||||
{dreg2,dreg1} <= {dreg3[depth-3:0], din_s1};
|
||||
end
|
||||
end
|
||||
assign dout = dreg3[depth-2];
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "nATEpDWf3CgajPjgH0t9FI3P3v7c7W2p1Bjo8KPiWXptDDKP83tHlZV4/kOjbfP5B3iPKq3r9UGmKAo7uM5E+NrMJJrWKQHFxNhuD9YH7WIm4w92BUZP4bPiPCFjEfA8Gg2F5To+TwSe7HVsQs+/7MZQj0QmDr2hjiVbFLL88xfR21RarRUIjnXzluc0JvTFFI13vcHyvhug/HSbBYjOOLVxyFVn/zaj46Yp0VXaMOw1nlZhJnKcXQsJx0gJoXbJzhqXMAEUYlyGq9c1wdgQSBXE8l1jREheSOvQ0cfeRX88+8g4+XINHMQVcPl0OjfoyRZ3JmyxFBhhTKaBFTuwa9JPGjKsP23EId66pNJyNHw+kx9hfuti4zKPh+4qDKzImqe3EvW9LvOpRFmLrX2Uxvpo1FTEMNxGrXb1ke0Z7vcuC95O72ct3MSS89UfL7tYbP1vXYWRLQ8C82nSl0K+WK6SnZZVbZLDHRpCCYtfelsLw7JJdfz2uhT+702K/cMywBt9oqHNmoTZubqV7787HlJwx1FqO2KI+EJorlVBtLfK7PJ4fOhDL7SQ23Tmb67gx0VsXcDYP/832+fsZsVMzSvS/3CiJjMDZAG0NuCMdvDXLySCkFUgqtHyScmaaundWnVAa+e66Sx7mp7VFD2d91rm0/mT6kUthgdXh1QRF/0/Ip6hP5huj45XBDVGZvX1ZQluQO/BXZXjyiuHXjM+ciVm9ZSPvoSKLFn9QolBYAEnDPQ3meQJpCkgBKNo6sG2vgaH89bYRlanB14+4Oqf7bAr3180nN8Z9LDTJRFfw0lWJ3OGhrRI1NyQ5YEzAsUO+H029+cDiasAmGbTULVUCBCkqyPlboA6mBIxBGWHngeFhEu5HagTbe2Xbew0EmTDW/5vz/BCGK4o27Md24EDRxAKVS/gyU4yVrE2LtGN26kHjxWvloc59PFbZL7EjLB+5tx8lFaZU+DwmAVNAwauX4DQYtDhS9XUFO0Pzj7ryCBHw0ifW2bHRF/R/fHkbo30"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc/+wy8E8ETTe1+Zbc/9GcIueWTJA2iZreuMmukHROZYk3U4Sj+jDUyi4lItTYhCWIWvXCDr3EeE3gwbnvHgUJsLLGYdr4J5OlDCKId8OXAHAW+Ws8ZGidFJZ3CedIrTvJWQyEggo8sEsUWwpm+HNLKo3KtNbPTFdvAQ1URSNyctPQA5nF/bXjMtTKB+co29WOstGrrQBTZZznlWv/xUFqRqRnlTVxlF9E/AdFXX7QhqSaf/+SpCQ42ULLZTWtE1/0IIVVoV6qlnX2sqOCR+oh9ZP68Z2TpNguCjWJDb9ElZeXvwYwHdE1AA6+PFER5hsr5trTrUdQpac9EOHUqdSWybamnC17Jwj64+WKoU1Cnn/Z4JJxSrq4cr7fQnZQi4FVhxZKGmAPbHeDYxsWRi8H+XlbNn5tkNmiVoSEDNW+ZyscnY6wfI7ftY2OAl729LqsmzYSfiDIxxyJtxRFUXePUEAIHkZsqD3kBESXrWEdW07ZlGl5R5f7LNdHG6sBxiQTeP0Zk6W34R6TZU79Zy8UkKQHE5ULHpgCGU4YKz5D7da5DC9vJv2HGdesyQaFhV8Slkpanj8v602u+4/ZrQ7G/vOJ5GLMGQjuw5oyIaxjQ+cVSsGJMwZFHv33zt87Smy8Ahmp/Niqr6BO5Hs0wfQ5QyoDs2nHKoOrZGI9OnfgHNsRMqwteRqcSU6e3PXsVKL82PmphHWjY0CSC5g+E5VV6HwAAdwnZpsryz6DBszifPeWMcSflqGPZLaYvm+7HN+TXIBrwPQGYhUA/v3/bDUTEe"
|
||||
`endif
|
||||
+294
@@ -0,0 +1,294 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module altera_wrap_burst_converter
|
||||
#(
|
||||
parameter
|
||||
MAX_IN_LEN = 16,
|
||||
MAX_OUT_LEN = 4,
|
||||
ADDR_WIDTH = 12,
|
||||
BNDRY_WIDTH = 12,
|
||||
NUM_SYMBOLS = 4,
|
||||
AXI_SLAVE = 0,
|
||||
OPTIMIZE_WRITE_BURST = 0,
|
||||
SYNC_RESET = 0,
|
||||
LEN_WIDTH = log2ceil(MAX_IN_LEN) + 1,
|
||||
OUT_LEN_WIDTH = log2ceil(MAX_OUT_LEN) + 1,
|
||||
LOG2_NUMSYMBOLS = log2ceil(NUM_SYMBOLS)
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
input enable_write,
|
||||
input enable_read,
|
||||
|
||||
input [LEN_WIDTH - 1 : 0] in_len,
|
||||
input [LEN_WIDTH - 1 : 0] first_len,
|
||||
input in_sop,
|
||||
|
||||
input [ADDR_WIDTH - 1 : 0] in_addr,
|
||||
input [ADDR_WIDTH - 1 : 0] in_addr_reg,
|
||||
input [BNDRY_WIDTH - 1 : 0] in_boundary,
|
||||
input [BNDRY_WIDTH - 1 : 0] in_burstwrap,
|
||||
input [BNDRY_WIDTH - 1 : 0] in_burstwrap_reg,
|
||||
|
||||
output reg [LEN_WIDTH - 1 : 0] out_len,
|
||||
output reg [LEN_WIDTH - 1 : 0] uncompr_out_len,
|
||||
|
||||
output reg [ADDR_WIDTH - 1 : 0] out_addr,
|
||||
output reg new_burst_export
|
||||
);
|
||||
|
||||
localparam
|
||||
OUT_BOUNDARY = MAX_OUT_LEN * NUM_SYMBOLS,
|
||||
ADDR_SEL = log2ceil(OUT_BOUNDARY);
|
||||
|
||||
reg [LEN_WIDTH - 1 : 0] remaining_len;
|
||||
reg [LEN_WIDTH - 1 : 0] next_out_len;
|
||||
reg [LEN_WIDTH - 1 : 0] next_rem_len;
|
||||
reg [LEN_WIDTH - 1 : 0] uncompr_remaining_len;
|
||||
reg new_burst;
|
||||
reg uncompr_sub_burst;
|
||||
reg [LEN_WIDTH - 1 : 0] next_uncompr_out_len;
|
||||
reg [LEN_WIDTH - 1 : 0] next_uncompr_sub_len;
|
||||
|
||||
wire [OUT_LEN_WIDTH - 1 : 0] max_out_length;
|
||||
assign max_out_length = MAX_OUT_LEN[OUT_LEN_WIDTH - 1 : 0];
|
||||
|
||||
reg [ADDR_WIDTH - 1 : 0] extended_burstwrap;
|
||||
reg [ADDR_WIDTH - 1 : 0] extended_burstwrap_reg;
|
||||
|
||||
always_comb begin
|
||||
extended_burstwrap = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap[BNDRY_WIDTH - 1]}}, in_burstwrap};
|
||||
extended_burstwrap_reg = {{(ADDR_WIDTH - BNDRY_WIDTH) {in_burstwrap_reg[BNDRY_WIDTH - 1]}}, in_burstwrap_reg};
|
||||
new_burst_export = new_burst;
|
||||
end
|
||||
|
||||
reg internal_sclr;
|
||||
generate if (SYNC_RESET == 1) begin : rst_syncronizer
|
||||
always @ (posedge clk) begin
|
||||
internal_sclr <= reset;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
reg [LEN_WIDTH -1 : 0] next_uncompr_remaining_len;
|
||||
always_comb begin
|
||||
|
||||
if (in_sop) begin
|
||||
uncompr_remaining_len = in_len;
|
||||
end
|
||||
else begin
|
||||
uncompr_remaining_len = next_uncompr_remaining_len;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin : proc_compressed_read
|
||||
remaining_len = in_len;
|
||||
if (!new_burst)
|
||||
remaining_len = next_rem_len;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
next_uncompr_out_len = first_len;
|
||||
if (in_sop) begin
|
||||
next_uncompr_out_len = first_len;
|
||||
end
|
||||
else begin
|
||||
if (uncompr_sub_burst)
|
||||
next_uncompr_out_len = next_uncompr_sub_len;
|
||||
else begin
|
||||
if (uncompr_remaining_len < max_out_length)
|
||||
next_uncompr_out_len = uncompr_remaining_len;
|
||||
else
|
||||
next_uncompr_out_len = max_out_length;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
if (new_burst) begin
|
||||
next_out_len = first_len;
|
||||
end
|
||||
else begin
|
||||
next_out_len = max_out_length;
|
||||
if (remaining_len < max_out_length) begin
|
||||
next_out_len = remaining_len;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_read) begin
|
||||
if (new_burst)
|
||||
next_rem_len <= in_len - first_len;
|
||||
else
|
||||
next_rem_len <= next_rem_len - max_out_length;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_write) begin
|
||||
if (in_sop)
|
||||
next_uncompr_remaining_len <= in_len - first_len;
|
||||
else if (!uncompr_sub_burst)
|
||||
next_uncompr_remaining_len <= next_uncompr_remaining_len - max_out_length;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_write) begin
|
||||
next_uncompr_sub_len <= next_uncompr_out_len - 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : async_rst2
|
||||
|
||||
|
||||
always_ff @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
uncompr_sub_burst <= 0;
|
||||
end
|
||||
else if (enable_write) begin
|
||||
uncompr_sub_burst <= (next_uncompr_out_len > 1'b1);
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (internal_sclr) begin
|
||||
uncompr_sub_burst <= 0;
|
||||
end
|
||||
else if (enable_write) begin
|
||||
uncompr_sub_burst <= (next_uncompr_out_len > 1'b1);
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire end_compressed_sub_burst;
|
||||
assign end_compressed_sub_burst = (remaining_len == next_out_len);
|
||||
|
||||
generate
|
||||
if (SYNC_RESET == 0) begin : async_rst3
|
||||
always_ff @(posedge clk, posedge reset) begin
|
||||
if (reset) begin
|
||||
new_burst <= 1;
|
||||
end
|
||||
else if (enable_read) begin
|
||||
new_burst <= end_compressed_sub_burst;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
always_ff @(posedge clk) begin
|
||||
if (internal_sclr) begin
|
||||
new_burst <= 1;
|
||||
end
|
||||
else if (enable_read) begin
|
||||
new_burst <= end_compressed_sub_burst;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_read) begin
|
||||
out_len <= next_out_len;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
generate
|
||||
if (OPTIMIZE_WRITE_BURST) begin : optimized_write_burst_len
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_read) begin
|
||||
uncompr_out_len <= first_len;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
else begin : unoptimized_write_burst_len
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_write) begin
|
||||
uncompr_out_len <= next_uncompr_out_len;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
reg [ADDR_WIDTH - 1 : 0] addr_incr;
|
||||
localparam [ADDR_WIDTH - 1 : 0] ADDR_INCR = MAX_OUT_LEN << LOG2_NUMSYMBOLS;
|
||||
assign addr_incr = ADDR_INCR[ADDR_WIDTH - 1 : 0];
|
||||
|
||||
reg [ADDR_WIDTH - 1 : 0] next_out_addr;
|
||||
reg [ADDR_WIDTH - 1 : 0] incremented_addr;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_read) begin
|
||||
out_addr <= (next_out_addr);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (enable_read) begin
|
||||
incremented_addr <= ((next_out_addr + addr_incr) & extended_burstwrap_reg);
|
||||
if (new_burst) begin
|
||||
incremented_addr <= ((next_out_addr + (first_len << LOG2_NUMSYMBOLS)) & extended_burstwrap);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_comb begin
|
||||
next_out_addr = in_addr;
|
||||
if (!new_burst) begin
|
||||
next_out_addr = in_addr_reg & ~extended_burstwrap_reg | incremented_addr;
|
||||
end
|
||||
end
|
||||
|
||||
function integer log2ceil;
|
||||
input integer val;
|
||||
reg[31:0] i;
|
||||
|
||||
begin
|
||||
i = 1;
|
||||
log2ceil = 0;
|
||||
|
||||
while (i < val) begin
|
||||
log2ceil = log2ceil + 1;
|
||||
i = i[30:0] << 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FgX7fXRetecITTJAqdbkZBsCHzJq/Jytj7t5Txnwxy9ssrydFmy2BTmEsJnplde8gT/5Z8QfaR32L5HbYq69F24RC85ln/Re/7VLNnjYyPPB9rIQmswin58UILlVBEJpTgkjDP9oQbneipXCLBJ1GSj75M00bxvksj2EVvOJOeDH43r6CJRONHpyB6hHXe+8v/iaJp3r2XmmPF28YE05QiespwE43MLpe1lNptdNUdnloyWvFt0sdJ6bjThGMjfbGHUoXhygRKVQR19MFPoxnmthXkr6Y8l0Veh/6SyVy17U/CWUSNz6JN4MtV5p4WdDhZsUMapJkR83sXO0fBW/xBER5ys9rKq5b7n13HHftKdVp8vWaOicRKUriPsvJ9tO1x+mioCb7V4xpxaAgivOia0r9fu3oJMebjs5zwVt3NwNLfBdmhE1DstswGwswOR9sifgdyZeV4AYO9wC+3dvrvBl42cpx14z2210+w673Y0mqDu1bV/h4l5CbYz7xpoqqqQVUYRsiUIM35pZHPyCAKn1D6FE2xrMh4s3y9i19A6a3jNlbiWEsfW2oMH9zsXnLL2vFeVdzs2eQR32hVB7wav2ryqSMMm7Lz2GzBCR0ukesTgCjec0DdSpuNYAfS9A4k2ve5gdL+Tl5uM/kfGg9jy+RMV4YUeUYVSrfzqAdIZUVxncEns1FtcTG8LvaG3fjIY/RdlCy20cE9M2KFgGif7Wl2OpyBy7701q2zhsDWOM+3yyMgoXb26zt4mAw0hWgngkIz2etWf+gzYJgRawD0K"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc/sjLowhmEPaka/N+Hg05w56COKZyYo5XS1VO+sVlmGbTcxy+wc4Z/GTYRUv2sV08J8JX84wWH77aXztOHVMnf8/pOpT4arrSV1XZ3YrmNga/X3dq1vHFCfd4sO+whXMOzKgOnYIxMFHty1BgUaHu8YvD1LqZP3nZkVhSFNE8Ti0zA4bMz2/O9JzEl4jsWO6+UVbl4Zw2u0L3H5UZ/v/9TzGzB9CxyEK4LUkwPQE80hsPVeNWg5zeG1KksCUs7QnKhCudpwcjUIctWjaoqEYa47DfIxs15EdoDoVH2DxECto0Gyd0MMpCrkVg/Yu8Lh5+46RKZAp17+PatyVEk51YnTA2gppXOU4wPQg2KTwleZqP/2433s/o5xGxCpQA04LdhwDHUSRhY+L7RH9KHnD7k/OEt6ImN3aiy4NR+ZL2wG/qO9VvN+m7YiVKeIc5JmFBwHH/iA53mI4qTNxEGG/GUMoefWkPPxNVo4sUZhQ+2nSkX5HpjgzdbYGqpO5HIt5Zo57yplP1V6MeaVuAvnagdIMkJeufK56OifIFT1e8+PbmED1LQL8pjXLTbTlc+89JN6jFpw5PDrYZ1Ke6jbRoygciVTAgq2hxZ85kmBkT8Jp5vaBAkeSiQGBZd38ozukPgln+QZJgGv2YeHHQmUP4F8Px3TcHHwwFY9+0G4uySIBFfFDrD/1r8Yg4CqJe3kxSyGc4WdH5HC4RODk2uZNTanZ9zYlCTLVOFSZqUTyK8ps11cblGHZVgZmv1T5WBFuX1gQTBa0RaRQuw3Fxq+2TAj"
|
||||
`endif
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module compare_eq #(
|
||||
parameter WIDTH=10
|
||||
) (
|
||||
input [WIDTH-1:0] in_a,
|
||||
input [WIDTH-1:0] in_b,
|
||||
output equal
|
||||
);
|
||||
|
||||
assign equal = (in_a==in_b);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "3wrV9vxkV6cm3KZuU0YmrpECz0gO85cpwPAwvoDmqQfm97s5UZmfYguhz8/428PUc52yhrNL2DIcflQpOkDgIHixsN/qQIr1Yl8RrFxWUW9+BWG4mgSfzo8rnvUQWJayS2cUu9k11ZYcmdN3LHF6s1KoNJ9JXlORxyEgsglhkdhkf1ALusfEVuG233HcW8M7RNXR6hb8GxDqWtwlLRj1qCOttHqbLRcgsbfjrMDR1FjQL9exbfXYTp137Dtd6Y0g6L4MgYOzwjRQpR0jP8MXyY0JHzOEOLBvGLeAfT0zJFN5eB54bfkyPWJXaUD9Yt++782v+rIWyQg5F3Q+VN5KWZObQSZSJZjskCikMATWs4odQUY2/UcTZ3iS0cyZ1gXZBv5vGyXsGpo3JMt8UqBRfF1GddwcaSNOLRFHi1adCsXu76Z1F1CAuiXCV+d92LcX5yDP9SbxTbuY8uOetEv1wHnVth16O1avdtiqUj8qtb0rrDaBUiskNDQOGgJrkP3YC2PV5p5Ep5C4udKdywI3ziips38Ds90PuJy67yjR8tG/R6zabBtu54dn1e8SLL326vGTA2sisJaEzjaRfIKsLJnA326qDRFJRXuJyNTM7cWuc6AbVd7frqsYkl08yfw34RPfW1+c+YH4f3PlPLrR0O6uYYvNhwJ9mQUj23tFchjYyASeMky7PNT0BIRTQEikjAtaLzBKpg5fs5fbnOqOERLQBFzbBPh4+FDq/9hu4gCx7eTa7MyIsxZKV5gt/lwT2hZcqDd/Z33loBENj5mAY5TuV7o5T6CQNg04nejD9dHDDPGwYJWtrjyx7Cdd/NXGCkPee8GzhdSawScqvEdT4qSIxEZ5C/Yaco4E3KjR+kltA956dS76He9dUzKofYAjSx8SNrd00sOxpHpDnq0yCOcmq6U2usnwNpYR4/6dZvcbsyarjLzWAiNvHJzbqrGMYbPHq2pU03yyDXkLFcSkzzETYMcG+/Jb0ZL6RUUP88PAn1MYWRVdlTzrc4hYcISV"
|
||||
`endif
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc/3fRCOMC7ZtuwldGcjP9hBCPb9R6+43F29EAlHvwDdqpHad9gRrgZbtD58p8F/OF+8ut1sRHN0JaLes6jT9fDWXGh+sDBJjTJ/wINpNUzZd4yO2sjBvhIzvHEpaEkiI1mpQwY2p8vMDq1AKz9NtqDyosBds+3yyQ9Ge2FyMMd2nipwmNlpHzbXajrP7HO5j3MNItLNjGhneh+raAzpI6UR6bTdS1gJqqfowVP5NrEBLbKzi9cofjXVTIm7/DH8TykZrtjJCFx6cxeQLMinO0Wzk1lKYnh1qrG+xe2dernSLBRz/vUOFZRsCPd1ZdNyf3cIlMvoEnexDh0CAVb7O+BL4jLX6uOvvfB9tIJAtomPasqV2ukeMbh0lU2Lf7yZRbYos47wdYZisJOlszLC0d7D7JZo0oTIgmfxQH6bZkbK2zi8yKFsj3K7CYpJw/M2yynxXojvtryzC/ZUzbWoXE6qfHwPthBVr1wSWCcZcXgt57+hUgWc4QlKbKsHli4ECzQhzT3Vbp8tzKyjz0QkWzhHltMAc1vIVOG0kffl0bIP2oXMIY7Gq545n6rCuP3kSS/Cp7tQZICjS9mnNzXPZdEQYcsoRPbIvdpbR1ZAsYWtC3KV4asbHvzArlFYYy+RDrQRrItYCFfAw/2TNBOB9jHfFcDZfIpRc6d3QR8ajJYuNNyOtzqaI3ikZTSvNYIPV3Tmj2ECBv/vw+Biwolx97gZFduZxNnaX9Pvx+HNxy9h10es47fxSPY98hmAbRCqjku6lF9pZCs8nhYSeiGHNxmG"
|
||||
`endif
|
||||
+1175
File diff suppressed because it is too large
Load Diff
+178
@@ -0,0 +1,178 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
|
||||
parameter
|
||||
USE_FIFO_IP = 0,
|
||||
SYMBOLS_PER_BEAT = 1,
|
||||
BITS_PER_SYMBOL = 8,
|
||||
USE_PACKETS = 0,
|
||||
USE_EMPTY = 0,
|
||||
PIPELINE_READY = 1,
|
||||
SYNC_RESET = 0,
|
||||
CHANNEL_WIDTH = 0,
|
||||
ERROR_WIDTH = 0,
|
||||
|
||||
DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
|
||||
PACKET_WIDTH = 0,
|
||||
EMPTY_WIDTH = 0
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
output in_ready,
|
||||
input in_valid,
|
||||
input [DATA_WIDTH - 1 : 0] in_data,
|
||||
input [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] in_channel,
|
||||
input [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] in_error,
|
||||
input in_startofpacket,
|
||||
input in_endofpacket,
|
||||
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
|
||||
|
||||
input out_ready,
|
||||
output out_valid,
|
||||
output [DATA_WIDTH - 1 : 0] out_data,
|
||||
output [(CHANNEL_WIDTH ? (CHANNEL_WIDTH - 1) : 0) : 0] out_channel,
|
||||
output [(ERROR_WIDTH ? (ERROR_WIDTH - 1) : 0) : 0] out_error,
|
||||
output out_startofpacket,
|
||||
output out_endofpacket,
|
||||
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
|
||||
);
|
||||
localparam
|
||||
PAYLOAD_WIDTH =
|
||||
DATA_WIDTH +
|
||||
PACKET_WIDTH +
|
||||
CHANNEL_WIDTH +
|
||||
EMPTY_WIDTH +
|
||||
ERROR_WIDTH;
|
||||
|
||||
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
|
||||
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
|
||||
|
||||
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
|
||||
generate
|
||||
if (PACKET_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH - 1 :
|
||||
DATA_WIDTH
|
||||
] = {in_startofpacket, in_endofpacket};
|
||||
end
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
] = in_channel;
|
||||
end
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
] = in_empty;
|
||||
end
|
||||
if (ERROR_WIDTH) begin
|
||||
assign in_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
] = in_error;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
localparam NUM_128BIT_SLOTS = (PAYLOAD_WIDTH / 128) + (((PAYLOAD_WIDTH % 128) == 0) ? 0 : 1);
|
||||
localparam LAST_PAYLOAD_W = ((PAYLOAD_WIDTH % 128) == 0) ? 128 : (PAYLOAD_WIDTH % 128);
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < NUM_128BIT_SLOTS; i = i + 1) begin : gen_inst
|
||||
if (i == NUM_128BIT_SLOTS - 1) begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (LAST_PAYLOAD_W),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (in_ready),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i*128)+LAST_PAYLOAD_W-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (out_valid),
|
||||
.out_data (out_payload[(i*128)+LAST_PAYLOAD_W-1:i*128])
|
||||
);
|
||||
end
|
||||
else begin
|
||||
altera_avalon_st_pipeline_base #(
|
||||
.SYMBOLS_PER_BEAT (128),
|
||||
.BITS_PER_SYMBOL (1),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) core (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_payload[(i+1)*128-1:i*128]),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (),
|
||||
.out_data (out_payload[(i+1)*128-1:i*128])
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
|
||||
generate
|
||||
if (PACKET_WIDTH) begin
|
||||
assign {out_startofpacket, out_endofpacket} =
|
||||
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
|
||||
end else begin
|
||||
assign {out_startofpacket, out_endofpacket} = 2'b0;
|
||||
end
|
||||
|
||||
if (CHANNEL_WIDTH) begin
|
||||
assign out_channel = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH
|
||||
];
|
||||
end else begin
|
||||
assign out_channel = 1'b0;
|
||||
end
|
||||
if (EMPTY_WIDTH) begin
|
||||
assign out_empty = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH
|
||||
];
|
||||
end else begin
|
||||
assign out_empty = 1'b0;
|
||||
end
|
||||
if (ERROR_WIDTH) begin
|
||||
assign out_error = out_payload[
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH + ERROR_WIDTH - 1 :
|
||||
DATA_WIDTH + PACKET_WIDTH + CHANNEL_WIDTH + EMPTY_WIDTH
|
||||
];
|
||||
end else begin
|
||||
assign out_error = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc95nYGFLE9tra4xsr/oHxBuJjmaod1/QD62UVNlbk6m9k/gj6tPg4xjLITr2R1q/AkgSS6aiOGaSwEWZyFSz5EDSZTcsU1ychL0V9/gOn94pa9Q8eRDvsB/Nlx1Gva+gQoqtQ+DIOxITbrj75z9DzJH3OoVFmLqYU9PyojSktvNgk5Pwv2OR6/lfStqVFf8UCXVRsVgOq994VZREsAwcGLX/hJZWJvYA+TZuv9r+Z9bgg/UTC5KNSBZatmRNTh+ffoOYtbwVyR9TfKyMUN7BTEs9fOGaV/FdNTowPd5Nu51Snee51AWxBjK9Md6HcS58Z0oZ6Zs+Eb52hKaRo0sROLPbR8CYcvrIlJyWo2bxwndT2q3Df5bkZTgYz5CIsJV7hPZlK7X3dQXtmgqexLWIqz1S5p9ABI7acfQeUtCylYPDvv6HDOZRgyDeQESyql7fubsp8jWuI8z+hZ+cFQ9fo797hjF3E4R78g68voWC1H2R/ChiYE0wGdNIo7tfmVd+oP6/fXfaAx1P8QiqcHkKLrqOsxbVWAGXsLqUpTnM1L9O0c3mRdIzgs/CRjWVvwUEMAvQMf1Gd1rnd77BVWKIyvtF5YZX3GSG7VLcAj8NS7BHobEe6a5RgDgL3kFU/uzaA7TESxv7I3qHmtw6dTQw5pVtSkh2FRhLheN1L/xq6PiNrg8KPlu0xWvnZ5I4Kw6c+XidLRjeT9Jmyf4H4Bhv2AeA3qRA1F737+SdFnyWJFdD36LOWjl+aBAiG70Rx656fEjhmwUR1bwHzTrJ4ub3Sv5"
|
||||
`endif
|
||||
+1018
File diff suppressed because it is too large
Load Diff
+1406
File diff suppressed because it is too large
Load Diff
+1405
File diff suppressed because it is too large
Load Diff
+114
@@ -0,0 +1,114 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_o34766q #(
|
||||
parameter SYMBOLS_PER_BEAT = 1,
|
||||
parameter BITS_PER_SYMBOL = 125,
|
||||
parameter FIFO_DEPTH = 1,
|
||||
parameter CHANNEL_WIDTH = 0,
|
||||
parameter ERROR_WIDTH = 0,
|
||||
parameter USE_PACKETS = 0,
|
||||
parameter USE_FILL_LEVEL = 0,
|
||||
parameter EMPTY_LATENCY = 1,
|
||||
parameter USE_MEMORY_BLOCKS = 0,
|
||||
parameter USE_STORE_FORWARD = 0,
|
||||
parameter USE_ALMOST_FULL_IF = 0,
|
||||
parameter USE_ALMOST_EMPTY_IF = 0,
|
||||
parameter EMPTY_WIDTH = 1,
|
||||
parameter SYNC_RESET = 0
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire [124:0] in_data,
|
||||
input wire in_valid,
|
||||
output wire in_ready,
|
||||
output wire [124:0] out_data,
|
||||
output wire out_valid,
|
||||
input wire out_ready
|
||||
);
|
||||
|
||||
generate
|
||||
if (EMPTY_WIDTH != 1)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
empty_width_check ( .error(1'b1) );
|
||||
end
|
||||
if (SYNC_RESET != 0)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
sync_reset_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
ed_synth_dut_altera_avalon_sc_fifo_1931_fzgstwy #(
|
||||
.SYMBOLS_PER_BEAT (SYMBOLS_PER_BEAT),
|
||||
.BITS_PER_SYMBOL (BITS_PER_SYMBOL),
|
||||
.FIFO_DEPTH (FIFO_DEPTH),
|
||||
.CHANNEL_WIDTH (CHANNEL_WIDTH),
|
||||
.ERROR_WIDTH (ERROR_WIDTH),
|
||||
.USE_PACKETS (USE_PACKETS),
|
||||
.USE_FILL_LEVEL (USE_FILL_LEVEL),
|
||||
.EMPTY_LATENCY (EMPTY_LATENCY),
|
||||
.USE_MEMORY_BLOCKS (USE_MEMORY_BLOCKS),
|
||||
.USE_STORE_FORWARD (USE_STORE_FORWARD),
|
||||
.USE_ALMOST_FULL_IF (USE_ALMOST_FULL_IF),
|
||||
.USE_ALMOST_EMPTY_IF (USE_ALMOST_EMPTY_IF),
|
||||
.EMPTY_WIDTH (1),
|
||||
.SYNC_RESET (0)
|
||||
) my_altera_avalon_sc_fifo_wr (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_data (in_data),
|
||||
.in_valid (in_valid),
|
||||
.in_ready (in_ready),
|
||||
.out_data (out_data),
|
||||
.out_valid (out_valid),
|
||||
.out_ready (out_ready),
|
||||
.csr_address (2'b00),
|
||||
.csr_read (1'b0),
|
||||
.csr_write (1'b0),
|
||||
.csr_readdata (),
|
||||
.csr_writedata (32'b00000000000000000000000000000000),
|
||||
.almost_full_data (),
|
||||
.almost_empty_data (),
|
||||
.in_startofpacket (1'b0),
|
||||
.in_endofpacket (1'b0),
|
||||
.out_startofpacket (),
|
||||
.out_endofpacket (),
|
||||
.in_empty (1'b0),
|
||||
.out_empty (),
|
||||
.in_error (1'b0),
|
||||
.out_error (),
|
||||
.in_channel (1'b0),
|
||||
.out_channel ()
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc97oYl99JBZAfZg/HJ1EtkD2rctLbHBJvelOV9G2sRcOztS6I3UQjP45gG7UVFwWY9NiGEXpqa7iWnIKgWXbNOw7QLlpmnWfyrKVGjSytO7aCwE78pSupnpgbUbKfDTTr5E4Oqm77jdWX+9hEtlUA5xBewb2djlf0IKlrKriKsx3xMy/FmQjVRbQ/ric/R70e+VqkImU4kUuC8hMdhLBH82T7e+N22koRcCr2wTm8O6dfcGyYRn1wKizdu3eCgEQSefO/98cTeQx9qvY/YdyHTHlvJ/WI8IYjl4BOXSyVz6K6/5EfvYMDjyRyZHR/zGbyihCyYE9w+r+wuEwISgJyDKOIrr+T8tFhzlxZpslD/4hWXk9uuBtF0tB4Z7agW7XGCM/TLPtnod2Rbw/WJEOlu5KGjs33mZiBqrlmPEY31cyefIkMLgj9zaKYDLnjEd33Dfa8zCWHvnON/Pl9QL5NAu4sDZEc3NjadfhBoIJI6eVes512cmV+8iglItAgX2i9bSgBx6t3GoYQq4VQoYzWjOhzRoHtRfqc9ChiP+160e3sPNJkbfW++xCu+aXOAW3eMVbHOOCo7Pad6Xr7trl4JYNa8EiALTGdctoatq6dSwEyvMaa46kOsjuMsC6ED2bCpgS0Yu2y7lQ2TtFlRABcJ1e78NvfOVyph9dRSPCYEvRY+x8g/4IDl7Oel5qQMhMNIors98lwPDpAOk5ss36okH67Nrx/3iBH+UEu/uW8fGrYvJeW/VSTigJLB3/cO5PkT03kdZq7KeprJLAvgYAAhi"
|
||||
`endif
|
||||
+114
@@ -0,0 +1,114 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_ysgnmwa #(
|
||||
parameter SYMBOLS_PER_BEAT = 1,
|
||||
parameter BITS_PER_SYMBOL = 189,
|
||||
parameter FIFO_DEPTH = 1,
|
||||
parameter CHANNEL_WIDTH = 0,
|
||||
parameter ERROR_WIDTH = 0,
|
||||
parameter USE_PACKETS = 0,
|
||||
parameter USE_FILL_LEVEL = 0,
|
||||
parameter EMPTY_LATENCY = 1,
|
||||
parameter USE_MEMORY_BLOCKS = 0,
|
||||
parameter USE_STORE_FORWARD = 0,
|
||||
parameter USE_ALMOST_FULL_IF = 0,
|
||||
parameter USE_ALMOST_EMPTY_IF = 0,
|
||||
parameter EMPTY_WIDTH = 1,
|
||||
parameter SYNC_RESET = 0
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire [188:0] in_data,
|
||||
input wire in_valid,
|
||||
output wire in_ready,
|
||||
output wire [188:0] out_data,
|
||||
output wire out_valid,
|
||||
input wire out_ready
|
||||
);
|
||||
|
||||
generate
|
||||
if (EMPTY_WIDTH != 1)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
empty_width_check ( .error(1'b1) );
|
||||
end
|
||||
if (SYNC_RESET != 0)
|
||||
begin
|
||||
// synthesis translate_off
|
||||
initial begin
|
||||
$display("Generated module instantiated with wrong parameters");
|
||||
$stop;
|
||||
end
|
||||
// synthesis translate_on
|
||||
instantiated_with_wrong_parameters_error_see_comment_above
|
||||
sync_reset_check ( .error(1'b1) );
|
||||
end
|
||||
endgenerate
|
||||
|
||||
ed_synth_dut_altera_avalon_sc_fifo_1931_fzgstwy #(
|
||||
.SYMBOLS_PER_BEAT (SYMBOLS_PER_BEAT),
|
||||
.BITS_PER_SYMBOL (BITS_PER_SYMBOL),
|
||||
.FIFO_DEPTH (FIFO_DEPTH),
|
||||
.CHANNEL_WIDTH (CHANNEL_WIDTH),
|
||||
.ERROR_WIDTH (ERROR_WIDTH),
|
||||
.USE_PACKETS (USE_PACKETS),
|
||||
.USE_FILL_LEVEL (USE_FILL_LEVEL),
|
||||
.EMPTY_LATENCY (EMPTY_LATENCY),
|
||||
.USE_MEMORY_BLOCKS (USE_MEMORY_BLOCKS),
|
||||
.USE_STORE_FORWARD (USE_STORE_FORWARD),
|
||||
.USE_ALMOST_FULL_IF (USE_ALMOST_FULL_IF),
|
||||
.USE_ALMOST_EMPTY_IF (USE_ALMOST_EMPTY_IF),
|
||||
.EMPTY_WIDTH (1),
|
||||
.SYNC_RESET (0)
|
||||
) my_altera_avalon_sc_fifo_wr (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_data (in_data),
|
||||
.in_valid (in_valid),
|
||||
.in_ready (in_ready),
|
||||
.out_data (out_data),
|
||||
.out_valid (out_valid),
|
||||
.out_ready (out_ready),
|
||||
.csr_address (2'b00),
|
||||
.csr_read (1'b0),
|
||||
.csr_write (1'b0),
|
||||
.csr_readdata (),
|
||||
.csr_writedata (32'b00000000000000000000000000000000),
|
||||
.almost_full_data (),
|
||||
.almost_empty_data (),
|
||||
.in_startofpacket (1'b0),
|
||||
.in_endofpacket (1'b0),
|
||||
.out_startofpacket (),
|
||||
.out_endofpacket (),
|
||||
.in_empty (1'b0),
|
||||
.out_empty (),
|
||||
.in_error (1'b0),
|
||||
.out_error (),
|
||||
.in_channel (1'b0),
|
||||
.out_channel ()
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc+6HT15wuJhp2fn4JA24eaiAhTgEr1778yS1TM5bWSPvW9+gz9SsM2zpTvo3X1VJebG/kiXBMNFPlmc2hBN0mTfY71a8Ur1cRhgz/HalsADvvGtFuH/iXr2xoJ013YRnE++NeOh83z+bcK33thpdqd3PKIt+/YKL8ZIrxNV8a1+ZtGm3vTIxlDdvZYNtqGkY+9qW+1j0tdyHfbH0NEs/efdYqek7/JsE9igfWv9JLcQmhPcUFTszfqb6NBBQve7JzuOy7YJuqEx378XAYJoJlF72b9BCLMOeYAjC+ScF8BkZNQ/g2E3Ey4aZeZirw6vS0RWRmpVo/ZdSy6qtA1ReGFx2HrbpZO+D+dcF209wQAti4CfcBdUofvN/X/JGJaCUKf34nCD8cVGu1ugWVm8iFP4l6YpCDwqrif6SOye0AT8jXXLXNwc4lOvcAeCG+JojQy87jCRw4ZQwKyPAxXDIcAuZ5IesORKk00uiepEdlkDX1iKG9ooYZSZ5R/6E03sen6gqW5Uld0ojRzVrtjtkgJu59RExW0zHOjh1KGH5xWMG7Qw48USV4UX4z09cRyXw7CQqjLXlJTNZqwlTpOD/FKug3SK7aQbUcjjMnGvYeRbhGGLWy056sd+HhvCJ5F2mmdbj2g0DDURb+CDVSZq0zzbC8ig3aBLzG2mJ+Qy1TYSjDGgxKcgFlqw2nwO8YW1RZeKK8gupgq+mBCTh2KrG/Sb0n31NzsGbtTqBytF66lzb4geo+5DbRUAmBIoTFE4AdBZagX+t9iPScbkvDf/tNXf"
|
||||
`endif
|
||||
+74
@@ -0,0 +1,74 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_alj3kza #(
|
||||
parameter SYMBOLS_PER_BEAT = 1,
|
||||
parameter BITS_PER_SYMBOL = 37,
|
||||
parameter USE_PACKETS = 0,
|
||||
parameter USE_EMPTY = 0,
|
||||
parameter EMPTY_WIDTH = 0,
|
||||
parameter CHANNEL_WIDTH = 0,
|
||||
parameter PACKET_WIDTH = 0,
|
||||
parameter ERROR_WIDTH = 0,
|
||||
parameter PIPELINE_READY = 0,
|
||||
parameter SYNC_RESET = 0
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
output wire in_ready,
|
||||
input wire in_valid,
|
||||
input wire [36:0] in_data,
|
||||
input wire out_ready,
|
||||
output wire out_valid,
|
||||
output wire [36:0] out_data
|
||||
);
|
||||
|
||||
ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
|
||||
.SYMBOLS_PER_BEAT (SYMBOLS_PER_BEAT),
|
||||
.BITS_PER_SYMBOL (BITS_PER_SYMBOL),
|
||||
.USE_PACKETS (USE_PACKETS),
|
||||
.USE_EMPTY (USE_EMPTY),
|
||||
.EMPTY_WIDTH (EMPTY_WIDTH),
|
||||
.CHANNEL_WIDTH (CHANNEL_WIDTH),
|
||||
.PACKET_WIDTH (PACKET_WIDTH),
|
||||
.ERROR_WIDTH (ERROR_WIDTH),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) my_altera_avalon_st_pipeline_stage_rd (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (in_ready),
|
||||
.in_valid (in_valid),
|
||||
.in_data (in_data),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (out_valid),
|
||||
.out_data (out_data),
|
||||
.in_startofpacket (1'b0),
|
||||
.in_endofpacket (1'b0),
|
||||
.out_startofpacket (),
|
||||
.out_endofpacket (),
|
||||
.in_empty (1'b0),
|
||||
.out_empty (),
|
||||
.out_error (),
|
||||
.in_error (1'b0),
|
||||
.out_channel (),
|
||||
.in_channel (1'b0)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9H49BIrSv2YORai8UBCpP5fj4SY1FQcJ17ubBAdkQ7pbMSaMpiTbjhcofGMJoXO+xSXPbiZRfzGkl9DxhbMF/KfSue7tn0Rsf6AjBKj2PN24j9R+qCmnvGhWKdRl+w2VR5pXabNctYmWeDd2vi30D0HZCe6Jtp88dFTdaAby1EBjmUUtesOcYmWMn8LwRngCOiSHlD9CBfvYJUTAG6AX6okxWMOovMK3yk6HGwXGC+LMZDoIHUwzYPWK0h6fJSBpC13DCbAKgpHmtC6S1wFhIffnE+NsMD05bmFa+o2/469DT2zbdmRnnSTJ/vzzxiEIth/+8Pj/N3V0tzxBKhubc3E6c1WurF+M3P6oGwXd4DpkPNLs7buga5dm27d6hL6iKsb2/pWaDtalLPqCDEK/AoVQ2eBRvGEFn6ZMrrBT1LZt8t3yBlZzsEOnPjm+zG4Gt40L34Fkp/G4NidHs/fdEhZgCO7pw6AfKsaQb7LYE8UV9muRy/kq+Q7A3dHmWVcpvSfLzN4OIFPjefOAkJwO0peauH/481BBazhDRepshPNXvBbXzoyR8aqlN6r6UxPmhsK7VdMY0+hw2ZcCaerVaW/dPmF5Qx3U0Yr8Swea6DFHazbHRqgpSJoSCUmJypG5Kol0yHgVcf+9TwINFfZXJg7Wz4G6fo/7YFbZW9PPrGeooKmct1n4+SEc+FuIJx8CLvf7i28aOCvA7SFcDNZb3XX5DK9UApNy5VbkrwbXrAu8SPZ4hTsZKX7dopuBUGio6xW7JyRXqrZPyciv2OB8dh"
|
||||
`endif
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
// (C) 2001-2026 Altera Corporation. All rights reserved.
|
||||
// Your use of Altera Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Altera Program License Subscription
|
||||
// Agreement, Altera IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Altera and sold by
|
||||
// Altera or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_cgpn6xq #(
|
||||
parameter SYMBOLS_PER_BEAT = 1,
|
||||
parameter BITS_PER_SYMBOL = 188,
|
||||
parameter USE_PACKETS = 1,
|
||||
parameter USE_EMPTY = 0,
|
||||
parameter EMPTY_WIDTH = 0,
|
||||
parameter CHANNEL_WIDTH = 0,
|
||||
parameter PACKET_WIDTH = 2,
|
||||
parameter ERROR_WIDTH = 0,
|
||||
parameter PIPELINE_READY = 1,
|
||||
parameter SYNC_RESET = 0
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
output wire in_ready,
|
||||
input wire in_valid,
|
||||
input wire in_startofpacket,
|
||||
input wire in_endofpacket,
|
||||
input wire [187:0] in_data,
|
||||
input wire out_ready,
|
||||
output wire out_valid,
|
||||
output wire out_startofpacket,
|
||||
output wire out_endofpacket,
|
||||
output wire [187:0] out_data
|
||||
);
|
||||
|
||||
ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
|
||||
.SYMBOLS_PER_BEAT (SYMBOLS_PER_BEAT),
|
||||
.BITS_PER_SYMBOL (BITS_PER_SYMBOL),
|
||||
.USE_PACKETS (USE_PACKETS),
|
||||
.USE_EMPTY (USE_EMPTY),
|
||||
.EMPTY_WIDTH (EMPTY_WIDTH),
|
||||
.CHANNEL_WIDTH (CHANNEL_WIDTH),
|
||||
.PACKET_WIDTH (PACKET_WIDTH),
|
||||
.ERROR_WIDTH (ERROR_WIDTH),
|
||||
.PIPELINE_READY (PIPELINE_READY),
|
||||
.SYNC_RESET (SYNC_RESET)
|
||||
) my_altera_avalon_st_pipeline_stage_rp (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_ready (in_ready),
|
||||
.in_valid (in_valid),
|
||||
.in_startofpacket (in_startofpacket),
|
||||
.in_endofpacket (in_endofpacket),
|
||||
.in_data (in_data),
|
||||
.out_ready (out_ready),
|
||||
.out_valid (out_valid),
|
||||
.out_startofpacket (out_startofpacket),
|
||||
.out_endofpacket (out_endofpacket),
|
||||
.out_data (out_data),
|
||||
.in_empty (1'b0),
|
||||
.out_empty (),
|
||||
.out_error (),
|
||||
.in_error (1'b0),
|
||||
.out_channel (),
|
||||
.in_channel (1'b0)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`ifdef QUESTA_INTEL_OEM
|
||||
`pragma questa_oem_00 "teYVLGZNsNaiPcWqMo30NLVhg9IMsUmKVYNVZA1g6YoMxCd3saFbjdspgxSuUGwJbR9kWeEFKaMzYwRfr2xaLMzQysyjOgYwIl9lo4FRttf7J9onFRZ+cQrE2NDuXtdJIIGO+/dKUOmyPPPV1hqZy6acKa90MKRpH3sijyxlOYLyV6T4kJRgD7++iamENcxEYRZnFpkQV+bUVDpbgF3G26MsZv5WeY2kTm/9hl8Mtc9HK5TT5s6Ih2WsyxV0SE4EkPuCNGvhgpLRwyZeCZPv6/b2uemhj1RnlqUydlwWhMhjSeDsTD68SgVrOTl6je4gDjwqKLMKmGqu27TJQhFNaWKaQ9mC5Eg8tzCvig+3G8wqPkD9t3iixDIA9ef2U9rd1Wafap1T7lAdyq+Xj7abkNsyr6rJLWw7dcGBB6WyKNCk2wupbx6Rf5Y5kxZT0r8EwuhX3SniewnzKfmVDGhlf+h94ajhQln5wHOnI2zH8An7HM4AfgAMt6eLnSUHI0Sl7A9HOJydd0jGeKf82L9so7yeU42iaVOSdJQzMdfAwkVp5EcijEQcRzTRtxxGEWxMqBTLWige6Xd39nOd69AxdwXc6RVwjo4uHtztejMtYMndfCUyPJos3ObkDzOmsqEI1ocqncA2Y3Q06dirxkMAYmuUlhLIrBnIKSCIzWLjuIMkxqfANKLfKIVFNUhR5eGBSYfCc6/6cXyA754EeIUVK5ez6A4B/JB62abeTcL/ofA7+5jGMcKxy8dA1Gc9Q9PhYiT1I0sQM5A6W3iANyV9Bu8t1sl5V9Q6cdew6O0FKFR8MKqPyTh/wFqfdB7uCFifG2iflzGI7PmPODAFKAgMX3VzzXg61Uw9FB+bqRvj6y7hxky21BI4j36AOOP4STH4arMmsEHMl8rRPtI5ZFleEVObNKXxGG5ECdfIhPiqTn0TKL+pZir7XphFf/9w7NvZbCr+ylHdkNvm3twxvthJQGbYhwMkPCTCoaR8qcx6GYmyT7wNrJkFxqa7Xy80q72+"
|
||||
`endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user