Ch441: one-entry fully-registered W buffer, Z-RMW master -> wr_arb s2 [READY FOR REVIEW]

Cuts the lone remaining EMIF setup fail (-0.016 ns, -0.259 skew): the combinational
EMIF gen_p2c_ff -> wr_arb s2_wready -> gs_lpddr_z_rmw next-state (st, endpoint
labelled S_FILL_R via the shared encoded state register).

New gs_axi_w_regbuf: fully-registered one-entry W buffer (Option B per Codex).
- u_wready = !full ONLY (registered occupancy) -> EMIF WREADY never reaches the Z
  FSM combinationally. NOT a fall-through skid (no !full-OR-d_wready term).
- Buffers WDATA/WSTRB/WLAST; downstream held stable until accepted; exactly-once.
- AW/B untouched; arbiter bready_q unchanged (still arms on real EMIF W handshake).
- z_rmw may enter B-wait once the beat is buffered -- safe: EMIF cannot return B
  until the buffered beat reaches it. Single-beat writes -> the 1-beat/2-cycle
  buffer rate is far above the Z write rate (no new FIFO pressure).

Wired in zc_emit between u_z W output (zi_*) and the z_w* ports. New file in sim
Makefile RTL_SRCS + synth QSF (both). Focused tb_gs_axi_w_regbuf: exactly-once/order/
payload scoreboard + no-combinational-bypass check (u_wready===!full incl. full &&
d_wready) + downstream-stable check; standalone target + in make run. Texture-cache
+0.016 paths NOT touched. No simulations or Quartus run.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

rtl/gif_gs/gs_lpddr_zc_emit.sv

@@ -150,6 +150,11 @@ module gs_lpddr_zc_emit #(
     // ---------------- Z RMW (axi_clk) ----------------
     logic        z_fvalid, z_fready, z_pvalid, z_pready, z_ppass, z_sflush, z_drained;
     logic [11:0] z_px, z_py; logic [15:0] z_pzq;
+    // Ch441: the Z RMW master's W output goes into a one-entry fully-registered W
+    // buffer (gs_axi_w_regbuf u_z_wbuf, below); the BUFFER drives the zc_emit z_w*
+    // ports (write arbiter s2). This cuts the combinational EMIF WREADY -> z_rmw
+    // FSM path. AW and B pass straight through (z_awaddr.../z_bvalid... unchanged).
+    logic [255:0] zi_wdata; logic [31:0] zi_wstrb; logic zi_wlast, zi_wvalid, zi_wready;
     gs_lpddr_z_rmw #(.ZBASE(ZBASE), .FB_PXW(FB_PXW), .FB_H(FB_H), .Z_CLEAR(Z_CLEAR)) u_z (
         .clk(axi_clk), .rst_n(axi_rst_n), .enable(enable), .clear_start(clear_start), .clear_done(clear_done),
         .scene_flush(z_sflush), .z_drained(z_drained),
@@ -159,10 +164,19 @@ module gs_lpddr_zc_emit #(
         .araddr(z_araddr), .arlen(z_arlen), .arsize(z_arsize), .arburst(z_arburst), .arvalid(z_arvalid), .arready(z_arready),
         .rdata(z_rdata), .rresp(z_rresp), .rlast(z_rlast), .rvalid(z_rvalid), .rready(z_rready),
         .awaddr(z_awaddr), .awlen(z_awlen), .awsize(z_awsize), .awburst(z_awburst), .awvalid(z_awvalid), .awready(z_awready),
-        .wdata(z_wdata), .wstrb(z_wstrb), .wlast(z_wlast), .wvalid(z_wvalid), .wready(z_wready),
+        .wdata(zi_wdata), .wstrb(zi_wstrb), .wlast(zi_wlast), .wvalid(zi_wvalid), .wready(zi_wready),
         .bvalid(z_bvalid), .bready(z_bready), .bresp(z_bresp),
         .beats_read(z_beats_read), .beats_written(z_beats_written), .bresp_err(bresp_err), .idle(z_idle)
     );
+    // Ch441: one-entry fully-registered W-channel buffer between the Z RMW master
+    // (u_z) and the write arbiter s2 (via the z_w* ports). Breaks the combinational
+    // EMIF WREADY -> z_rmw FSM path. AW/B untouched; the arbiter's bready_q still
+    // arms on the real EMIF m_wvalid && m_wready && m_wlast (buffer is upstream).
+    gs_axi_w_regbuf #(.WDATA_W(256), .WSTRB_W(32)) u_z_wbuf (
+        .clk(axi_clk), .rst_n(axi_rst_n),
+        .u_wdata(zi_wdata), .u_wstrb(zi_wstrb), .u_wlast(zi_wlast), .u_wvalid(zi_wvalid), .u_wready(zi_wready),
+        .d_wdata(z_wdata),  .d_wstrb(z_wstrb),  .d_wlast(z_wlast),  .d_wvalid(z_wvalid),  .d_wready(z_wready)
+    );
     // A fragment carries ztest: when ztest=0 it must ALWAYS pass. Feed the RMW a zmsk so it never writes Z for a
     // non-Z fragment, and force its zq to max so GEQUAL always passes. (All scheduler draws are ztest=1.)
     // (Handled at feed below via the always-pass override on the pass decision.)