Ch440: gs_async_fifo QUAD_WIDTH4_READ (2 depth x 4 width) for Z-req FIFO [READY FOR REVIEW]

Candidate 2 from the accepted structural proposal. Adds a QUAD_WIDTH4_READ
generate branch to gs_async_fifo: like QUADRANT_READ (2 depth x 2 width) but
splits the payload into FOUR width banks, so each preserved read-address launch
register drives ~half the M20K load (targets the 310MHz raddr_hi1_q->mem_hi1
setup family, WNS -0.103). Keeps QUADRANT_READ's proven 2:1 depth OUTPUT selector
unchanged (no new/deeper mux, per the doc's warning). Depth (8192), one-cycle
read latency, ordering, CDC, capacity, and interface are identical.

zc_emit u_req switched QUADRANT_READ->QUAD_WIDTH4_READ. New default-off param
leaves the other two gs_async_fifo instances byte-identical. TB gains a
TEST_QUAD_WIDTH4 variant + standalone Makefile target tb_gs_async_fifo_quad_width4.

NO simulations or Quartus run (per authorization). Awaiting review before any sim.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

sim/tb/gif_gs/tb_gs_async_fifo.sv

@@ -11,7 +11,8 @@
 module tb_gs_async_fifo #(
     parameter bit TEST_BANKED = 1'b0,
     parameter bit TEST_QUADRANT = 1'b0,
-    parameter bit TEST_REGISTERED = TEST_BANKED || TEST_QUADRANT
+    parameter bit TEST_QUAD_WIDTH4 = 1'b0,   // Ch440: 2 depth x 4 width banks
+    parameter bit TEST_REGISTERED = TEST_BANKED || TEST_QUADRANT || TEST_QUAD_WIDTH4
 );
     localparam int WIDTH = 32;
     localparam int DEPTH = 8;
@@ -31,7 +32,7 @@ module tb_gs_async_fifo #(
 
     gs_async_fifo #(.WIDTH(WIDTH), .DEPTH(DEPTH),
                     .REGISTERED_READ(TEST_REGISTERED), .BANKED_READ(TEST_BANKED),
-                    .QUADRANT_READ(TEST_QUADRANT)) dut (
+                    .QUADRANT_READ(TEST_QUADRANT), .QUAD_WIDTH4_READ(TEST_QUAD_WIDTH4)) dut (
         .wclk(wclk), .wrst_n(wrst_n), .wr(wr), .wdata(wdata), .wfull(wfull),
         .rclk(rclk), .rrst_n(rrst_n), .rd(dut_rd), .rdata(rdata), .rempty(rempty)
     );