Ch440: gs_async_fifo QUAD_WIDTH4_READ (2 depth x 4 width) for Z-req FIFO [READY FOR REVIEW]

Candidate 2 from the accepted structural proposal. Adds a QUAD_WIDTH4_READ
generate branch to gs_async_fifo: like QUADRANT_READ (2 depth x 2 width) but
splits the payload into FOUR width banks, so each preserved read-address launch
register drives ~half the M20K load (targets the 310MHz raddr_hi1_q->mem_hi1
setup family, WNS -0.103). Keeps QUADRANT_READ's proven 2:1 depth OUTPUT selector
unchanged (no new/deeper mux, per the doc's warning). Depth (8192), one-cycle
read latency, ordering, CDC, capacity, and interface are identical.

zc_emit u_req switched QUADRANT_READ->QUAD_WIDTH4_READ. New default-off param
leaves the other two gs_async_fifo instances byte-identical. TB gains a
TEST_QUAD_WIDTH4 variant + standalone Makefile target tb_gs_async_fifo_quad_width4.

NO simulations or Quartus run (per authorization). Awaiting review before any sim.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

sim/Makefile

@@ -1103,6 +1103,16 @@ tb_gs_async_fifo_quadrant: dirs
 	@echo "=== run tb_gs_async_fifo_quadrant ==="
 	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_async_fifo_quadrant.vvp
 
+tb_gs_async_fifo_quad_width4: dirs
+	@echo "=== build tb_gs_async_fifo_quad_width4 ==="
+	$(IVERILOG) -g2012 -Wall \
+	    -P tb_gs_async_fifo.TEST_QUAD_WIDTH4=1 \
+	    -o $(BUILD_DIR)/tb_gs_async_fifo_quad_width4.vvp \
+	    -s tb_gs_async_fifo \
+	    $(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_async_fifo.sv
+	@echo "=== run tb_gs_async_fifo_quad_width4 ==="
+	@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_async_fifo_quad_width4.vvp
+
 tb_gs_async_fifo_registered: dirs
 	@echo "=== build tb_gs_async_fifo_registered ==="
 	$(IVERILOG) $(IVERILOG_FLGS) \