Ch440: gs_async_fifo QUAD_WIDTH4_READ (2 depth x 4 width) for Z-req FIFO [READY FOR REVIEW]

Candidate 2 from the accepted structural proposal. Adds a QUAD_WIDTH4_READ
generate branch to gs_async_fifo: like QUADRANT_READ (2 depth x 2 width) but
splits the payload into FOUR width banks, so each preserved read-address launch
register drives ~half the M20K load (targets the 310MHz raddr_hi1_q->mem_hi1
setup family, WNS -0.103). Keeps QUADRANT_READ's proven 2:1 depth OUTPUT selector
unchanged (no new/deeper mux, per the doc's warning). Depth (8192), one-cycle
read latency, ordering, CDC, capacity, and interface are identical.

zc_emit u_req switched QUADRANT_READ->QUAD_WIDTH4_READ. New default-off param
leaves the other two gs_async_fifo instances byte-identical. TB gains a
TEST_QUAD_WIDTH4 variant + standalone Makefile target tb_gs_async_fifo_quad_width4.

NO simulations or Quartus run (per authorization). Awaiting review before any sim.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

rtl/gif_gs/gs_lpddr_zc_emit.sv

@@ -99,7 +99,11 @@ module gs_lpddr_zc_emit #(
     // Split that fixed capacity by both depth and width instead: each physical
     // address copy drives one quarter of the original deep/wide RAM tree.
     gs_async_fifo #(.WIDTH(PW), .DEPTH(REQ_DEPTH), .REGISTERED_READ(1'b1),
-                    .QUADRANT_READ(1'b1)) u_req (
+                    // Ch440: 2 depth x 4 width banks (was QUADRANT_READ = 2 depth x
+                    // 2 width) -> halves each read-address register's M20K load to
+                    // shorten the 310 MHz raddr->mem address routing, keeping the
+                    // proven 2:1 depth output selector, 8192 capacity, and latency.
+                    .QUAD_WIDTH4_READ(1'b1)) u_req (
         .wclk(gs_clk), .wrst_n(gs_rst_n), .wr(g_valid && g_ready), .wdata(req_wdata), .wfull(req_wfull),
         .rclk(axi_clk), .rrst_n(axi_rst_n), .rd(req_rd), .rdata(req_rdata), .rempty(req_rempty)
     );