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QSF: revert to AGGRESSIVE AREA + surgical MAX_FANOUT on Z-req raddr (close EMIF, keep design clk)

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Fit data: AGGRESSIVE AREA gives design clk +0.631 / EMIF -0.103; global BALANCED
flipped it to EMIF +0.084 / design clk -6.119 (vert_count->texcache swung 6.7ns).
AGGRESSIVE AREA is far closer to closing, so keep it and fix the one 310MHz EMIF
miss surgically: MAX_FANOUT 3 on u_zc_emit|u_req|raddr_hi1_q forces the register
duplication Quartus asked for (TMC-20551) without the global placement disruption.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-07-21 04:36:42 -04:00
parent b29fb17a11
commit 3d27095c2b
1 changed files with 10 additions and 7 deletions
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synth/de25_nano/top_psmct32_raster_demo/de25_nano_psmct32_raster_demo_top.qsf
+10 -7
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@@ -984,13 +984,16 @@ set_global_assignment -name HPS_INITIALIZATION "HPS FIRST"
# AUTO_RESOURCE_SHARING=OFF from fresh synthesis through route and produced an # AUTO_RESOURCE_SHARING=OFF from fresh synthesis through route and produced an
# identical netlist, resource count, placement, and timing path; sharing was # identical netlist, resource count, placement, and timing path; sharing was
# therefore not the source of the tap-to-texture-cache STA arc. # therefore not the source of the tap-to-texture-cache STA arc.
# Ch415: was "AGGRESSIVE AREA" (a leftover from the pre-useg-strip LAB-overflow era). That mode # AGGRESSIVE AREA keeps the long texture-address combinational paths (e.g. vert_count -> u_texcache RAM)
# suppresses register duplication, which left the 8K Z-req FIFO's read-address register (u_zc_emit| # placed compactly enough to meet the 25 MHz design clock (+0.631 ns). A global switch to BALANCED closed
# u_req|raddr_hi1_q) fanning out to 6 spread M20K blocks and failing 310 MHz EMIF setup by ~103 ps # the EMIF path but blew that design-clock path to -6.119 ns (a 6.7 ns placement swing), so DON'T change the
# (Quartus TMC-20551: "duplication candidate likely requires more duplication"). Utilization has ample # global mode. Instead close the one 310 MHz EMIF miss surgically via the MAX_FANOUT below.
# headroom now (ALM 85%, DSP 45%, RAM unaffected by opt mode), so BALANCED lets the fitter duplicate set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
# that address register to close the path. Revert to AGGRESSIVE AREA only if a future build re-overflows ALMs. # Ch415: the 8K Z-req FIFO read-address register u_zc_emit|u_req|raddr_hi1_q fans out to ~6 spread M20K blocks
set_global_assignment -name OPTIMIZATION_MODE "BALANCED" # and missed 310 MHz EMIF setup by 103 ps (Quartus TMC-20551 asked for more register duplication, which the
# AGGRESSIVE AREA global mode suppresses). Force duplication of JUST this register so each copy drives a nearby
# block cluster -> shorter routing. Surgical (no global area/placement disruption); ~a few ALMs.
set_instance_assignment -name MAX_FANOUT 3 -to "u_zc_emit|u_req|raddr_hi1_q*"
set_global_assignment -name AUTO_RESOURCE_SHARING ON set_global_assignment -name AUTO_RESOURCE_SHARING ON
# Ch357 (Codex) — SEED left at default (1): seed 1 gave -0.019 (quasi-static EMIF-lock ONLY, all real datapaths met); # Ch357 (Codex) — SEED left at default (1): seed 1 gave -0.019 (quasi-static EMIF-lock ONLY, all real datapaths met);
# seed 2 was worse (-0.155, exposed a different marginal path). The last sliver is closed via the scoped false-path in the SDC. # seed 2 was worse (-0.155, exposed a different marginal path). The last sliver is closed via the scoped false-path in the SDC.