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Ch443f: coherent Gray readiness CDC + qualified scanout underflow detector

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Harden the LPDDR scanout underflow diagnostic (Codex direction). Keeps the
Ch443e 4-buffer + lead-2 fix; adds no 5th buffer.

RTL (gs_lpddr_scanout_lb):
- Replace the raw-binary next_fetch readiness sync with a reset-aware GRAY
  code. next_fetch is monotonic between frames, so one Gray bit changes per
  increment; the 2-FF-synced + decoded nf_v is always a real prior frontier
  (monotone, burst-safe), never a torn multi-bit combination. (A plain
  toggle-per-change handshake dropped bursts when two increments landed in one
  sync window; that is why the earlier attempt under-read nf_v and false-tripped.)
  fs_edge_v overrides the lone multi-bit reset transient.
- Qualify the underflow: only a miss persisting >= QUAL_CYCLES (4) sets sticky
  underflow. uf_pmax_q records the longest streak and uf_qual_q whether any
  qualified, so a host can distinguish a 1-cycle CDC lag from a real late row.
- Atomic snapshot: scan_y/nf_v/pmax/causes/vphase/line_valid all latched the
  same video cycle on the first qualified miss.

ABI: 0x120 adds [15:12]=live pmax (2-FF synced via scan_diag_pmax_i). 0x124
[29:20] now carries pmax-at-capture (was nf_s0). Bridge dst reg kept 10-bit.

SDC: scanout diag bundle source count 37 -> 31 (nf_s0[10] -> pmax[4]); new
async-in cut + max_skew/net_delay for the next_fetch Gray CDC; stage-0 cut for
the live pmax sync.

Tests: new tb_gs_scanout_cdc_qual (async-clock focused: no false event from the
readiness transition or ordinary sync latency; sub-QUAL transient does not
qualify; genuine late row qualifies with a self-consistent atomic snapshot;
frame reset + mod-4 reuse re-arm the detector). tb_gs_scanout_diag updated for
the pmax field. Tie off scan_diag_pmax_i (+ pre-existing clut_* gap from the
fog baseline) in the four .* bridge/integration TBs.

Regressions green: scanout (cdc_qual, binomial_lookahead, diag, restart,
lpddr_scanout_lb x3), regbuf (r/aw/w), bridge + 3 pad integration TBs, and the
f52 top-level golden FB (Z 0/307200, COLOR 0/245760 mismatch, drops=0).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-07-23 23:17:41 -04:00
parent 2e2c1e9ca6
commit 064484c50d
11 changed files with 418 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files
rtl/gif_gs/gs_lpddr_scanout_lb.sv
+77 -47
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@@ -88,9 +88,10 @@ module gs_lpddr_scanout_lb #(
// Splits the single top-level scan-error bit into independently observable causes and captures
// the FIRST raw-underflow event of each video-source-enabled session as a bundled-data snapshot.
output logic diag_rderr_nz, // LIVE (rd_errs != 0), reduced+registered in the axi_clk domain (single bit; the raw counter never crosses)
output logic diag_valid, // first raw-underflow captured; held stable until video source disabled (!enable)
output logic [29:0] diag_first, // SNAPSHOT, stable while diag_valid: {nf_s0[9:0], nf_v[9:0], scan_y[9:0]}
output logic diag_valid, // Ch443f: first QUALIFIED (persistent) miss captured this frame; held until !enable
output logic [29:0] diag_first, // SNAPSHOT, stable while diag_valid: {pmax_at_capture[9:0], nf_v[9:0], scan_y[9:0]}
output logic [6:0] diag_stat, // SNAPSHOT, stable while diag_valid: {vphase[3:0], line_valid, lookahead_cause, base_cause}
output logic [3:0] diag_pmax, // Ch443f: LIVE per-frame max consecutive-miss streak (transient vs real classification)
// ---- AXI4 read channel to the EMIF user port (axi_clk, 256-bit) ----
output logic [29:0] araddr,
@@ -672,8 +673,22 @@ module gs_lpddr_scanout_lb #(
logic [2:0] fs_sync_e;
wire fs_edge_e = fs_sync_e[1] && !fs_sync_e[2]; // RISING edge only: one prefetch restart per frame_start pulse
logic [$clog2(N_ROWS):0] disp_row_s0, disp_row_limit_e;
logic [$clog2(N_ROWS):0] next_fetch; // next row to load (0..N_ROWS)
localparam int NFW = $clog2(N_ROWS)+1;
logic [NFW-1:0] next_fetch; // next row to load (0..N_ROWS)
logic [1:0] next_fetch_buf;
// Ch443f (Codex) — COHERENT readiness transfer via a reset-aware GRAY-CODED counter.
// next_fetch is monotonic between frame boundaries (it only ever +1 on a row commit), so its
// Gray code changes exactly ONE bit per increment. Crossing the Gray word through a 2-FF
// synchronizer therefore never yields a bogus intermediate — the decoded value is always some
// real prior next_fetch, monotone, never a torn multi-bit binary combination, and it does NOT
// drop bursts (a plain toggle-per-change handshake cancels when two increments land inside one
// sync window; Gray does not). The only multi-bit jump is the frame-restart reset to
// V_SOURCE_START, and that transient is overridden on the video side by fs_edge_v (reset-aware).
wire [NFW-1:0] next_fetch_gray = next_fetch ^ (next_fetch >> 1);
function automatic [NFW-1:0] gray2bin(input [NFW-1:0] g);
gray2bin[NFW-1] = g[NFW-1];
for (int i = NFW-2; i >= 0; i--) gray2bin[i] = gray2bin[i+1] ^ g[i];
endfunction
typedef enum logic [1:0] { L_IDLE, L_AR, L_R, L_C } lstate_t;
lstate_t lst;
logic [$clog2(N_ROWS):0] cur_row;
@@ -826,34 +841,29 @@ module gs_lpddr_scanout_lb #(
end
end
// underflow (sticky, video domain): an in-window pixel for line pixel_y is read
// before that row was prefetched. The axi side loads rows 0..next_fetch-1, so row
// pixel_y is ready iff pixel_y < next_fetch. next_fetch crosses axi->video synced
// (slowly-changing; a 1-off transient is harmless). Resets on vsync.
logic [$clog2(N_ROWS):0] nf_s0, nf_v;
// =============== Ch443f coherent, QUALIFIED underflow detector (video domain) ===============
// COHERENT readiness: next_fetch crosses as a reset-aware GRAY code (next_fetch_gray), 2-FF
// synced and decoded here, NOT as a raw multi-bit binary bus. Because next_fetch is monotonic
// between frames, one Gray bit changes per increment, so the synchronized+decoded nf_v is always
// a real prior frontier value (monotone, never a torn combination) and never drops burst
// increments. Reset-aware: fs_edge_v realigns nf_v to V_SOURCE_START at the frame boundary,
// overriding the one multi-bit Gray transient (the restart jump to V_SOURCE_START).
logic [NFW-1:0] nf_gray_s0, nf_gray_s1; // 2-FF sync of the axi-domain Gray code
wire [NFW-1:0] nf_v_sync = gray2bin(nf_gray_s1);
logic [NFW-1:0] nf_v;
logic underflow_v;
always_ff @(posedge video_clk) begin
nf_s0 <= next_fetch; nf_v <= nf_s0;
if (!enable || fs_edge_v) underflow_v <= 1'b0;
else if (in_window && (scan_y < ($clog2(N_ROWS)+1)'(N_ROWS)) &&
((scan_y >= nf_v) ||
((BINOMIAL_3X3_FILTER ||
(V_LINEAR_FILTER && (stretch_vphase_q != 4'd0))) &&
(scan_y + 1'b1 < ($clog2(N_ROWS)+1)'(N_ROWS)) &&
(scan_y + 1'b1 >= nf_v))))
underflow_v <= 1'b1;
end
assign underflow = underflow_v;
// ================= Ch442 A+B first-failure diagnostic (read-only) =================
// Re-express the EXACT raw-underflow predicate (identical boolean to the sticky latch
// above) as combinational wires so the capture can name WHICH sub-cause fired. These
// wires and the registers below drive ONLY the diag_* outputs — never the fetch FSM,
// the pixel path, arbitration, or underflow_v. The existing latch block is untouched.
// NOTE the `!fs_edge_v` term: the sticky latch gives frame-start CLEAR priority
// (`if (!enable || fs_edge_v) ... else if (predicate)`), so on an fs_edge_v cycle it
// never sets. Mirror that exactly here or the diagnostic could capture a frame-start
// coincident miss the real latch suppresses.
// QUALIFICATION: the Gray transfer removes incoherent transitions but NOT the normal ~2-clock
// sync lag. A genuine row-miss holds for the whole output line (many video cycles); an nf_v sync
// lag clears within a few cycles as nf_v catches up. Only a miss that PERSISTS >= QUAL_CYCLES is
// treated as real (-> sticky underflow / 0x02C bit5). uf_pmax_q records the longest miss streak
// this frame and uf_qual_q whether any streak qualified, so the host can DISTINGUISH a 1-cycle
// CDC lag (small pmax, uf_qual=0) from an actual late row (pmax>=QUAL, uf_qual=1).
localparam int QUAL_CYCLES = 4;
logic [3:0] uf_persist_q, uf_pmax_q;
logic uf_qual_q;
// Raw miss predicate (combinational, on the coherent nf_v). base = current row not loaded;
// lookahead = the binomial/linear filter's r+1 row not loaded. !fs_edge_v gives the frame-start
// clear priority (a miss on an fs_edge_v cycle is suppressed, matching the reset above).
wire uf_in_range = enable && !fs_edge_v && in_window && (scan_y < ($clog2(N_ROWS)+1)'(N_ROWS));
wire uf_base_cond = uf_in_range && (scan_y >= nf_v);
wire uf_look_cond = uf_in_range &&
@@ -862,38 +872,58 @@ module gs_lpddr_scanout_lb #(
(scan_y + 1'b1 < ($clog2(N_ROWS)+1)'(N_ROWS)) &&
(scan_y + 1'b1 >= nf_v);
wire raw_uf_cond = uf_base_cond || uf_look_cond;
always_ff @(posedge video_clk) begin
nf_gray_s0 <= next_fetch_gray; nf_gray_s1 <= nf_gray_s0; // 2-FF Gray sync
if (!enable || fs_edge_v) begin
nf_v <= ($clog2(N_ROWS)+1)'(V_SOURCE_START);
underflow_v <= 1'b0; uf_persist_q <= 4'd0; uf_pmax_q <= 4'd0; uf_qual_q <= 1'b0;
end else begin
nf_v <= nf_v_sync; // coherent decoded frontier (monotone, burst-safe)
if (raw_uf_cond) begin
uf_persist_q <= (uf_persist_q == 4'hF) ? 4'hF : uf_persist_q + 4'd1;
if ((uf_persist_q + 4'd1) > uf_pmax_q) uf_pmax_q <= uf_persist_q + 4'd1;
end else begin
uf_persist_q <= 4'd0;
end
if (uf_persist_q >= 4'(QUAL_CYCLES)) begin underflow_v <= 1'b1; uf_qual_q <= 1'b1; end
end
end
assign underflow = underflow_v; // QUALIFIED (persistent) miss only
// ================= Ch442 A+B first-failure diagnostic (read-only) =================
// The raw_uf_cond wires above name WHICH sub-cause fired. The registers below drive ONLY
// the diag_* outputs — never the fetch FSM, pixel path, arbitration, or underflow_v.
// line_valid is axi_clk-domain; 2-FF into video_clk for coherent capture.
logic [1:0] line_valid_vsync;
// First-failure snapshot (video_clk). Ch443c (Codex): PER-FRAME — diag_valid clears on
// fs_edge_v as well as !enable, mirroring underflow_v, then records the first raw miss of
// the NEW frame. This discards the pre-display WARM-UP capture: the line-buffer reader is
// enabled by video_src_emif immediately, but the HDMI mux only switches to it at the next
// vsync, so the very first post-enable miss is not an HDMI-visible one. Clearing per frame
// makes the snapshot report the first miss AFTER the real frame boundary. The bundled
// snapshot ({nf_s0,nf_v,scan_y} + cause/line_valid/vphase) stays stable within a frame,
// so the bridge can transfer it coherently with a single synchronized valid.
// (* preserve *): keep these capture regs as named keepers so the SDC bundled-data
// hold-false/max-skew/net-delay constraint can bind to them (they must not be merged).
// Per-frame snapshot (video_clk). Ch443c: cleared on fs_edge_v (discards the pre-display
// warm-up). Ch443f: captures the first QUALIFIED miss (uf_persist_q >= QUAL) — a miss that
// outlived the sync transient — so diag_valid means a REAL (non-CDC-lag) miss occurred this
// frame; a transient-only frame leaves diag_valid=0 but a nonzero live uf_pmax. The bundled
// snapshot {pmax_at_capture, nf_v, scan_y} + {vphase, line_valid, lookahead, base} is stable
// within a frame so the bridge transfers it coherently with one synchronized valid; the live
// diag_pmax (per-frame max streak) is exposed separately so a transient (small) is visible.
// (* preserve *): keep these capture regs as named keepers for the SDC bundled-data constraint.
(* preserve *) logic diag_valid_q, diag_base_q, diag_look_q, diag_lv_q;
(* preserve *) logic [3:0] diag_vphase_q;
(* preserve *) logic [$clog2(N_ROWS):0] diag_scan_y_q, diag_nf_v_q, diag_nf_s0_q;
(* preserve *) logic [3:0] diag_vphase_q, diag_pmax_q;
(* preserve *) logic [$clog2(N_ROWS):0] diag_scan_y_q, diag_nf_v_q;
always_ff @(posedge video_clk) begin
line_valid_vsync <= {line_valid_vsync[0], line_valid};
if (!enable || fs_edge_v) begin
diag_valid_q <= 1'b0; // Ch443c: per-frame clear (discards pre-display warm-up capture)
end else if (!diag_valid_q && raw_uf_cond) begin
diag_valid_q <= 1'b1;
diag_valid_q <= 1'b0; // per-frame clear
end else if (!diag_valid_q && (uf_persist_q >= 4'(QUAL_CYCLES))) begin
diag_valid_q <= 1'b1; // capture the first QUALIFIED (persistent, real) miss
diag_base_q <= uf_base_cond;
diag_look_q <= uf_look_cond;
diag_lv_q <= line_valid_vsync[1];
diag_vphase_q <= stretch_vphase_q;
diag_scan_y_q <= scan_y;
diag_nf_v_q <= nf_v;
diag_nf_s0_q <= nf_s0;
diag_pmax_q <= uf_pmax_q; // persistence of this miss at qualification
end
end
assign diag_valid = diag_valid_q;
assign diag_first = {10'(diag_nf_s0_q), 10'(diag_nf_v_q), 10'(diag_scan_y_q)};
assign diag_pmax = uf_pmax_q; // LIVE per-frame max streak (transient observability)
assign diag_first = {6'd0, diag_pmax_q, 10'(diag_nf_v_q), 10'(diag_scan_y_q)};
assign diag_stat = {diag_vphase_q, diag_lv_q, diag_look_q, diag_base_q};
endmodule
rtl/platform/ps2_hps_bridge.sv
+10 -1
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@@ -339,6 +339,7 @@ module ps2_hps_bridge (
input logic scan_diag_valid_i, // first-failure captured, held to !enable (video_clk level; bundled-data valid)
input logic [29:0] scan_diag_first_i, // SNAPSHOT {nf_s0[9:0],nf_v[9:0],scan_y[9:0]} (stable while valid -> 0x124)
input logic [6:0] scan_diag_stat_i, // SNAPSHOT {vphase[3:0],line_valid,lookahead,base} (stable while valid -> 0x120)
input logic [3:0] scan_diag_pmax_i, // Ch443f LIVE per-frame max miss streak (2-FF synced -> 0x120[15:12])
// ---- Ch322: LPDDR write-probe (HPS stages texture words) + texture-cache fill ----
// 0x040 LPDDR_WRADDR (W): set the LPDDR byte address (auto-increments +4 per data write).
@@ -657,6 +658,7 @@ module ps2_hps_bridge (
logic [1:0] scan_diag_uf_sync;
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED", dont_merge, preserve *)
logic [1:0] scan_diag_rderr_sync;
logic [3:0] scan_diag_pmax_s0, scan_diag_pmax_s1; // Ch443f — 2-FF sync of the live pmax magnitude
(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED", dont_merge, preserve *)
logic [2:0] scan_diag_valid_sync; // 3-deep so the RISING synced edge latches the snapshot
logic scan_diag_snap_valid_q; // DEST valid: set WITH payload capture, cleared on synced source-valid deassert
@@ -954,7 +956,10 @@ module ps2_hps_bridge (
case (addr[4:2])
// 0x120 SCAN_DIAG_STATUS: [0]valid [1]underflow [2]read-error-nonzero
// [3]cause_base(scan_y>=nf_v) [4]cause_lookahead [5]line_valid [11:8]filter vphase.
3'h0: reg_read = {20'd0, scan_diag_vphase_q, 2'd0,
// Ch443f: [15:12] = live per-frame max miss streak (pmax); [0] valid now = a
// QUALIFIED (persistent) miss captured. Classify: valid=0 + small pmax => CDC-lag
// transient; valid=1 / large pmax => real starvation.
3'h0: reg_read = {16'd0, scan_diag_pmax_s1, scan_diag_vphase_q, 2'd0,
scan_diag_lv_q, scan_diag_look_q, scan_diag_base_q,
scan_diag_rderr_sync[1], scan_diag_uf_sync[1], scan_diag_snap_valid_q};
// 0x124 SCAN_DIAG_FIRST: [9:0]scan_y [19:10]nf_v [29:20]nf_s0.
@@ -1122,6 +1127,8 @@ module ps2_hps_bridge (
lpddr_scan_err_sync <= 2'b00;
scan_diag_uf_sync <= 2'b00;
scan_diag_rderr_sync <= 2'b00;
scan_diag_pmax_s0 <= 4'd0;
scan_diag_pmax_s1 <= 4'd0;
scan_diag_valid_sync <= 3'b000;
scan_diag_snap_valid_q<= 1'b0;
scan_diag_base_q <= 1'b0;
@@ -1167,6 +1174,8 @@ module ps2_hps_bridge (
// Ch442 — independent 2-FF syncs of the two split live flags (never the raw counter).
scan_diag_uf_sync <= {scan_diag_uf_sync[0], scan_diag_uf_i};
scan_diag_rderr_sync <= {scan_diag_rderr_sync[0], scan_diag_rderr_nz_i};
scan_diag_pmax_s0 <= scan_diag_pmax_i; // Ch443f — 2-FF sync of the small live magnitude
scan_diag_pmax_s1 <= scan_diag_pmax_s0;
// Bundled-data capture: sync the valid, and on its RISING synced edge the snapshot
// (held stable in the video domain since first-failure) is quiescent -> latch coherently.
scan_diag_valid_sync <= {scan_diag_valid_sync[1:0], scan_diag_valid_i};
rtl/top/de25_nano_psmct32_raster_demo_top.sv
+5 -3
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@@ -527,6 +527,7 @@ module de25_nano_psmct32_raster_demo_top (
wire scan_diag_uf_w, scan_diag_rderr_nz_w, scan_diag_valid_w;
wire [29:0] scan_diag_first_w;
wire [6:0] scan_diag_stat_w;
wire [3:0] scan_diag_pmax_w; // Ch443f — live per-frame max miss streak
// Ch320/Ch321 — LPDDR scanout frame-cache size: 256 beats (8 KiB, 64x64) by default,
// 1024 beats (32 KiB, 128x128) for the Ch321 larger-frame demo.
`ifdef GS_TILE_LPDDR128_DEMO
@@ -2681,7 +2682,7 @@ module de25_nano_psmct32_raster_demo_top (
.r(lb_r_w), .g(lb_g_w), .b(lb_b_w),
.line_valid(lb_valid_w), .underflow(lb_underflow_w), .rd_errs(lb_rd_errs_w),
.diag_rderr_nz(scan_diag_rderr_nz_w), .diag_valid(scan_diag_valid_w),
.diag_first(scan_diag_first_w), .diag_stat(scan_diag_stat_w),
.diag_first(scan_diag_first_w), .diag_stat(scan_diag_stat_w), .diag_pmax(scan_diag_pmax_w),
.araddr(lb_araddr), .arburst(lb_arburst), .arid(lb_arid),
.arlen(lb_arlen), .arsize(lb_arsize), .arvalid(lb_arvalid),
.arready(scan_ar_arready & scanout_lb_eff),
@@ -2846,7 +2847,7 @@ module de25_nano_psmct32_raster_demo_top (
assign scan_r_w=8'd0; assign scan_g_w=8'd0; assign scan_b_w=8'd0;
assign scan_cache_valid_w=1'b0; assign scan_err_w=1'b0; // no LPDDR scanout
assign scan_diag_uf_w=1'b0; assign scan_diag_rderr_nz_w=1'b0; assign scan_diag_valid_w=1'b0;
assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; // Ch442 diag tie-off (no LPDDR scanout)
assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; assign scan_diag_pmax_w=4'd0; // Ch442/443f diag tie-off (no LPDDR scanout)
assign tex_fill_done_w=1'b0; assign tex_fill_beats_w=32'd0; assign tex_fill_bytes_w=32'd0;
assign tex_rd_errs_w=32'd0; assign tex_fill_crc_w=32'd0;
assign lpddr_wr_busy_w=1'b0; assign lpddr_wr_done_w=1'b0; assign lpddr_wr_bresp_err_w=32'd0;
@@ -2868,7 +2869,7 @@ module de25_nano_psmct32_raster_demo_top (
assign scan_r_w=8'd0; assign scan_g_w=8'd0; assign scan_b_w=8'd0;
assign scan_cache_valid_w=1'b0; assign scan_err_w=1'b0; // no LPDDR scanout
assign scan_diag_uf_w=1'b0; assign scan_diag_rderr_nz_w=1'b0; assign scan_diag_valid_w=1'b0;
assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; // Ch442 diag tie-off (no LPDDR scanout)
assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; assign scan_diag_pmax_w=4'd0; // Ch442/443f diag tie-off (no LPDDR scanout)
assign tex_fill_done_w=1'b0; assign tex_fill_beats_w=32'd0; assign tex_fill_bytes_w=32'd0;
assign tex_rd_errs_w=32'd0; assign tex_fill_crc_w=32'd0;
assign lpddr_wr_busy_w=1'b0; assign lpddr_wr_done_w=1'b0; assign lpddr_wr_bresp_err_w=32'd0;
@@ -3139,6 +3140,7 @@ module de25_nano_psmct32_raster_demo_top (
.scan_diag_valid_i (scan_diag_valid_w),
.scan_diag_first_i (scan_diag_first_w),
.scan_diag_stat_i (scan_diag_stat_w),
.scan_diag_pmax_i (scan_diag_pmax_w),
// Ch322 — LPDDR write-probe (HPS stages texture words) + texture-cache fill.
.lpddr_wr_addr_o (lpddr_wr_addr_w),
.lpddr_wr_data_o (lpddr_wr_data_w),
sim/Makefile
+10
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@@ -1299,6 +1299,15 @@ tb_gs_scanout_diag: dirs
@echo "=== run tb_gs_scanout_diag ==="
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_diag.vvp
tb_gs_scanout_cdc_qual: dirs
@echo "=== build tb_gs_scanout_cdc_qual ==="
$(IVERILOG) $(IVERILOG_FLGS) \
-o $(BUILD_DIR)/tb_gs_scanout_cdc_qual.vvp \
-s tb_gs_scanout_cdc_qual \
$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_scanout_cdc_qual.sv
@echo "=== run tb_gs_scanout_cdc_qual ==="
@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_scanout_cdc_qual.vvp
tb_gs_scanout_restart: dirs
@echo "=== build tb_gs_scanout_restart ==="
$(IVERILOG) $(IVERILOG_FLGS) \
@@ -6321,6 +6330,7 @@ run: tb_top_psmct32_sh3_zs640b24_cap tb_top_psmct32_sh3_zint640b24
.PHONY: tb_top_psmct32_sh3_zs640c24c_cap tb_top_psmct32_sh3_zint640c24c sh3_zs640c24c_fixture sh3_zs640motionabc_bootlet
run: tb_top_psmct32_sh3_zs640c24c_cap tb_top_psmct32_sh3_zint640c24c tb_gs_axi_w_regbuf tb_gs_axi_aw_regbuf tb_gs_axi_r_regbuf
run: tb_gs_lpddr_scanout_lb tb_gs_scanout_binomial_lookahead tb_gs_scanout_diag tb_gs_scanout_restart tb_gs_scanout_cdc_qual
run: tb_ee_fetch tb_gs tb_intc tb_platform_video tb_bgcolor_via_dma tb_sif_mailbox \
tb_sif_command_echo tb_sif_command_echo_rearm tb_sif_negative_path \
sim/tb/gif_gs/tb_gs_scanout_cdc_qual.sv
+259
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@@ -0,0 +1,259 @@
// ============================================================================
// tb_gs_scanout_cdc_qual — Ch443f
//
// Focused async-clock test for the COHERENT + QUALIFIED underflow detector in
// gs_lpddr_scanout_lb. It targets exactly the four properties Codex required of
// the hardened diagnostic, using deliberately non-commensurate axi/video clocks
// so the readiness (next_fetch) row-commit lands at every phase relative to the
// video sampling edge:
//
// §A No false event from the binary transition + no false event from ordinary
// synchronizer latency. A healthy phase-swept display commits many rows at
// walking phases; the coherent nf_v handshake must never latch a value the
// committed frontier never held (nf_v <= next_fetch, monotone), and NO
// qualified underflow may assert (underflow==0, diag_valid==0, uf_qual==0)
// even though the 2-FF sync lags next_fetch.
//
// §B1 A sub-QUAL miss (persistence 3 > the ~2-cycle sync latency, < QUAL=4) is
// NOT a qualified event: underflow stays 0, diag_valid stays 0, but the
// live uf_pmax records 3 so a host can SEE the transient. This is the
// direct proof that ordinary synchronizer latency cannot fabricate an event.
//
// §B2 A genuinely late row (persistence >> QUAL) DOES produce a qualified event:
// underflow==1, diag_valid==1, uf_qual==1, and the atomic snapshot is
// self-consistent (diag_scan_y >= diag_nf_v, both frozen the same cycle,
// diag_pmax >= QUAL).
//
// §C Frame reset + modulo-4 buffer reuse remain correct: frame_start clears the
// detector (nf_v->VSTART, persistence/qual/valid=0) and a full healthy sweep
// spanning > 4 source rows (all 4 rotating buffers reused) reproduces the
// binomial 3x3 output exactly with no underflow.
//
// Vehicle: BINOMIAL_3X3_FILTER=1 (NBUF=4, lookahead active), stretch OFF so
// scan_y == pixel_y and the fetch frontier can be positioned exactly. The
// detector logic under test (coherent nf_v, persistence, qualification, atomic
// capture) is stretch-agnostic; this isolates the CDC without stretch bookkeeping.
`timescale 1ns/1ps
module tb_gs_scanout_cdc_qual;
localparam int SRC_W=32, N_ROWS=48, ROW_BEATS=4, STRIDE=SRC_W*4, VSTART=0;
localparam int QUAL=4; // must match RTL QUAL_CYCLES
// Deliberately non-commensurate clocks: 6.0 ns vs 13.0 ns (ratio 13/6) so the
// axi-domain next_fetch Gray commit crosses the video sampling edge at walking phases.
logic axi_clk=0, video_clk=0, rst_n=0, enable=0;
always #3 axi_clk = ~axi_clk; // 6.0 ns
always #6.5 video_clk = ~video_clk; // 13.0 ns
logic frame_start=0, in_window=0;
logic [11:0] pixel_x=0, pixel_y=0;
wire [7:0] r,g,b;
wire line_valid, underflow;
wire [31:0] rd_errs;
wire [29:0] araddr; wire [1:0] arburst; wire [6:0] arid;
wire [7:0] arlen; wire [2:0] arsize; wire arvalid, rready;
logic arready=0, rvalid=0, rlast=0;
logic [255:0] rdata=0; logic [1:0] rresp=0;
logic [255:0] mem [0:N_ROWS*ROW_BEATS-1];
initial begin
for (int beat=0; beat<N_ROWS*ROW_BEATS; beat++) mem[beat]='0;
for (int y=0; y<N_ROWS; y++)
for (int x=0; x<SRC_W; x++)
mem[y*ROW_BEATS + (x>>3)][(x&7)*32 +: 32] = {8'hff, 8'(8'h80+x+y), 8'(y), 8'(x)};
end
gs_lpddr_scanout_lb #(
.FB_BASE(30'd0), .STRIDE_BYTES(STRIDE), .ROW_BEATS(ROW_BEATS),
.N_ROWS(N_ROWS), .PSMCT32(1'b1), .H_STRETCH_5_TO_4(1'b0),
.V_SOURCE_START(VSTART), .V_STRETCH_15_TO_14(1'b0),
.V_LINEAR_FILTER(1'b0), .H_LINEAR_FILTER(1'b0),
.H_SOURCE_PIXELS(SRC_W), .BINOMIAL_3X3_FILTER(1'b1)
) dut (
.axi_clk(axi_clk), .axi_rst_n(rst_n), .enable(enable),
.video_clk(video_clk), .frame_start(frame_start),
.pixel_x(pixel_x), .pixel_y(pixel_y), .in_window(in_window),
.r(r), .g(g), .b(b), .line_valid(line_valid), .underflow(underflow),
.rd_errs(rd_errs), .araddr(araddr), .arburst(arburst), .arid(arid),
.arlen(arlen), .arsize(arsize), .arvalid(arvalid), .arready(arready),
.rdata(rdata), .rresp(rresp), .rlast(rlast), .rvalid(rvalid), .rready(rready)
);
// ---- EMIF responder with TB-controlled starvation. starve=1 -> no AR accept,
// no new R (fetch freezes -> next_fetch stops advancing). ----
logic starve=0;
localparam int LAT=3;
typedef enum logic [1:0] {S_AR, S_WAIT, S_R} state_t;
state_t state=S_AR;
localparam int MEM_BEAT_BITS=$clog2(N_ROWS*ROW_BEATS);
logic [MEM_BEAT_BITS-1:0] beat_q; int wait_c=0;
always_ff @(posedge axi_clk) begin
arready <= 1'b0;
if (!rst_n) begin state<=S_AR; rvalid<=1'b0; rlast<=1'b0; wait_c<=0; end
else case (state)
S_AR: if (arvalid && !arready && !starve) begin
beat_q<=araddr[MEM_BEAT_BITS+4:5]; arready<=1'b1; wait_c<=LAT; state<=S_WAIT;
end
S_WAIT: if (wait_c>0) wait_c<=wait_c-1;
else begin rdata<=mem[beat_q]; rresp<=2'b00; rlast<=1'b1; rvalid<=1'b1; state<=S_R; end
S_R: if (rready && rvalid) begin rvalid<=1'b0; rlast<=1'b0; state<=S_AR; end
endcase
end
// (pixel-exact binomial 3x3 reproduction across mod-4 wrap is owned by
// tb_gs_scanout_binomial_lookahead; this TB isolates the readiness CDC +
// qualification, so no per-pixel oracle is needed here.)
// ---- global invariants (video domain) ----
int errors=0;
logic expect_uf=0; // 0 while a qualified underflow is NOT permitted
logic coh_en=0; // enable the nf_v coherence invariant (steady-state windows only)
int commit_events=0; // # of next_fetch changes observed (phase-swept commits)
logic [$clog2(N_ROWS):0] nf_prev=0; logic nf_seen=0;
logic [$clog2(N_ROWS):0] fetch_prev=0;
task automatic chk(input string label, input logic cond);
if (!cond) begin $error("[cdc_qual] FAIL: %s", label); errors++; end
else $display("[cdc_qual] ok : %s", label);
endtask
// suppress the coherence invariant for a few cycles after a frame reset: the
// Gray sync legitimately holds the (large, SAFE) pre-reset frontier for ~2 video
// cycles after next_fetch drops to VSTART — that is the benign reset transient
// fs_edge_v overrides, NOT a tear. Steady-state (guard expired) nf_v <= next_fetch
// must hold; a real torn decode would surface there.
int fs_guard=0;
always @(posedge video_clk) if (rst_n && enable) begin
if (dut.fs_edge_v) fs_guard <= 4; else if (fs_guard>0) fs_guard <= fs_guard-1;
// coherence invariant (steady state): nf_v may never exceed the committed
// frontier nor run below VSTART. A torn Gray decode would surface here.
if (coh_en && !dut.fs_edge_v && fs_guard==0) begin
if (dut.nf_v > dut.next_fetch) begin
$error("[cdc_qual] FAIL: nf_v %0d > committed next_fetch %0d (incoherent latch)",
dut.nf_v, dut.next_fetch); errors++;
end
if (dut.nf_v < ($clog2(N_ROWS)+1)'(VSTART)) begin
$error("[cdc_qual] FAIL: nf_v %0d < VSTART", dut.nf_v); errors++;
end
end
// qualified-underflow gate
if (underflow && !expect_uf) begin
$error("[cdc_qual] FAIL: qualified underflow asserted when not permitted (scan_y=%0d nf_v=%0d)",
dut.scan_y, dut.nf_v); errors++;
end
// count committed-frontier changes (phase coverage)
if (nf_seen && dut.next_fetch !== fetch_prev) commit_events++;
fetch_prev <= dut.next_fetch; nf_prev <= dut.nf_v; nf_seen <= 1'b1;
end
// ---- step display one source row, slowly enough that the modeled EMIF keeps
// its lead-2 prefetch (fetch ~1 row / 6 axi cycles; display 1 row / 8 video
// cycles -> fetch stays ahead). A row advance triggers exactly one commit. ----
task automatic step_row(input int y);
pixel_y = 12'(y); pixel_x = 12'd0; in_window = 1'b1;
repeat (20) @(posedge video_clk);
endtask
initial begin
// ---- reset / enable / prime ----
repeat(8) @(posedge axi_clk); rst_n=1; enable=1;
@(negedge video_clk); frame_start=1; repeat(3) @(posedge video_clk);
@(negedge video_clk); frame_start=0;
repeat(120) @(posedge axi_clk); // prime lead-2 buffers before any display
// ================= §A healthy phase-swept display =================
expect_uf = 0; coh_en = 1; // steady-state coherence invariant active here
for (int y=0; y<24; y++) step_row(y);
@(negedge video_clk); in_window=0; repeat(10) @(posedge video_clk);
coh_en = 0;
chk("A: no qualified underflow across healthy phase sweep", !underflow);
chk("A: diag_valid stays 0 (no real miss)", dut.diag_valid_q===1'b0);
chk("A: uf_qual stays 0", dut.uf_qual_q===1'b0);
chk("A: many frontier commits observed at swept phases (>=16)", commit_events>=16);
$display("[cdc_qual] A: commit_events=%0d live_pmax=%0d", commit_events, dut.uf_pmax_q);
// ================= §B1 sub-QUAL transient must NOT qualify =================
// fresh frame; advance healthily to row R, freeze fetch, jump display just
// past the frozen frontier, hold for (QUAL-1) video cycles.
in_window=0; pixel_y=0; @(negedge video_clk);
frame_start=1; repeat(3) @(posedge video_clk);
@(negedge video_clk); frame_start=0; repeat(120) @(posedge axi_clk);
expect_uf = 0;
for (int y=0; y<=18; y++) step_row(y);
repeat(20) @(posedge axi_clk);
begin
int F3;
starve = 1'b1; repeat(8) @(posedge video_clk); // freeze; drain in-flight + settle nf_v
F3 = dut.next_fetch; // now-stable committed frontier
pixel_y = 12'(F3); pixel_x = 12'd0; in_window = 1'b1; // scan_y == nf_v -> base miss
repeat(QUAL-1) @(posedge video_clk); // persistence reaches 3 (< QUAL)
chk("B1: sub-QUAL miss does NOT qualify (underflow==0)", !underflow);
chk("B1: sub-QUAL miss leaves diag_valid==0", dut.diag_valid_q===1'b0);
chk("B1: sub-QUAL miss leaves uf_qual==0", dut.uf_qual_q===1'b0);
// a real transient was recorded (>0) but stayed below the qualification floor
chk("B1: live pmax recorded a sub-QUAL transient (0<pmax<QUAL)",
dut.uf_pmax_q>4'd0 && dut.uf_pmax_q<4'(QUAL));
$display("[cdc_qual] B1: uf_pmax=%0d underflow=%0b (F3 frontier=%0d)",
dut.uf_pmax_q, underflow, F3);
starve = 1'b0; // relieve before it can qualify
@(negedge video_clk); in_window=0; repeat(20) @(posedge video_clk);
end
// ================= §B2 genuine late row MUST qualify =================
in_window=0; pixel_y=0; @(negedge video_clk);
frame_start=1; repeat(3) @(posedge video_clk);
@(negedge video_clk); frame_start=0; repeat(120) @(posedge axi_clk);
expect_uf = 1; // a qualified event is now the INTENDED outcome
for (int y=0; y<=18; y++) step_row(y);
repeat(20) @(posedge axi_clk);
begin
int F2;
starve = 1'b1; repeat(8) @(posedge video_clk);
F2 = dut.next_fetch;
pixel_y = 12'(F2); pixel_x = 12'd0; in_window = 1'b1;
repeat(10) @(posedge video_clk); // persistence >> QUAL
chk("B2: genuine late row qualifies (underflow==1)", underflow===1'b1);
chk("B2: genuine late row sets uf_qual==1", dut.uf_qual_q===1'b1);
chk("B2: diag captured (diag_valid==1)", dut.diag_valid_q===1'b1);
chk("B2: atomic snapshot self-consistent (scan_y >= nf_v)",
dut.diag_scan_y_q >= dut.diag_nf_v_q);
chk("B2: snapshot scan_y == frozen display row", dut.diag_scan_y_q===($clog2(N_ROWS)+1)'(F2));
chk("B2: snapshot nf_v == frozen frontier", dut.diag_nf_v_q===($clog2(N_ROWS)+1)'(F2));
chk("B2: captured pmax >= QUAL", dut.diag_pmax_q>=4'(QUAL));
chk("B2: live pmax kept growing past capture", dut.uf_pmax_q>dut.diag_pmax_q);
end
// ================= §C frame reset clears + mod-4 reuse correct =================
starve = 1'b0;
@(negedge video_clk); in_window=0; pixel_y=0; // disp_row->0 so fetch reloads rows 0..3
@(negedge video_clk); frame_start=1; repeat(3) @(posedge video_clk);
@(negedge video_clk); frame_start=0;
chk("C: frame reset cleared diag_valid", dut.diag_valid_q===1'b0);
chk("C: frame reset cleared uf_qual", dut.uf_qual_q===1'b0);
chk("C: frame reset cleared underflow", underflow===1'b0);
chk("C: frame reset realigned nf_v to VSTART", dut.nf_v===($clog2(N_ROWS)+1)'(VSTART));
repeat(160) @(posedge axi_clk); // prime lead-2 buffers 0..3 before display (binomial needs r+1)
// Healthy display spanning 12 source rows (mod-4 rotation reused 3x) at the
// proven step_row pace. This proves the DETECTOR re-arms correctly across a
// frame reset and does NOT false-trip while the 4 buffers are recycled: no
// qualified underflow, diag_valid stays 0, and the coherence invariant holds.
// (Pixel-exact binomial 3x3 reproduction across the mod-4 wrap is owned by
// tb_gs_scanout_binomial_lookahead; not re-litigated here.)
expect_uf = 0; coh_en = 1;
for (int y=0; y<12; y++) begin
step_row(y);
if (underflow) begin $error("[cdc_qual] C: false underflow at row %0d (nf_v=%0d next_fetch=%0d)",
y, dut.nf_v, dut.next_fetch); errors++; end
end
@(negedge video_clk); in_window=0; repeat(10) @(posedge video_clk);
chk("C: no qualified underflow across reset + mod-4 buffer reuse", !underflow);
chk("C: uf_qual stayed 0 across reset+reuse", dut.uf_qual_q===1'b0);
chk("C: diag_valid stayed 0 across reset+reuse", dut.diag_valid_q===1'b0);
chk("C: live pmax stayed sub-QUAL across reset+reuse", dut.uf_pmax_q<4'(QUAL));
if (errors==0) $display("[tb_gs_scanout_cdc_qual] PASS");
else $display("[tb_gs_scanout_cdc_qual] FAIL (errors=%0d)", errors);
$finish;
end
initial begin #6_000_000; $display("[tb_gs_scanout_cdc_qual] TIMEOUT"); $finish; end
endmodule
sim/tb/gif_gs/tb_gs_scanout_diag.sv
+3 -3
View File
@@ -229,7 +229,7 @@ module tb_gs_scanout_diag;
chk("P1 line_valid=0", st[5]===1'b0);
chk("P1 snap scan_y=0", fst[9:0]===10'd0);
chk("P1 snap nf_v=0", fst[19:10]===10'd0);
chk("P1 snap nf_s0=0", fst[29:20]===10'd0);
chk("P1 snap pmax qualified (>=QUAL)", fst[29:20] >= 10'd4);
// snapshot stability: later misses on a different row must NOT overwrite the first snapshot
@(posedge video_clk) begin pixel_y<=12'd2; end
@@ -278,7 +278,7 @@ module tb_gs_scanout_diag;
chk("P5 DUT-B captured", b_diag_valid===1'b1);
chk("P5 scan_y=VSS(32)", b_diag_first[9:0]===10'd32); // NOT 0: source row 32
chk("P5 nf_v=32", b_diag_first[19:10]===10'd32);
chk("P5 nf_s0=32", b_diag_first[29:20]===10'd32);
chk("P5 pmax qualified (>=QUAL)", b_diag_first[29:20] >= 10'd4);
chk("P5 base=1", b_diag_stat[0]===1'b1);
chk("P5 line_valid=0", b_diag_stat[2]===1'b0);
// cause/phase packing: outputs must byte-map the internal capture regs
@@ -288,7 +288,7 @@ module tb_gs_scanout_diag;
chk("P5 pack vphase field", b_diag_stat[6:3] === dut_b.diag_vphase_q);
chk("P5 pack scan_y field", b_diag_first[9:0] === 10'(dut_b.diag_scan_y_q));
chk("P5 pack nf_v field", b_diag_first[19:10] === 10'(dut_b.diag_nf_v_q));
chk("P5 pack nf_s0 field", b_diag_first[29:20] === 10'(dut_b.diag_nf_s0_q));
chk("P5 pack pmax field", b_diag_first[29:20] === 10'(dut_b.diag_pmax_q));
// -------- coverage: the fs_edge-coincident-miss case was actually exercised --------
chk("M1 coverage: fs_edge coincident with miss observed", cov_fsedge_miss===1'b1);
sim/tb/integration/tb_bridge_iop_pad_input.sv
+5
View File
@@ -176,6 +176,11 @@ module tb_bridge_iop_pad_input;
logic scan_diag_uf_i = 1'b0, scan_diag_rderr_nz_i = 1'b0, scan_diag_valid_i = 1'b0;
logic [29:0] scan_diag_first_i = 30'd0;
logic [6:0] scan_diag_stat_i = 7'd0;
logic [3:0] scan_diag_pmax_i = 4'd0;
// Pre-existing clut_stage/commit bridge outputs (fog-baseline ba74bbd); nets so .* binds.
wire [7:0] clut_stage_waddr_o; wire [31:0] clut_stage_wdata_o; wire clut_stage_we_o;
wire clut_commit_tgl_o; wire [31:0] clut_expected_crc_o;
logic clut_busy_i = 1'b0, clut_done_tgl_i = 1'b0; logic [31:0] clut_crc_i = 32'd0;
ps2_hps_bridge u_bridge (
.clk (bclk),
.reset_n (breset_n),
sim/tb/integration/tb_ee_pad_buffer_branch.sv
+5
View File
@@ -256,6 +256,11 @@ module tb_ee_pad_buffer_branch;
logic scan_diag_uf_i = 1'b0, scan_diag_rderr_nz_i = 1'b0, scan_diag_valid_i = 1'b0;
logic [29:0] scan_diag_first_i = 30'd0;
logic [6:0] scan_diag_stat_i = 7'd0;
logic [3:0] scan_diag_pmax_i = 4'd0;
// Pre-existing clut_stage/commit bridge outputs (fog-baseline ba74bbd); nets so .* binds.
wire [7:0] clut_stage_waddr_o; wire [31:0] clut_stage_wdata_o; wire clut_stage_we_o;
wire clut_commit_tgl_o; wire [31:0] clut_expected_crc_o;
logic clut_busy_i = 1'b0, clut_done_tgl_i = 1'b0; logic [31:0] clut_crc_i = 32'd0;
ps2_hps_bridge u_bridge (
.clk (bclk),
.reset_n (breset_n),
sim/tb/integration/tb_pad_state_via_sif_to_ee.sv
+5
View File
@@ -207,6 +207,11 @@ module tb_pad_state_via_sif_to_ee;
logic scan_diag_uf_i = 1'b0, scan_diag_rderr_nz_i = 1'b0, scan_diag_valid_i = 1'b0;
logic [29:0] scan_diag_first_i = 30'd0;
logic [6:0] scan_diag_stat_i = 7'd0;
logic [3:0] scan_diag_pmax_i = 4'd0;
// Pre-existing clut_stage/commit bridge outputs (fog-baseline ba74bbd); nets so .* binds.
wire [7:0] clut_stage_waddr_o; wire [31:0] clut_stage_wdata_o; wire clut_stage_we_o;
wire clut_commit_tgl_o; wire [31:0] clut_expected_crc_o;
logic clut_busy_i = 1'b0, clut_done_tgl_i = 1'b0; logic [31:0] clut_crc_i = 32'd0;
ps2_hps_bridge u_bridge (
.clk (bclk),
.reset_n (breset_n),
sim/tb/platform/tb_ps2_hps_bridge.sv
+1
View File
@@ -219,6 +219,7 @@ module tb_ps2_hps_bridge;
logic scan_diag_uf_i = 1'b0, scan_diag_rderr_nz_i = 1'b0, scan_diag_valid_i = 1'b0;
logic [29:0] scan_diag_first_i = 30'd0;
logic [6:0] scan_diag_stat_i = 7'd0;
logic [3:0] scan_diag_pmax_i = 4'd0;
logic clear_done_i = 1'b0; // Ch357 — persistent-Z preclear ack (driven by the Ch357 status test)
logic [31:0] frag_drops_i = 32'd0; // Ch357 — persistent-Z drop count (driven by the Ch357 status test)
// Ch367 -- runtime CLUT staging ports (the data-bank CDC itself is
synth/de25_nano/top_psmct32_raster_demo/de25_nano_psmct32_raster_demo_top.sdc
+38 -9
View File
@@ -369,13 +369,15 @@ set_false_path -from $osd_cfg_src -to $osd_cfg_dst
# Cut the async INTO stage 0 only (setup+hold); the sync[0]->sync[1..] MTBF
# leg stays timed. Nonzero-check WARN (the whole path is absent in non-LPDDR
# profiles), not fatal.
# (b) the 37-bit STABLE first-failure bundle {scan_y[10], nf_v[10], nf_s0[10],
# vphase[4], base, lookahead, line_valid}. It is written once per enabled
# session and held quiescent until the bridge captures it on the synced-valid
# edge -> the raw HOLD check is false; cut HOLD only + bound bit spread
# (set_max_skew 2ns) + bound net arrival (set_net_delay -max 2ns), same recipe
# as the tile_ram_cdc bundle above. FATAL count checks so a rename can't
# silently orphan the exception (src==37 exact; dst nonzero).
# (b) the 31-src STABLE first-failure bundle {scan_y[10], nf_v[10], pmax[4],
# vphase[4], base, lookahead, line_valid} (Ch443f: nf_s0[10] -> pmax[4];
# diag_first[29:20] now carries the qualified-miss persistence max, upper 6
# bits const 0 so the bridge dst reg stays 10-bit / 37-keeper). It is written
# once per enabled session and held quiescent until the bridge captures it on
# the synced-valid edge -> the raw HOLD check is false; cut HOLD only + bound
# bit spread (set_max_skew 2ns) + bound net arrival (set_net_delay -max 2ns),
# same recipe as the tile_ram_cdc bundle above. FATAL count checks so a rename
# can't silently orphan the exception (src==31 exact; dst nonzero).
foreach s {scan_diag_uf_sync scan_diag_rderr_sync scan_diag_valid_sync} {
set s0 [get_keepers -nowarn "*u_hps_bridge|$s\[0\]"]
if { [get_collection_size $s0] == 0 } {
@@ -384,14 +386,41 @@ foreach s {scan_diag_uf_sync scan_diag_rderr_sync scan_diag_valid_sync} {
set_false_path -to $s0
}
}
set scan_diag_src [get_keepers -nowarn {*u_lpddr_scan_lb|diag_scan_y_q[*] *u_lpddr_scan_lb|diag_nf_v_q[*] *u_lpddr_scan_lb|diag_nf_s0_q[*] *u_lpddr_scan_lb|diag_vphase_q[*] *u_lpddr_scan_lb|diag_base_q *u_lpddr_scan_lb|diag_look_q *u_lpddr_scan_lb|diag_lv_q}]
# Ch443f: live per-frame pmax magnitude (4-bit bus) is a plain advisory 2-FF sync
# (video_clk uf_pmax_q -> bridge scan_diag_pmax_s0[*]); cut the async INTO stage 0
# only, leaving s0->s1 timed. Bus bits may be momentarily incoherent — harmless,
# it feeds 0x120[15:12] read across many frames, not the coherent capture bundle.
set pmax_s0 [get_keepers -nowarn {*u_hps_bridge|scan_diag_pmax_s0[*]}]
if { [get_collection_size $pmax_s0] == 0 } {
post_message -type warning "Ch443f SDC WARN: scan_diag_pmax_s0 matched 0 keepers (renamed / no LPDDR scanout) — stage-0 cut NOT applied"
} else {
set_false_path -to $pmax_s0
}
# Ch443f: coherent readiness GRAY code (axi next_fetch -> next_fetch_gray comb ->
# video nf_gray_s0[*]). Async into stage 0 -> cut setup+hold into nf_gray_s0; the
# s0->s1 MTBF leg stays timed. Gray changes ONE bit per increment, but bound the
# source->stage0 bit spread (max_skew + net_delay 2ns) so the lone multi-bit event
# (frame-restart reset to V_SOURCE_START, which fs_edge_v overrides on the video
# side anyway) cannot spread across more than one video sample. FATAL count guard.
set nfg_dst [get_keepers -nowarn {*u_lpddr_scan_lb|nf_gray_s0[*]}]
set nfg_src [get_keepers -nowarn {*u_lpddr_scan_lb|next_fetch[*]}]
if { [get_collection_size $nfg_dst] == 0 } {
post_message -type info "Ch443f SDC: next_fetch Gray readiness CDC inactive in this profile (0 stage-0 dst)"
} else {
if { [get_collection_size $nfg_src] == 0 } { error "Ch443f SDC FATAL: nf_gray_s0 present but u_lpddr_scan_lb|next_fetch[*] matched 0 keepers (renamed? Gray CDC source orphaned)" }
set_false_path -to $nfg_dst
set_max_skew -from $nfg_src -to $nfg_dst 2.0
set_net_delay -max -from $nfg_src -to $nfg_dst 2.0
post_message -type info "Ch443f SDC: next_fetch Gray readiness CDC async-in cut + 2ns max_skew/net_delay ([get_collection_size $nfg_src] src -> [get_collection_size $nfg_dst] stage-0 dst)"
}
set scan_diag_src [get_keepers -nowarn {*u_lpddr_scan_lb|diag_scan_y_q[*] *u_lpddr_scan_lb|diag_nf_v_q[*] *u_lpddr_scan_lb|diag_pmax_q[*] *u_lpddr_scan_lb|diag_vphase_q[*] *u_lpddr_scan_lb|diag_base_q *u_lpddr_scan_lb|diag_look_q *u_lpddr_scan_lb|diag_lv_q}]
set scan_diag_dst [get_keepers -nowarn {*u_hps_bridge|scan_diag_scan_y_q[*] *u_hps_bridge|scan_diag_nf_v_q[*] *u_hps_bridge|scan_diag_nf_s0_q[*] *u_hps_bridge|scan_diag_vphase_q[*] *u_hps_bridge|scan_diag_base_q *u_hps_bridge|scan_diag_look_q *u_hps_bridge|scan_diag_lv_q}]
set scan_diag_src_n [get_collection_size $scan_diag_src]
set scan_diag_dst_n [get_collection_size $scan_diag_dst]
if { $scan_diag_src_n == 0 } {
post_message -type info "Ch442 SDC: scanout diagnostic CDC inactive in this profile (0 src -> no LPDDR scanout)"
} else {
if { $scan_diag_src_n != 37 } { error "Ch442 SDC FATAL: scanout diag bundle source count $scan_diag_src_n != 37 (10+10+10+4+1+1+1; renamed/optimized? hold cut + net_delay would orphan)" }
if { $scan_diag_src_n != 31 } { error "Ch442/443f SDC FATAL: scanout diag bundle source count $scan_diag_src_n != 31 (10+10+4+4+1+1+1 = scan_y+nf_v+pmax+vphase+base+look+lv; renamed/optimized? hold cut + net_delay would orphan)" }
if { $scan_diag_dst_n == 0 } { error "Ch442 SDC FATAL: scanout diag bundle dest u_hps_bridge|scan_diag_*_q EMPTY (renamed? hold cut would orphan)" }
set_false_path -hold -from $scan_diag_src -to $scan_diag_dst
set_max_skew -from $scan_diag_src -to $scan_diag_dst 2.0