Ch443f: coherent Gray readiness CDC + qualified scanout underflow detector
Harden the LPDDR scanout underflow diagnostic (Codex direction). Keeps the Ch443e 4-buffer + lead-2 fix; adds no 5th buffer. RTL (gs_lpddr_scanout_lb): - Replace the raw-binary next_fetch readiness sync with a reset-aware GRAY code. next_fetch is monotonic between frames, so one Gray bit changes per increment; the 2-FF-synced + decoded nf_v is always a real prior frontier (monotone, burst-safe), never a torn multi-bit combination. (A plain toggle-per-change handshake dropped bursts when two increments landed in one sync window; that is why the earlier attempt under-read nf_v and false-tripped.) fs_edge_v overrides the lone multi-bit reset transient. - Qualify the underflow: only a miss persisting >= QUAL_CYCLES (4) sets sticky underflow. uf_pmax_q records the longest streak and uf_qual_q whether any qualified, so a host can distinguish a 1-cycle CDC lag from a real late row. - Atomic snapshot: scan_y/nf_v/pmax/causes/vphase/line_valid all latched the same video cycle on the first qualified miss. ABI: 0x120 adds [15:12]=live pmax (2-FF synced via scan_diag_pmax_i). 0x124 [29:20] now carries pmax-at-capture (was nf_s0). Bridge dst reg kept 10-bit. SDC: scanout diag bundle source count 37 -> 31 (nf_s0[10] -> pmax[4]); new async-in cut + max_skew/net_delay for the next_fetch Gray CDC; stage-0 cut for the live pmax sync. Tests: new tb_gs_scanout_cdc_qual (async-clock focused: no false event from the readiness transition or ordinary sync latency; sub-QUAL transient does not qualify; genuine late row qualifies with a self-consistent atomic snapshot; frame reset + mod-4 reuse re-arm the detector). tb_gs_scanout_diag updated for the pmax field. Tie off scan_diag_pmax_i (+ pre-existing clut_* gap from the fog baseline) in the four .* bridge/integration TBs. Regressions green: scanout (cdc_qual, binomial_lookahead, diag, restart, lpddr_scanout_lb x3), regbuf (r/aw/w), bridge + 3 pad integration TBs, and the f52 top-level golden FB (Z 0/307200, COLOR 0/245760 mismatch, drops=0). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
@@ -88,9 +88,10 @@ module gs_lpddr_scanout_lb #(
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// Splits the single top-level scan-error bit into independently observable causes and captures
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// the FIRST raw-underflow event of each video-source-enabled session as a bundled-data snapshot.
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output logic diag_rderr_nz, // LIVE (rd_errs != 0), reduced+registered in the axi_clk domain (single bit; the raw counter never crosses)
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output logic diag_valid, // first raw-underflow captured; held stable until video source disabled (!enable)
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output logic [29:0] diag_first, // SNAPSHOT, stable while diag_valid: {nf_s0[9:0], nf_v[9:0], scan_y[9:0]}
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output logic diag_valid, // Ch443f: first QUALIFIED (persistent) miss captured this frame; held until !enable
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output logic [29:0] diag_first, // SNAPSHOT, stable while diag_valid: {pmax_at_capture[9:0], nf_v[9:0], scan_y[9:0]}
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output logic [6:0] diag_stat, // SNAPSHOT, stable while diag_valid: {vphase[3:0], line_valid, lookahead_cause, base_cause}
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output logic [3:0] diag_pmax, // Ch443f: LIVE per-frame max consecutive-miss streak (transient vs real classification)
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// ---- AXI4 read channel to the EMIF user port (axi_clk, 256-bit) ----
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output logic [29:0] araddr,
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@@ -672,8 +673,22 @@ module gs_lpddr_scanout_lb #(
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logic [2:0] fs_sync_e;
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wire fs_edge_e = fs_sync_e[1] && !fs_sync_e[2]; // RISING edge only: one prefetch restart per frame_start pulse
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logic [$clog2(N_ROWS):0] disp_row_s0, disp_row_limit_e;
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logic [$clog2(N_ROWS):0] next_fetch; // next row to load (0..N_ROWS)
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localparam int NFW = $clog2(N_ROWS)+1;
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logic [NFW-1:0] next_fetch; // next row to load (0..N_ROWS)
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logic [1:0] next_fetch_buf;
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// Ch443f (Codex) — COHERENT readiness transfer via a reset-aware GRAY-CODED counter.
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// next_fetch is monotonic between frame boundaries (it only ever +1 on a row commit), so its
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// Gray code changes exactly ONE bit per increment. Crossing the Gray word through a 2-FF
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// synchronizer therefore never yields a bogus intermediate — the decoded value is always some
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// real prior next_fetch, monotone, never a torn multi-bit binary combination, and it does NOT
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// drop bursts (a plain toggle-per-change handshake cancels when two increments land inside one
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// sync window; Gray does not). The only multi-bit jump is the frame-restart reset to
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// V_SOURCE_START, and that transient is overridden on the video side by fs_edge_v (reset-aware).
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wire [NFW-1:0] next_fetch_gray = next_fetch ^ (next_fetch >> 1);
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function automatic [NFW-1:0] gray2bin(input [NFW-1:0] g);
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gray2bin[NFW-1] = g[NFW-1];
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for (int i = NFW-2; i >= 0; i--) gray2bin[i] = gray2bin[i+1] ^ g[i];
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endfunction
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typedef enum logic [1:0] { L_IDLE, L_AR, L_R, L_C } lstate_t;
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lstate_t lst;
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logic [$clog2(N_ROWS):0] cur_row;
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@@ -826,34 +841,29 @@ module gs_lpddr_scanout_lb #(
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end
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end
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// underflow (sticky, video domain): an in-window pixel for line pixel_y is read
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// before that row was prefetched. The axi side loads rows 0..next_fetch-1, so row
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// pixel_y is ready iff pixel_y < next_fetch. next_fetch crosses axi->video synced
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// (slowly-changing; a 1-off transient is harmless). Resets on vsync.
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logic [$clog2(N_ROWS):0] nf_s0, nf_v;
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// =============== Ch443f coherent, QUALIFIED underflow detector (video domain) ===============
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// COHERENT readiness: next_fetch crosses as a reset-aware GRAY code (next_fetch_gray), 2-FF
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// synced and decoded here, NOT as a raw multi-bit binary bus. Because next_fetch is monotonic
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// between frames, one Gray bit changes per increment, so the synchronized+decoded nf_v is always
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// a real prior frontier value (monotone, never a torn combination) and never drops burst
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// increments. Reset-aware: fs_edge_v realigns nf_v to V_SOURCE_START at the frame boundary,
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// overriding the one multi-bit Gray transient (the restart jump to V_SOURCE_START).
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logic [NFW-1:0] nf_gray_s0, nf_gray_s1; // 2-FF sync of the axi-domain Gray code
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wire [NFW-1:0] nf_v_sync = gray2bin(nf_gray_s1);
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logic [NFW-1:0] nf_v;
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logic underflow_v;
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always_ff @(posedge video_clk) begin
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nf_s0 <= next_fetch; nf_v <= nf_s0;
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if (!enable || fs_edge_v) underflow_v <= 1'b0;
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else if (in_window && (scan_y < ($clog2(N_ROWS)+1)'(N_ROWS)) &&
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((scan_y >= nf_v) ||
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((BINOMIAL_3X3_FILTER ||
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(V_LINEAR_FILTER && (stretch_vphase_q != 4'd0))) &&
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(scan_y + 1'b1 < ($clog2(N_ROWS)+1)'(N_ROWS)) &&
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(scan_y + 1'b1 >= nf_v))))
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underflow_v <= 1'b1;
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end
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assign underflow = underflow_v;
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// ================= Ch442 A+B first-failure diagnostic (read-only) =================
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// Re-express the EXACT raw-underflow predicate (identical boolean to the sticky latch
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// above) as combinational wires so the capture can name WHICH sub-cause fired. These
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// wires and the registers below drive ONLY the diag_* outputs — never the fetch FSM,
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// the pixel path, arbitration, or underflow_v. The existing latch block is untouched.
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// NOTE the `!fs_edge_v` term: the sticky latch gives frame-start CLEAR priority
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// (`if (!enable || fs_edge_v) ... else if (predicate)`), so on an fs_edge_v cycle it
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// never sets. Mirror that exactly here or the diagnostic could capture a frame-start
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// coincident miss the real latch suppresses.
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// QUALIFICATION: the Gray transfer removes incoherent transitions but NOT the normal ~2-clock
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// sync lag. A genuine row-miss holds for the whole output line (many video cycles); an nf_v sync
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// lag clears within a few cycles as nf_v catches up. Only a miss that PERSISTS >= QUAL_CYCLES is
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// treated as real (-> sticky underflow / 0x02C bit5). uf_pmax_q records the longest miss streak
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// this frame and uf_qual_q whether any streak qualified, so the host can DISTINGUISH a 1-cycle
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// CDC lag (small pmax, uf_qual=0) from an actual late row (pmax>=QUAL, uf_qual=1).
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localparam int QUAL_CYCLES = 4;
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logic [3:0] uf_persist_q, uf_pmax_q;
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logic uf_qual_q;
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// Raw miss predicate (combinational, on the coherent nf_v). base = current row not loaded;
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// lookahead = the binomial/linear filter's r+1 row not loaded. !fs_edge_v gives the frame-start
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// clear priority (a miss on an fs_edge_v cycle is suppressed, matching the reset above).
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wire uf_in_range = enable && !fs_edge_v && in_window && (scan_y < ($clog2(N_ROWS)+1)'(N_ROWS));
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wire uf_base_cond = uf_in_range && (scan_y >= nf_v);
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wire uf_look_cond = uf_in_range &&
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@@ -862,38 +872,58 @@ module gs_lpddr_scanout_lb #(
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(scan_y + 1'b1 < ($clog2(N_ROWS)+1)'(N_ROWS)) &&
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(scan_y + 1'b1 >= nf_v);
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wire raw_uf_cond = uf_base_cond || uf_look_cond;
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always_ff @(posedge video_clk) begin
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nf_gray_s0 <= next_fetch_gray; nf_gray_s1 <= nf_gray_s0; // 2-FF Gray sync
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if (!enable || fs_edge_v) begin
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nf_v <= ($clog2(N_ROWS)+1)'(V_SOURCE_START);
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underflow_v <= 1'b0; uf_persist_q <= 4'd0; uf_pmax_q <= 4'd0; uf_qual_q <= 1'b0;
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end else begin
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nf_v <= nf_v_sync; // coherent decoded frontier (monotone, burst-safe)
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if (raw_uf_cond) begin
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uf_persist_q <= (uf_persist_q == 4'hF) ? 4'hF : uf_persist_q + 4'd1;
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if ((uf_persist_q + 4'd1) > uf_pmax_q) uf_pmax_q <= uf_persist_q + 4'd1;
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end else begin
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uf_persist_q <= 4'd0;
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end
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if (uf_persist_q >= 4'(QUAL_CYCLES)) begin underflow_v <= 1'b1; uf_qual_q <= 1'b1; end
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end
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end
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assign underflow = underflow_v; // QUALIFIED (persistent) miss only
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// ================= Ch442 A+B first-failure diagnostic (read-only) =================
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// The raw_uf_cond wires above name WHICH sub-cause fired. The registers below drive ONLY
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// the diag_* outputs — never the fetch FSM, pixel path, arbitration, or underflow_v.
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// line_valid is axi_clk-domain; 2-FF into video_clk for coherent capture.
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logic [1:0] line_valid_vsync;
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// First-failure snapshot (video_clk). Ch443c (Codex): PER-FRAME — diag_valid clears on
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// fs_edge_v as well as !enable, mirroring underflow_v, then records the first raw miss of
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// the NEW frame. This discards the pre-display WARM-UP capture: the line-buffer reader is
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// enabled by video_src_emif immediately, but the HDMI mux only switches to it at the next
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// vsync, so the very first post-enable miss is not an HDMI-visible one. Clearing per frame
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// makes the snapshot report the first miss AFTER the real frame boundary. The bundled
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// snapshot ({nf_s0,nf_v,scan_y} + cause/line_valid/vphase) stays stable within a frame,
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// so the bridge can transfer it coherently with a single synchronized valid.
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// (* preserve *): keep these capture regs as named keepers so the SDC bundled-data
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// hold-false/max-skew/net-delay constraint can bind to them (they must not be merged).
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// Per-frame snapshot (video_clk). Ch443c: cleared on fs_edge_v (discards the pre-display
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// warm-up). Ch443f: captures the first QUALIFIED miss (uf_persist_q >= QUAL) — a miss that
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// outlived the sync transient — so diag_valid means a REAL (non-CDC-lag) miss occurred this
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// frame; a transient-only frame leaves diag_valid=0 but a nonzero live uf_pmax. The bundled
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// snapshot {pmax_at_capture, nf_v, scan_y} + {vphase, line_valid, lookahead, base} is stable
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// within a frame so the bridge transfers it coherently with one synchronized valid; the live
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// diag_pmax (per-frame max streak) is exposed separately so a transient (small) is visible.
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// (* preserve *): keep these capture regs as named keepers for the SDC bundled-data constraint.
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(* preserve *) logic diag_valid_q, diag_base_q, diag_look_q, diag_lv_q;
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(* preserve *) logic [3:0] diag_vphase_q;
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(* preserve *) logic [$clog2(N_ROWS):0] diag_scan_y_q, diag_nf_v_q, diag_nf_s0_q;
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(* preserve *) logic [3:0] diag_vphase_q, diag_pmax_q;
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(* preserve *) logic [$clog2(N_ROWS):0] diag_scan_y_q, diag_nf_v_q;
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always_ff @(posedge video_clk) begin
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line_valid_vsync <= {line_valid_vsync[0], line_valid};
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if (!enable || fs_edge_v) begin
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diag_valid_q <= 1'b0; // Ch443c: per-frame clear (discards pre-display warm-up capture)
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end else if (!diag_valid_q && raw_uf_cond) begin
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diag_valid_q <= 1'b1;
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diag_valid_q <= 1'b0; // per-frame clear
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end else if (!diag_valid_q && (uf_persist_q >= 4'(QUAL_CYCLES))) begin
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diag_valid_q <= 1'b1; // capture the first QUALIFIED (persistent, real) miss
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diag_base_q <= uf_base_cond;
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diag_look_q <= uf_look_cond;
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diag_lv_q <= line_valid_vsync[1];
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diag_vphase_q <= stretch_vphase_q;
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diag_scan_y_q <= scan_y;
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diag_nf_v_q <= nf_v;
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diag_nf_s0_q <= nf_s0;
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diag_pmax_q <= uf_pmax_q; // persistence of this miss at qualification
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end
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end
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assign diag_valid = diag_valid_q;
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assign diag_first = {10'(diag_nf_s0_q), 10'(diag_nf_v_q), 10'(diag_scan_y_q)};
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assign diag_pmax = uf_pmax_q; // LIVE per-frame max streak (transient observability)
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assign diag_first = {6'd0, diag_pmax_q, 10'(diag_nf_v_q), 10'(diag_scan_y_q)};
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assign diag_stat = {diag_vphase_q, diag_lv_q, diag_look_q, diag_base_q};
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endmodule
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@@ -339,6 +339,7 @@ module ps2_hps_bridge (
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input logic scan_diag_valid_i, // first-failure captured, held to !enable (video_clk level; bundled-data valid)
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input logic [29:0] scan_diag_first_i, // SNAPSHOT {nf_s0[9:0],nf_v[9:0],scan_y[9:0]} (stable while valid -> 0x124)
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input logic [6:0] scan_diag_stat_i, // SNAPSHOT {vphase[3:0],line_valid,lookahead,base} (stable while valid -> 0x120)
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input logic [3:0] scan_diag_pmax_i, // Ch443f LIVE per-frame max miss streak (2-FF synced -> 0x120[15:12])
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// ---- Ch322: LPDDR write-probe (HPS stages texture words) + texture-cache fill ----
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// 0x040 LPDDR_WRADDR (W): set the LPDDR byte address (auto-increments +4 per data write).
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@@ -657,6 +658,7 @@ module ps2_hps_bridge (
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logic [1:0] scan_diag_uf_sync;
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(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED", dont_merge, preserve *)
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logic [1:0] scan_diag_rderr_sync;
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logic [3:0] scan_diag_pmax_s0, scan_diag_pmax_s1; // Ch443f — 2-FF sync of the live pmax magnitude
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(* altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION FORCED", dont_merge, preserve *)
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logic [2:0] scan_diag_valid_sync; // 3-deep so the RISING synced edge latches the snapshot
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logic scan_diag_snap_valid_q; // DEST valid: set WITH payload capture, cleared on synced source-valid deassert
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@@ -954,7 +956,10 @@ module ps2_hps_bridge (
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case (addr[4:2])
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// 0x120 SCAN_DIAG_STATUS: [0]valid [1]underflow [2]read-error-nonzero
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// [3]cause_base(scan_y>=nf_v) [4]cause_lookahead [5]line_valid [11:8]filter vphase.
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3'h0: reg_read = {20'd0, scan_diag_vphase_q, 2'd0,
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// Ch443f: [15:12] = live per-frame max miss streak (pmax); [0] valid now = a
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// QUALIFIED (persistent) miss captured. Classify: valid=0 + small pmax => CDC-lag
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// transient; valid=1 / large pmax => real starvation.
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3'h0: reg_read = {16'd0, scan_diag_pmax_s1, scan_diag_vphase_q, 2'd0,
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scan_diag_lv_q, scan_diag_look_q, scan_diag_base_q,
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scan_diag_rderr_sync[1], scan_diag_uf_sync[1], scan_diag_snap_valid_q};
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// 0x124 SCAN_DIAG_FIRST: [9:0]scan_y [19:10]nf_v [29:20]nf_s0.
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@@ -1122,6 +1127,8 @@ module ps2_hps_bridge (
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lpddr_scan_err_sync <= 2'b00;
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scan_diag_uf_sync <= 2'b00;
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scan_diag_rderr_sync <= 2'b00;
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scan_diag_pmax_s0 <= 4'd0;
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scan_diag_pmax_s1 <= 4'd0;
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scan_diag_valid_sync <= 3'b000;
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scan_diag_snap_valid_q<= 1'b0;
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scan_diag_base_q <= 1'b0;
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@@ -1167,6 +1174,8 @@ module ps2_hps_bridge (
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// Ch442 — independent 2-FF syncs of the two split live flags (never the raw counter).
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scan_diag_uf_sync <= {scan_diag_uf_sync[0], scan_diag_uf_i};
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scan_diag_rderr_sync <= {scan_diag_rderr_sync[0], scan_diag_rderr_nz_i};
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scan_diag_pmax_s0 <= scan_diag_pmax_i; // Ch443f — 2-FF sync of the small live magnitude
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scan_diag_pmax_s1 <= scan_diag_pmax_s0;
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// Bundled-data capture: sync the valid, and on its RISING synced edge the snapshot
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// (held stable in the video domain since first-failure) is quiescent -> latch coherently.
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scan_diag_valid_sync <= {scan_diag_valid_sync[1:0], scan_diag_valid_i};
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@@ -527,6 +527,7 @@ module de25_nano_psmct32_raster_demo_top (
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wire scan_diag_uf_w, scan_diag_rderr_nz_w, scan_diag_valid_w;
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wire [29:0] scan_diag_first_w;
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wire [6:0] scan_diag_stat_w;
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wire [3:0] scan_diag_pmax_w; // Ch443f — live per-frame max miss streak
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// Ch320/Ch321 — LPDDR scanout frame-cache size: 256 beats (8 KiB, 64x64) by default,
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// 1024 beats (32 KiB, 128x128) for the Ch321 larger-frame demo.
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`ifdef GS_TILE_LPDDR128_DEMO
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@@ -2681,7 +2682,7 @@ module de25_nano_psmct32_raster_demo_top (
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.r(lb_r_w), .g(lb_g_w), .b(lb_b_w),
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.line_valid(lb_valid_w), .underflow(lb_underflow_w), .rd_errs(lb_rd_errs_w),
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.diag_rderr_nz(scan_diag_rderr_nz_w), .diag_valid(scan_diag_valid_w),
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.diag_first(scan_diag_first_w), .diag_stat(scan_diag_stat_w),
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.diag_first(scan_diag_first_w), .diag_stat(scan_diag_stat_w), .diag_pmax(scan_diag_pmax_w),
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.araddr(lb_araddr), .arburst(lb_arburst), .arid(lb_arid),
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.arlen(lb_arlen), .arsize(lb_arsize), .arvalid(lb_arvalid),
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.arready(scan_ar_arready & scanout_lb_eff),
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@@ -2846,7 +2847,7 @@ module de25_nano_psmct32_raster_demo_top (
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assign scan_r_w=8'd0; assign scan_g_w=8'd0; assign scan_b_w=8'd0;
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assign scan_cache_valid_w=1'b0; assign scan_err_w=1'b0; // no LPDDR scanout
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assign scan_diag_uf_w=1'b0; assign scan_diag_rderr_nz_w=1'b0; assign scan_diag_valid_w=1'b0;
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assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; // Ch442 diag tie-off (no LPDDR scanout)
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assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; assign scan_diag_pmax_w=4'd0; // Ch442/443f diag tie-off (no LPDDR scanout)
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assign tex_fill_done_w=1'b0; assign tex_fill_beats_w=32'd0; assign tex_fill_bytes_w=32'd0;
|
||||
assign tex_rd_errs_w=32'd0; assign tex_fill_crc_w=32'd0;
|
||||
assign lpddr_wr_busy_w=1'b0; assign lpddr_wr_done_w=1'b0; assign lpddr_wr_bresp_err_w=32'd0;
|
||||
@@ -2868,7 +2869,7 @@ module de25_nano_psmct32_raster_demo_top (
|
||||
assign scan_r_w=8'd0; assign scan_g_w=8'd0; assign scan_b_w=8'd0;
|
||||
assign scan_cache_valid_w=1'b0; assign scan_err_w=1'b0; // no LPDDR scanout
|
||||
assign scan_diag_uf_w=1'b0; assign scan_diag_rderr_nz_w=1'b0; assign scan_diag_valid_w=1'b0;
|
||||
assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; // Ch442 diag tie-off (no LPDDR scanout)
|
||||
assign scan_diag_first_w=30'd0; assign scan_diag_stat_w=7'd0; assign scan_diag_pmax_w=4'd0; // Ch442/443f diag tie-off (no LPDDR scanout)
|
||||
assign tex_fill_done_w=1'b0; assign tex_fill_beats_w=32'd0; assign tex_fill_bytes_w=32'd0;
|
||||
assign tex_rd_errs_w=32'd0; assign tex_fill_crc_w=32'd0;
|
||||
assign lpddr_wr_busy_w=1'b0; assign lpddr_wr_done_w=1'b0; assign lpddr_wr_bresp_err_w=32'd0;
|
||||
@@ -3139,6 +3140,7 @@ module de25_nano_psmct32_raster_demo_top (
|
||||
.scan_diag_valid_i (scan_diag_valid_w),
|
||||
.scan_diag_first_i (scan_diag_first_w),
|
||||
.scan_diag_stat_i (scan_diag_stat_w),
|
||||
.scan_diag_pmax_i (scan_diag_pmax_w),
|
||||
// Ch322 — LPDDR write-probe (HPS stages texture words) + texture-cache fill.
|
||||
.lpddr_wr_addr_o (lpddr_wr_addr_w),
|
||||
.lpddr_wr_data_o (lpddr_wr_data_w),
|
||||
|
||||
Reference in New Issue
Block a user