# Ch434 epoch descriptor table (22 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 22 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d0.mem 35 3 0 sh3_zsrt139l3d0_pal.mem 0x00000000
1 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d1.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
2 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d2.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
3 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d3.mem 62 6 1 sh3_zsrt139l3d0_pal.mem 0x00000000
4 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d4.mem 116 12 1 sh3_zsrt139l3d0_pal.mem 0x00000000
5 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d5.mem 143 15 1 sh3_zsrt139l3d0_pal.mem 0x00000000
6 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d6.mem 62 6 1 sh3_zsrt139l3d0_pal.mem 0x00000000
7 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d7.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
8 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d8.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
9 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d9.mem 35 3 1 sh3_zsrt139l3d0_pal.mem 0x00000000
10 195957 8192 480 sh3_zsrt139l3d0_tex_lpddr.mem 0x200000 262144 0xdfb3b054 feeder_sh3_zsrt139l3d10.mem 17 1 1 sh3_zsrt139l3d0_pal.mem 0x00000000
11 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d11.mem 35 3 0 sh3_zsrt139l3d0_pal.mem 0x00000000
12 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d12.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
13 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d13.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
14 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d14.mem 62 6 1 sh3_zsrt139l3d0_pal.mem 0x00000000
15 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d15.mem 116 12 1 sh3_zsrt139l3d0_pal.mem 0x00000000
16 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d16.mem 143 15 1 sh3_zsrt139l3d0_pal.mem 0x00000000
17 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d17.mem 62 6 1 sh3_zsrt139l3d0_pal.mem 0x00000000
18 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d18.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
19 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d19.mem 44 4 1 sh3_zsrt139l3d0_pal.mem 0x00000000
20 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d20.mem 35 3 1 sh3_zsrt139l3d0_pal.mem 0x00000000
21 195973 8192 480 sh3_zsrt139l3d11_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l3d21.mem 17 1 1 sh3_zsrt139l3d0_pal.mem 0x00000000
