# Ch427 epoch descriptor table (129 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 129 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f270.mem 467 51 0 sh3_zsrt139f270_pal.mem 0x158afe76
1 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f271.mem 503 55 1 sh3_zsrt139f270_pal.mem 0x158afe76
2 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f272.mem 503 55 1 sh3_zsrt139f270_pal.mem 0x158afe76
3 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f273.mem 485 53 1 sh3_zsrt139f270_pal.mem 0x158afe76
4 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f274.mem 512 56 1 sh3_zsrt139f270_pal.mem 0x158afe76
5 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f275.mem 485 53 1 sh3_zsrt139f270_pal.mem 0x158afe76
6 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f276.mem 449 49 1 sh3_zsrt139f270_pal.mem 0x158afe76
7 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f277.mem 521 57 1 sh3_zsrt139f270_pal.mem 0x158afe76
8 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f278.mem 485 53 1 sh3_zsrt139f270_pal.mem 0x158afe76
9 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f279.mem 512 56 1 sh3_zsrt139f270_pal.mem 0x158afe76
10 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2710.mem 467 51 1 sh3_zsrt139f270_pal.mem 0x158afe76
11 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2711.mem 494 54 1 sh3_zsrt139f270_pal.mem 0x158afe76
12 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2712.mem 530 58 1 sh3_zsrt139f270_pal.mem 0x158afe76
13 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2713.mem 539 59 1 sh3_zsrt139f270_pal.mem 0x158afe76
14 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2714.mem 512 56 1 sh3_zsrt139f270_pal.mem 0x158afe76
15 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2715.mem 458 50 1 sh3_zsrt139f270_pal.mem 0x158afe76
16 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2716.mem 476 52 1 sh3_zsrt139f270_pal.mem 0x158afe76
17 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2717.mem 458 50 1 sh3_zsrt139f270_pal.mem 0x158afe76
18 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2718.mem 440 48 1 sh3_zsrt139f270_pal.mem 0x158afe76
19 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2719.mem 440 48 1 sh3_zsrt139f270_pal.mem 0x158afe76
20 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2720.mem 494 54 1 sh3_zsrt139f270_pal.mem 0x158afe76
21 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2721.mem 449 49 1 sh3_zsrt139f270_pal.mem 0x158afe76
22 196494 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2722.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
23 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2723.mem 404 44 1 sh3_zsrt139f270_pal.mem 0x158afe76
24 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2724.mem 440 48 1 sh3_zsrt139f270_pal.mem 0x158afe76
25 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2725.mem 413 45 1 sh3_zsrt139f270_pal.mem 0x158afe76
26 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2726.mem 395 43 1 sh3_zsrt139f270_pal.mem 0x158afe76
27 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2727.mem 377 41 1 sh3_zsrt139f270_pal.mem 0x158afe76
28 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2728.mem 458 50 1 sh3_zsrt139f270_pal.mem 0x158afe76
29 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2729.mem 467 51 1 sh3_zsrt139f270_pal.mem 0x158afe76
30 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2730.mem 395 43 1 sh3_zsrt139f270_pal.mem 0x158afe76
31 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2731.mem 422 46 1 sh3_zsrt139f270_pal.mem 0x158afe76
32 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2732.mem 449 49 1 sh3_zsrt139f270_pal.mem 0x158afe76
33 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2733.mem 440 48 1 sh3_zsrt139f270_pal.mem 0x158afe76
34 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2734.mem 404 44 1 sh3_zsrt139f270_pal.mem 0x158afe76
35 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2735.mem 413 45 1 sh3_zsrt139f270_pal.mem 0x158afe76
36 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2736.mem 395 43 1 sh3_zsrt139f270_pal.mem 0x158afe76
37 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2737.mem 539 59 1 sh3_zsrt139f270_pal.mem 0x158afe76
38 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2738.mem 602 66 1 sh3_zsrt139f270_pal.mem 0x158afe76
39 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2739.mem 413 45 1 sh3_zsrt139f270_pal.mem 0x158afe76
40 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2740.mem 476 52 1 sh3_zsrt139f270_pal.mem 0x158afe76
41 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2741.mem 377 41 1 sh3_zsrt139f270_pal.mem 0x158afe76
42 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2742.mem 323 35 1 sh3_zsrt139f270_pal.mem 0x158afe76
43 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2743.mem 413 45 1 sh3_zsrt139f270_pal.mem 0x158afe76
44 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2744.mem 404 44 1 sh3_zsrt139f270_pal.mem 0x158afe76
45 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2745.mem 395 43 1 sh3_zsrt139f270_pal.mem 0x158afe76
46 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2746.mem 431 47 1 sh3_zsrt139f270_pal.mem 0x158afe76
47 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2747.mem 395 43 1 sh3_zsrt139f270_pal.mem 0x158afe76
48 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2748.mem 710 78 1 sh3_zsrt139f270_pal.mem 0x158afe76
49 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2749.mem 575 63 1 sh3_zsrt139f270_pal.mem 0x158afe76
50 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2750.mem 602 66 1 sh3_zsrt139f270_pal.mem 0x158afe76
51 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2751.mem 512 56 1 sh3_zsrt139f270_pal.mem 0x158afe76
52 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2752.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
53 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2753.mem 395 43 1 sh3_zsrt139f270_pal.mem 0x158afe76
54 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2754.mem 422 46 1 sh3_zsrt139f270_pal.mem 0x158afe76
55 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2755.mem 404 44 1 sh3_zsrt139f270_pal.mem 0x158afe76
56 196868 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2756.mem 449 49 1 sh3_zsrt139f270_pal.mem 0x158afe76
57 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2757.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
58 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2758.mem 332 36 1 sh3_zsrt139f270_pal.mem 0x158afe76
59 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2759.mem 350 38 1 sh3_zsrt139f270_pal.mem 0x158afe76
60 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2760.mem 413 45 1 sh3_zsrt139f270_pal.mem 0x158afe76
61 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2761.mem 467 51 1 sh3_zsrt139f270_pal.mem 0x158afe76
62 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2762.mem 368 40 1 sh3_zsrt139f270_pal.mem 0x158afe76
63 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2763.mem 422 46 1 sh3_zsrt139f270_pal.mem 0x158afe76
64 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2764.mem 449 49 1 sh3_zsrt139f270_pal.mem 0x158afe76
65 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2765.mem 377 41 1 sh3_zsrt139f270_pal.mem 0x158afe76
66 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2766.mem 494 54 1 sh3_zsrt139f270_pal.mem 0x158afe76
67 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2767.mem 539 59 1 sh3_zsrt139f270_pal.mem 0x158afe76
68 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2768.mem 395 43 1 sh3_zsrt139f270_pal.mem 0x158afe76
69 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2769.mem 692 76 1 sh3_zsrt139f270_pal.mem 0x158afe76
70 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2770.mem 665 73 1 sh3_zsrt139f270_pal.mem 0x158afe76
71 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2771.mem 512 56 1 sh3_zsrt139f270_pal.mem 0x158afe76
72 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2772.mem 620 68 1 sh3_zsrt139f270_pal.mem 0x158afe76
73 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2773.mem 341 37 1 sh3_zsrt139f270_pal.mem 0x158afe76
74 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2774.mem 314 34 1 sh3_zsrt139f270_pal.mem 0x158afe76
75 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2775.mem 449 49 1 sh3_zsrt139f270_pal.mem 0x158afe76
76 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2776.mem 503 55 1 sh3_zsrt139f270_pal.mem 0x158afe76
77 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2777.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
78 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2778.mem 458 50 1 sh3_zsrt139f270_pal.mem 0x158afe76
79 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2779.mem 584 64 1 sh3_zsrt139f270_pal.mem 0x158afe76
80 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2780.mem 332 36 1 sh3_zsrt139f270_pal.mem 0x158afe76
81 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2781.mem 314 34 1 sh3_zsrt139f270_pal.mem 0x158afe76
82 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2782.mem 539 59 1 sh3_zsrt139f270_pal.mem 0x158afe76
83 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2783.mem 278 30 1 sh3_zsrt139f270_pal.mem 0x158afe76
84 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2784.mem 314 34 1 sh3_zsrt139f270_pal.mem 0x158afe76
85 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2785.mem 278 30 1 sh3_zsrt139f270_pal.mem 0x158afe76
86 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2786.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
87 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2787.mem 251 27 1 sh3_zsrt139f270_pal.mem 0x158afe76
88 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2788.mem 476 52 1 sh3_zsrt139f270_pal.mem 0x158afe76
89 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2789.mem 458 50 1 sh3_zsrt139f270_pal.mem 0x158afe76
90 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2790.mem 368 40 1 sh3_zsrt139f270_pal.mem 0x158afe76
91 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2791.mem 269 29 1 sh3_zsrt139f270_pal.mem 0x158afe76
92 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2792.mem 287 31 1 sh3_zsrt139f270_pal.mem 0x158afe76
93 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2793.mem 350 38 1 sh3_zsrt139f270_pal.mem 0x158afe76
94 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2794.mem 233 25 1 sh3_zsrt139f270_pal.mem 0x158afe76
95 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2795.mem 467 51 1 sh3_zsrt139f270_pal.mem 0x158afe76
96 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2796.mem 242 26 1 sh3_zsrt139f270_pal.mem 0x158afe76
97 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2797.mem 323 35 1 sh3_zsrt139f270_pal.mem 0x158afe76
98 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2798.mem 647 71 1 sh3_zsrt139f270_pal.mem 0x158afe76
99 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f2799.mem 332 36 1 sh3_zsrt139f270_pal.mem 0x158afe76
100 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27100.mem 476 52 1 sh3_zsrt139f270_pal.mem 0x158afe76
101 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27101.mem 368 40 1 sh3_zsrt139f270_pal.mem 0x158afe76
102 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27102.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
103 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27103.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
104 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27104.mem 611 67 1 sh3_zsrt139f270_pal.mem 0x158afe76
105 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27105.mem 359 39 1 sh3_zsrt139f270_pal.mem 0x158afe76
106 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27106.mem 458 50 1 sh3_zsrt139f270_pal.mem 0x158afe76
107 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27107.mem 386 42 1 sh3_zsrt139f270_pal.mem 0x158afe76
108 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27108.mem 404 44 1 sh3_zsrt139f270_pal.mem 0x158afe76
109 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27109.mem 224 24 1 sh3_zsrt139f270_pal.mem 0x158afe76
110 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27110.mem 404 44 1 sh3_zsrt139f270_pal.mem 0x158afe76
111 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27111.mem 440 48 1 sh3_zsrt139f270_pal.mem 0x158afe76
112 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27112.mem 251 27 1 sh3_zsrt139f270_pal.mem 0x158afe76
113 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27113.mem 269 29 1 sh3_zsrt139f270_pal.mem 0x158afe76
114 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27114.mem 224 24 1 sh3_zsrt139f270_pal.mem 0x158afe76
115 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27115.mem 368 40 1 sh3_zsrt139f270_pal.mem 0x158afe76
116 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27116.mem 278 30 1 sh3_zsrt139f270_pal.mem 0x158afe76
117 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27117.mem 341 37 1 sh3_zsrt139f270_pal.mem 0x158afe76
118 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27118.mem 314 34 1 sh3_zsrt139f270_pal.mem 0x158afe76
119 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27119.mem 278 30 1 sh3_zsrt139f270_pal.mem 0x158afe76
120 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27120.mem 269 29 1 sh3_zsrt139f270_pal.mem 0x158afe76
121 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27121.mem 296 32 1 sh3_zsrt139f270_pal.mem 0x158afe76
122 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27122.mem 242 26 1 sh3_zsrt139f270_pal.mem 0x158afe76
123 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27123.mem 251 27 1 sh3_zsrt139f270_pal.mem 0x158afe76
124 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27124.mem 161 17 1 sh3_zsrt139f270_pal.mem 0x158afe76
125 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27125.mem 296 32 1 sh3_zsrt139f270_pal.mem 0x158afe76
126 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27126.mem 251 27 1 sh3_zsrt139f270_pal.mem 0x158afe76
127 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27127.mem 251 27 1 sh3_zsrt139f270_pal.mem 0x158afe76
128 197327 10240 480 sh3_zsrt139f270_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139f27128.mem 134 14 1 sh3_zsrt139f270_pal.mem 0x158afe76
