# Ch384 epoch descriptor table (16 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 16 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 10123 2048 496 sh3_zsrte430_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte430.mem 1843 204 0 sh3_zsrte430_pal.mem 0x3bfe8722
1 10762 2048 496 sh3_zsrte431_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte431.mem 1843 204 1 sh3_zsrte431_pal.mem 0x3bfe8722
2 11401 2048 496 sh3_zsrte432_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte432.mem 817 90 1 sh3_zsrte432_pal.mem 0x3bfe8722
3 11698 2048 500 sh3_zsrte433_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte433.mem 1285 142 0 sh3_zsrte433_pal.mem 0x2c5b7e28
4 12646 2048 500 sh3_zsrte434_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte434.mem 1591 176 1 sh3_zsrte434_pal.mem 0x2c5b7e28
5 13201 2048 500 sh3_zsrte435_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte435.mem 1069 118 1 sh3_zsrte435_pal.mem 0x2c5b7e28
6 13582 2048 500 sh3_zsrte436_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte436.mem 205 22 1 sh3_zsrte436_pal.mem 0x2c5b7e28
7 93634 3072 504 sh3_zsrte437_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte437.mem 619 68 0 sh3_zsrte437_pal.mem 0x47097d4c
8 93847 3072 504 sh3_zsrte438_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte438.mem 1591 176 1 sh3_zsrte438_pal.mem 0x47097d4c
9 94402 3072 504 sh3_zsrte439_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte439.mem 1843 204 1 sh3_zsrte439_pal.mem 0x47097d4c
10 95254 3072 504 sh3_zsrte4310_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte4310.mem 1240 137 1 sh3_zsrte4310_pal.mem 0x47097d4c
11 97432 3072 504 sh3_zsrte4311_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte4311.mem 1465 162 1 sh3_zsrte4311_pal.mem 0x47097d4c
12 97945 3072 504 sh3_zsrte4312_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte4312.mem 1519 168 1 sh3_zsrte4312_pal.mem 0x47097d4c
13 121898 2048 508 sh3_zsrte4313_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrte4313.mem 1357 150 0 sh3_zsrte4313_pal.mem 0x20ffffff
14 123287 2048 508 sh3_zsrte4314_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrte4314.mem 1825 202 1 sh3_zsrte4314_pal.mem 0x20ffffff
15 123920 2048 508 sh3_zsrte4315_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrte4315.mem 1789 198 1 sh3_zsrte4315_pal.mem 0x20ffffff
