# Ch434 epoch descriptor table (39 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 39 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c0.mem 35 3 0 sh3_zsrt139l7c0_pal.mem 0x00000000
1 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c1.mem 35 3 1 sh3_zsrt139l7c0_pal.mem 0x00000000
2 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c2.mem 35 3 1 sh3_zsrt139l7c0_pal.mem 0x00000000
3 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c3.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
4 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c4.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
5 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c5.mem 53 5 1 sh3_zsrt139l7c0_pal.mem 0x00000000
6 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c6.mem 53 5 1 sh3_zsrt139l7c0_pal.mem 0x00000000
7 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c7.mem 62 6 1 sh3_zsrt139l7c0_pal.mem 0x00000000
8 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c8.mem 89 9 1 sh3_zsrt139l7c0_pal.mem 0x00000000
9 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c9.mem 467 51 1 sh3_zsrt139l7c0_pal.mem 0x00000000
10 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c10.mem 359 39 1 sh3_zsrt139l7c0_pal.mem 0x00000000
11 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c11.mem 98 10 1 sh3_zsrt139l7c0_pal.mem 0x00000000
12 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c12.mem 71 7 1 sh3_zsrt139l7c0_pal.mem 0x00000000
13 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c13.mem 62 6 1 sh3_zsrt139l7c0_pal.mem 0x00000000
14 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c14.mem 53 5 1 sh3_zsrt139l7c0_pal.mem 0x00000000
15 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c15.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
16 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c16.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
17 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c17.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
18 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c18.mem 35 3 1 sh3_zsrt139l7c0_pal.mem 0x00000000
19 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c19.mem 35 3 1 sh3_zsrt139l7c0_pal.mem 0x00000000
20 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c20.mem 35 3 1 sh3_zsrt139l7c0_pal.mem 0x00000000
21 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c21.mem 35 3 1 sh3_zsrt139l7c0_pal.mem 0x00000000
22 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c22.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
23 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c23.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
24 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c24.mem 53 5 1 sh3_zsrt139l7c0_pal.mem 0x00000000
25 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c25.mem 53 5 1 sh3_zsrt139l7c0_pal.mem 0x00000000
26 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c26.mem 62 6 1 sh3_zsrt139l7c0_pal.mem 0x00000000
27 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c27.mem 80 8 1 sh3_zsrt139l7c0_pal.mem 0x00000000
28 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c28.mem 287 31 1 sh3_zsrt139l7c0_pal.mem 0x00000000
29 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c29.mem 530 58 1 sh3_zsrt139l7c0_pal.mem 0x00000000
30 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c30.mem 107 11 1 sh3_zsrt139l7c0_pal.mem 0x00000000
31 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c31.mem 71 7 1 sh3_zsrt139l7c0_pal.mem 0x00000000
32 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c32.mem 62 6 1 sh3_zsrt139l7c0_pal.mem 0x00000000
33 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c33.mem 53 5 1 sh3_zsrt139l7c0_pal.mem 0x00000000
34 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c34.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
35 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c35.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
36 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c36.mem 44 4 1 sh3_zsrt139l7c0_pal.mem 0x00000000
37 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c37.mem 35 3 1 sh3_zsrt139l7c0_pal.mem 0x00000000
38 196167 11264 480 sh3_zsrt139l7c0_tex_lpddr.mem 0x200000 262144 0xedffb312 feeder_sh3_zsrt139l7c38.mem 26 2 1 sh3_zsrt139l7c0_pal.mem 0x00000000
