# Ch434 epoch descriptor table (656 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 656 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l10.mem 35 3 0 sh3_zsrt139l10_pal.mem 0x00000000
1 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l11.mem 44 4 1 sh3_zsrt139l10_pal.mem 0x00000000
2 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l12.mem 44 4 1 sh3_zsrt139l10_pal.mem 0x00000000
3 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l13.mem 62 6 1 sh3_zsrt139l10_pal.mem 0x00000000
4 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l14.mem 116 12 1 sh3_zsrt139l10_pal.mem 0x00000000
5 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l15.mem 143 15 1 sh3_zsrt139l10_pal.mem 0x00000000
6 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l16.mem 62 6 1 sh3_zsrt139l10_pal.mem 0x00000000
7 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l17.mem 44 4 1 sh3_zsrt139l10_pal.mem 0x00000000
8 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l18.mem 44 4 1 sh3_zsrt139l10_pal.mem 0x00000000
9 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l19.mem 35 3 1 sh3_zsrt139l10_pal.mem 0x00000000
10 177029 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l110.mem 17 1 1 sh3_zsrt139l10_pal.mem 0x00000000
11 177272 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l111.mem 206 22 1 sh3_zsrt139l10_pal.mem 0x00000000
12 177291 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l112.mem 413 45 1 sh3_zsrt139l10_pal.mem 0x00000000
13 177291 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l113.mem 557 61 1 sh3_zsrt139l10_pal.mem 0x00000000
14 177331 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l114.mem 341 37 1 sh3_zsrt139l10_pal.mem 0x00000000
15 177350 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l115.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
16 177364 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l116.mem 143 15 1 sh3_zsrt139l10_pal.mem 0x00000000
17 177397 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l117.mem 62 6 1 sh3_zsrt139l10_pal.mem 0x00000000
18 177638 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l118.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
19 177671 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l119.mem 71 7 1 sh3_zsrt139l10_pal.mem 0x00000000
20 177690 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l120.mem 89 9 1 sh3_zsrt139l10_pal.mem 0x00000000
21 177704 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l121.mem 116 12 1 sh3_zsrt139l10_pal.mem 0x00000000
22 177723 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l122.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
23 177737 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l123.mem 116 12 1 sh3_zsrt139l10_pal.mem 0x00000000
24 177756 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l124.mem 431 47 1 sh3_zsrt139l10_pal.mem 0x00000000
25 177756 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l125.mem 80 8 1 sh3_zsrt139l10_pal.mem 0x00000000
26 177763 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l126.mem 629 69 1 sh3_zsrt139l10_pal.mem 0x00000000
27 177763 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l127.mem 836 92 1 sh3_zsrt139l10_pal.mem 0x00000000
28 177803 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l128.mem 665 73 1 sh3_zsrt139l10_pal.mem 0x00000000
29 177810 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l129.mem 134 14 1 sh3_zsrt139l10_pal.mem 0x00000000
30 177822 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l130.mem 251 27 1 sh3_zsrt139l10_pal.mem 0x00000000
31 177836 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l131.mem 350 38 1 sh3_zsrt139l10_pal.mem 0x00000000
32 177855 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l132.mem 296 32 1 sh3_zsrt139l10_pal.mem 0x00000000
33 177862 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l133.mem 521 57 1 sh3_zsrt139l10_pal.mem 0x00000000
34 177895 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l134.mem 80 8 1 sh3_zsrt139l10_pal.mem 0x00000000
35 177909 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l135.mem 206 22 1 sh3_zsrt139l10_pal.mem 0x00000000
36 177928 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l136.mem 197 21 1 sh3_zsrt139l10_pal.mem 0x00000000
37 178041 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l137.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
38 178067 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l138.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
39 178099 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l139.mem 161 17 1 sh3_zsrt139l10_pal.mem 0x00000000
40 178138 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l140.mem 197 21 1 sh3_zsrt139l10_pal.mem 0x00000000
41 178152 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l141.mem 125 13 1 sh3_zsrt139l10_pal.mem 0x00000000
42 178191 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l142.mem 134 14 1 sh3_zsrt139l10_pal.mem 0x00000000
43 178205 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l143.mem 170 18 1 sh3_zsrt139l10_pal.mem 0x00000000
44 178224 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l144.mem 215 23 1 sh3_zsrt139l10_pal.mem 0x00000000
45 178250 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l145.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
46 178257 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l146.mem 305 33 1 sh3_zsrt139l10_pal.mem 0x00000000
47 178290 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l147.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
48 178304 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l148.mem 170 18 1 sh3_zsrt139l10_pal.mem 0x00000000
49 178323 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l149.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
50 178337 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l150.mem 170 18 1 sh3_zsrt139l10_pal.mem 0x00000000
51 178356 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l151.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
52 178370 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l152.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
53 178389 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l153.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
54 178403 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l154.mem 62 6 1 sh3_zsrt139l10_pal.mem 0x00000000
55 178415 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l155.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
56 178422 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l156.mem 215 23 1 sh3_zsrt139l10_pal.mem 0x00000000
57 178448 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l157.mem 125 13 1 sh3_zsrt139l10_pal.mem 0x00000000
58 178455 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l158.mem 215 23 1 sh3_zsrt139l10_pal.mem 0x00000000
59 178481 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l159.mem 161 17 1 sh3_zsrt139l10_pal.mem 0x00000000
60 178488 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l160.mem 197 21 1 sh3_zsrt139l10_pal.mem 0x00000000
61 178502 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l161.mem 35 3 1 sh3_zsrt139l10_pal.mem 0x00000000
62 178514 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l162.mem 152 16 1 sh3_zsrt139l10_pal.mem 0x00000000
63 178528 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l163.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
64 178547 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l164.mem 62 6 1 sh3_zsrt139l10_pal.mem 0x00000000
65 178554 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l165.mem 80 8 1 sh3_zsrt139l10_pal.mem 0x00000000
66 178568 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l166.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
67 178580 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l167.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
68 178587 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l168.mem 134 14 1 sh3_zsrt139l10_pal.mem 0x00000000
69 178601 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l169.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
70 178957 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l170.mem 62 6 1 sh3_zsrt139l10_pal.mem 0x00000000
71 178964 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l171.mem 71 7 1 sh3_zsrt139l10_pal.mem 0x00000000
72 178978 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l172.mem 71 7 1 sh3_zsrt139l10_pal.mem 0x00000000
73 178997 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l173.mem 80 8 1 sh3_zsrt139l10_pal.mem 0x00000000
74 179011 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l174.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
75 179030 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l175.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
76 179044 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l176.mem 35 3 1 sh3_zsrt139l10_pal.mem 0x00000000
77 179063 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l177.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
78 179077 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l178.mem 35 3 1 sh3_zsrt139l10_pal.mem 0x00000000
79 179096 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l179.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
80 179110 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l180.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
81 179129 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l181.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
82 179143 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l182.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
83 179162 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l183.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
84 179228 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l184.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
85 179242 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l185.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
86 179261 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l186.mem 17 1 1 sh3_zsrt139l10_pal.mem 0x00000000
87 179275 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l187.mem 17 1 1 sh3_zsrt139l10_pal.mem 0x00000000
88 179308 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l188.mem 35 3 1 sh3_zsrt139l10_pal.mem 0x00000000
89 179327 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l189.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
90 179341 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l190.mem 17 1 1 sh3_zsrt139l10_pal.mem 0x00000000
91 179360 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l191.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
92 179374 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l192.mem 35 3 1 sh3_zsrt139l10_pal.mem 0x00000000
93 179393 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l193.mem 44 4 1 sh3_zsrt139l10_pal.mem 0x00000000
94 179407 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l194.mem 17 1 1 sh3_zsrt139l10_pal.mem 0x00000000
95 179426 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l195.mem 17 1 1 sh3_zsrt139l10_pal.mem 0x00000000
96 179440 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l196.mem 26 2 1 sh3_zsrt139l10_pal.mem 0x00000000
97 179466 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l197.mem 17 1 1 sh3_zsrt139l10_pal.mem 0x00000000
98 179485 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l198.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
99 179499 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l199.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
100 179518 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1100.mem 53 5 1 sh3_zsrt139l10_pal.mem 0x00000000
101 179532 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1101.mem 62 6 1 sh3_zsrt139l10_pal.mem 0x00000000
102 179551 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1102.mem 89 9 1 sh3_zsrt139l10_pal.mem 0x00000000
103 179565 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1103.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
104 179584 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1104.mem 89 9 1 sh3_zsrt139l10_pal.mem 0x00000000
105 179598 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1105.mem 89 9 1 sh3_zsrt139l10_pal.mem 0x00000000
106 179617 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1106.mem 89 9 1 sh3_zsrt139l10_pal.mem 0x00000000
107 179631 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1107.mem 80 8 1 sh3_zsrt139l10_pal.mem 0x00000000
108 179650 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1108.mem 71 7 1 sh3_zsrt139l10_pal.mem 0x00000000
109 179664 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1109.mem 80 8 1 sh3_zsrt139l10_pal.mem 0x00000000
110 179683 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1110.mem 98 10 1 sh3_zsrt139l10_pal.mem 0x00000000
111 179697 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1111.mem 116 12 1 sh3_zsrt139l10_pal.mem 0x00000000
112 179716 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1112.mem 89 9 1 sh3_zsrt139l10_pal.mem 0x00000000
113 179730 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1113.mem 89 9 1 sh3_zsrt139l10_pal.mem 0x00000000
114 179749 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1114.mem 107 11 1 sh3_zsrt139l10_pal.mem 0x00000000
115 179763 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1115.mem 116 12 1 sh3_zsrt139l10_pal.mem 0x00000000
116 179782 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1116.mem 107 11 1 sh3_zsrt139l10_pal.mem 0x00000000
117 179796 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1117.mem 143 15 1 sh3_zsrt139l10_pal.mem 0x00000000
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119 179829 14336 480 sh3_zsrt139l10_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139l1119.mem 134 14 1 sh3_zsrt139l10_pal.mem 0x00000000
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