# Ch434 epoch descriptor table (631 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 631 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 177272 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f450.mem 206 22 0 sh3_zsrt139f450_pal.mem 0x00000000
1 177291 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f451.mem 962 106 1 sh3_zsrt139f450_pal.mem 0x00000000
2 177331 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f452.mem 332 36 1 sh3_zsrt139f450_pal.mem 0x00000000
3 177350 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f453.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
4 177364 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f454.mem 143 15 1 sh3_zsrt139f450_pal.mem 0x00000000
5 177397 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f455.mem 62 6 1 sh3_zsrt139f450_pal.mem 0x00000000
6 177638 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f456.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
7 177671 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f457.mem 71 7 1 sh3_zsrt139f450_pal.mem 0x00000000
8 177690 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f458.mem 89 9 1 sh3_zsrt139f450_pal.mem 0x00000000
9 177704 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f459.mem 116 12 1 sh3_zsrt139f450_pal.mem 0x00000000
10 177723 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4510.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
11 177737 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4511.mem 116 12 1 sh3_zsrt139f450_pal.mem 0x00000000
12 177756 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4512.mem 503 55 1 sh3_zsrt139f450_pal.mem 0x00000000
13 177763 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4513.mem 1466 162 1 sh3_zsrt139f450_pal.mem 0x00000000
14 177803 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4514.mem 629 69 1 sh3_zsrt139f450_pal.mem 0x00000000
15 177810 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4515.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
16 177822 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4516.mem 251 27 1 sh3_zsrt139f450_pal.mem 0x00000000
17 177836 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4517.mem 350 38 1 sh3_zsrt139f450_pal.mem 0x00000000
18 177855 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4518.mem 296 32 1 sh3_zsrt139f450_pal.mem 0x00000000
19 177862 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4519.mem 530 58 1 sh3_zsrt139f450_pal.mem 0x00000000
20 177895 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4520.mem 80 8 1 sh3_zsrt139f450_pal.mem 0x00000000
21 177909 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4521.mem 197 21 1 sh3_zsrt139f450_pal.mem 0x00000000
22 177928 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4522.mem 197 21 1 sh3_zsrt139f450_pal.mem 0x00000000
23 178041 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4523.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
24 178067 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4524.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
25 178099 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4525.mem 161 17 1 sh3_zsrt139f450_pal.mem 0x00000000
26 178138 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4526.mem 197 21 1 sh3_zsrt139f450_pal.mem 0x00000000
27 178152 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4527.mem 125 13 1 sh3_zsrt139f450_pal.mem 0x00000000
28 178191 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4528.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
29 178205 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4529.mem 170 18 1 sh3_zsrt139f450_pal.mem 0x00000000
30 178224 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4530.mem 224 24 1 sh3_zsrt139f450_pal.mem 0x00000000
31 178250 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4531.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
32 178257 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4532.mem 305 33 1 sh3_zsrt139f450_pal.mem 0x00000000
33 178290 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4533.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
34 178304 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4534.mem 170 18 1 sh3_zsrt139f450_pal.mem 0x00000000
35 178323 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4535.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
36 178337 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4536.mem 170 18 1 sh3_zsrt139f450_pal.mem 0x00000000
37 178356 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4537.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
38 178370 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4538.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
39 178389 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4539.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
40 178403 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4540.mem 62 6 1 sh3_zsrt139f450_pal.mem 0x00000000
41 178415 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4541.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
42 178422 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4542.mem 215 23 1 sh3_zsrt139f450_pal.mem 0x00000000
43 178448 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4543.mem 125 13 1 sh3_zsrt139f450_pal.mem 0x00000000
44 178455 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4544.mem 224 24 1 sh3_zsrt139f450_pal.mem 0x00000000
45 178481 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4545.mem 161 17 1 sh3_zsrt139f450_pal.mem 0x00000000
46 178488 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4546.mem 197 21 1 sh3_zsrt139f450_pal.mem 0x00000000
47 178502 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4547.mem 35 3 1 sh3_zsrt139f450_pal.mem 0x00000000
48 178514 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4548.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
49 178528 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4549.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
50 178547 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4550.mem 62 6 1 sh3_zsrt139f450_pal.mem 0x00000000
51 178554 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4551.mem 80 8 1 sh3_zsrt139f450_pal.mem 0x00000000
52 178568 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4552.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
53 178580 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4553.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
54 178587 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4554.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
55 178601 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4555.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
56 178957 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4556.mem 62 6 1 sh3_zsrt139f450_pal.mem 0x00000000
57 178964 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4557.mem 71 7 1 sh3_zsrt139f450_pal.mem 0x00000000
58 178978 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4558.mem 71 7 1 sh3_zsrt139f450_pal.mem 0x00000000
59 178997 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4559.mem 71 7 1 sh3_zsrt139f450_pal.mem 0x00000000
60 179011 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4560.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
61 179030 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4561.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
62 179044 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4562.mem 35 3 1 sh3_zsrt139f450_pal.mem 0x00000000
63 179063 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4563.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
64 179077 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4564.mem 35 3 1 sh3_zsrt139f450_pal.mem 0x00000000
65 179096 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4565.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
66 179110 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4566.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
67 179129 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4567.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
68 179143 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4568.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
69 179162 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4569.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
70 179228 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4570.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
71 179242 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4571.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
72 179261 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4572.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
73 179275 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4573.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
74 179308 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4574.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
75 179327 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4575.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
76 179341 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4576.mem 17 1 1 sh3_zsrt139f450_pal.mem 0x00000000
77 179360 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4577.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
78 179374 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4578.mem 35 3 1 sh3_zsrt139f450_pal.mem 0x00000000
79 179393 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4579.mem 35 3 1 sh3_zsrt139f450_pal.mem 0x00000000
80 179407 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4580.mem 17 1 1 sh3_zsrt139f450_pal.mem 0x00000000
81 179426 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4581.mem 17 1 1 sh3_zsrt139f450_pal.mem 0x00000000
82 179440 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4582.mem 26 2 1 sh3_zsrt139f450_pal.mem 0x00000000
83 179466 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4583.mem 17 1 1 sh3_zsrt139f450_pal.mem 0x00000000
84 179485 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4584.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
85 179499 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4585.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
86 179518 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4586.mem 53 5 1 sh3_zsrt139f450_pal.mem 0x00000000
87 179532 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4587.mem 62 6 1 sh3_zsrt139f450_pal.mem 0x00000000
88 179551 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4588.mem 89 9 1 sh3_zsrt139f450_pal.mem 0x00000000
89 179565 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4589.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
90 179584 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4590.mem 89 9 1 sh3_zsrt139f450_pal.mem 0x00000000
91 179598 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4591.mem 89 9 1 sh3_zsrt139f450_pal.mem 0x00000000
92 179617 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4592.mem 89 9 1 sh3_zsrt139f450_pal.mem 0x00000000
93 179631 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4593.mem 80 8 1 sh3_zsrt139f450_pal.mem 0x00000000
94 179650 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4594.mem 71 7 1 sh3_zsrt139f450_pal.mem 0x00000000
95 179664 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4595.mem 80 8 1 sh3_zsrt139f450_pal.mem 0x00000000
96 179683 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4596.mem 98 10 1 sh3_zsrt139f450_pal.mem 0x00000000
97 179697 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4597.mem 116 12 1 sh3_zsrt139f450_pal.mem 0x00000000
98 179716 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4598.mem 89 9 1 sh3_zsrt139f450_pal.mem 0x00000000
99 179730 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f4599.mem 89 9 1 sh3_zsrt139f450_pal.mem 0x00000000
100 179749 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45100.mem 107 11 1 sh3_zsrt139f450_pal.mem 0x00000000
101 179763 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45101.mem 116 12 1 sh3_zsrt139f450_pal.mem 0x00000000
102 179782 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45102.mem 107 11 1 sh3_zsrt139f450_pal.mem 0x00000000
103 179796 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45103.mem 143 15 1 sh3_zsrt139f450_pal.mem 0x00000000
104 179815 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45104.mem 107 11 1 sh3_zsrt139f450_pal.mem 0x00000000
105 179829 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45105.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
106 179848 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45106.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
107 179862 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45107.mem 143 15 1 sh3_zsrt139f450_pal.mem 0x00000000
108 179881 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45108.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
109 179895 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45109.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
110 179914 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45110.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
111 179928 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45111.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
112 179947 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45112.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
113 179961 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45113.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
114 179980 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45114.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
115 179994 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45115.mem 161 17 1 sh3_zsrt139f450_pal.mem 0x00000000
116 180013 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45116.mem 134 14 1 sh3_zsrt139f450_pal.mem 0x00000000
117 180027 14336 480 sh3_zsrt139f450_tex_lpddr.mem 0x200000 262144 0x00000000 feeder_sh3_zsrt139f45117.mem 152 16 1 sh3_zsrt139f450_pal.mem 0x00000000
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