# Ch407 epoch descriptor table (187 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 187 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 198075 10240 480 sh3_zsrt139d30_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d30.mem 557 61 0 sh3_zsrt139d30_pal.mem 0x158afe76
1 198075 10240 480 sh3_zsrt139d31_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d31.mem 323 35 1 sh3_zsrt139d31_pal.mem 0x158afe76
2 198075 10240 480 sh3_zsrt139d32_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d32.mem 53 5 1 sh3_zsrt139d32_pal.mem 0x158afe76
3 198092 10240 480 sh3_zsrt139d33_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d33.mem 665 73 1 sh3_zsrt139d33_pal.mem 0x158afe76
4 198092 10240 480 sh3_zsrt139d34_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d34.mem 215 23 1 sh3_zsrt139d34_pal.mem 0x158afe76
5 198092 10240 480 sh3_zsrt139d35_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d35.mem 458 50 1 sh3_zsrt139d35_pal.mem 0x158afe76
6 198092 10240 480 sh3_zsrt139d36_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d36.mem 431 47 1 sh3_zsrt139d36_pal.mem 0x158afe76
7 198092 10240 480 sh3_zsrt139d37_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d37.mem 395 43 1 sh3_zsrt139d37_pal.mem 0x158afe76
8 198092 10240 480 sh3_zsrt139d38_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d38.mem 206 22 1 sh3_zsrt139d38_pal.mem 0x158afe76
9 198092 10240 480 sh3_zsrt139d39_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d39.mem 170 18 1 sh3_zsrt139d39_pal.mem 0x158afe76
10 198092 10240 480 sh3_zsrt139d310_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d310.mem 242 26 1 sh3_zsrt139d310_pal.mem 0x158afe76
11 198092 10240 480 sh3_zsrt139d311_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d311.mem 359 39 1 sh3_zsrt139d311_pal.mem 0x158afe76
12 198092 10240 480 sh3_zsrt139d312_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d312.mem 323 35 1 sh3_zsrt139d312_pal.mem 0x158afe76
13 198092 10240 480 sh3_zsrt139d313_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d313.mem 215 23 1 sh3_zsrt139d313_pal.mem 0x158afe76
14 198092 10240 480 sh3_zsrt139d314_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d314.mem 314 34 1 sh3_zsrt139d314_pal.mem 0x158afe76
15 198092 10240 480 sh3_zsrt139d315_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d315.mem 278 30 1 sh3_zsrt139d315_pal.mem 0x158afe76
16 198092 10240 480 sh3_zsrt139d316_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d316.mem 116 12 1 sh3_zsrt139d316_pal.mem 0x158afe76
17 198092 10240 480 sh3_zsrt139d317_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d317.mem 197 21 1 sh3_zsrt139d317_pal.mem 0x158afe76
18 198092 10240 480 sh3_zsrt139d318_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d318.mem 458 50 1 sh3_zsrt139d318_pal.mem 0x158afe76
19 198092 10240 480 sh3_zsrt139d319_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d319.mem 269 29 1 sh3_zsrt139d319_pal.mem 0x158afe76
20 198092 10240 480 sh3_zsrt139d320_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d320.mem 206 22 1 sh3_zsrt139d320_pal.mem 0x158afe76
21 198092 10240 480 sh3_zsrt139d321_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d321.mem 323 35 1 sh3_zsrt139d321_pal.mem 0x158afe76
22 198092 10240 480 sh3_zsrt139d322_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d322.mem 494 54 1 sh3_zsrt139d322_pal.mem 0x158afe76
23 198092 10240 480 sh3_zsrt139d323_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d323.mem 566 62 1 sh3_zsrt139d323_pal.mem 0x158afe76
24 198092 10240 480 sh3_zsrt139d324_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d324.mem 287 31 1 sh3_zsrt139d324_pal.mem 0x158afe76
25 198092 10240 480 sh3_zsrt139d325_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d325.mem 260 28 1 sh3_zsrt139d325_pal.mem 0x158afe76
26 198092 10240 480 sh3_zsrt139d326_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d326.mem 89 9 1 sh3_zsrt139d326_pal.mem 0x158afe76
27 198092 10240 480 sh3_zsrt139d327_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d327.mem 359 39 1 sh3_zsrt139d327_pal.mem 0x158afe76
28 198092 10240 480 sh3_zsrt139d328_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d328.mem 539 59 1 sh3_zsrt139d328_pal.mem 0x158afe76
29 198092 10240 480 sh3_zsrt139d329_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d329.mem 323 35 1 sh3_zsrt139d329_pal.mem 0x158afe76
30 198092 10240 480 sh3_zsrt139d330_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d330.mem 179 19 1 sh3_zsrt139d330_pal.mem 0x158afe76
31 198092 10240 480 sh3_zsrt139d331_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d331.mem 494 54 1 sh3_zsrt139d331_pal.mem 0x158afe76
32 198092 10240 480 sh3_zsrt139d332_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d332.mem 251 27 1 sh3_zsrt139d332_pal.mem 0x158afe76
33 198092 10240 480 sh3_zsrt139d333_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d333.mem 116 12 1 sh3_zsrt139d333_pal.mem 0x158afe76
34 198092 10240 480 sh3_zsrt139d334_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d334.mem 251 27 1 sh3_zsrt139d334_pal.mem 0x158afe76
35 198092 10240 480 sh3_zsrt139d335_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d335.mem 251 27 1 sh3_zsrt139d335_pal.mem 0x158afe76
36 198092 10240 480 sh3_zsrt139d336_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d336.mem 170 18 1 sh3_zsrt139d336_pal.mem 0x158afe76
37 198092 10240 480 sh3_zsrt139d337_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d337.mem 188 20 1 sh3_zsrt139d337_pal.mem 0x158afe76
38 198092 10240 480 sh3_zsrt139d338_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d338.mem 170 18 1 sh3_zsrt139d338_pal.mem 0x158afe76
39 198092 10240 480 sh3_zsrt139d339_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d339.mem 71 7 1 sh3_zsrt139d339_pal.mem 0x158afe76
40 198092 10240 480 sh3_zsrt139d340_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d340.mem 224 24 1 sh3_zsrt139d340_pal.mem 0x158afe76
41 198092 10240 480 sh3_zsrt139d341_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d341.mem 143 15 1 sh3_zsrt139d341_pal.mem 0x158afe76
42 198092 10240 480 sh3_zsrt139d342_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d342.mem 305 33 1 sh3_zsrt139d342_pal.mem 0x158afe76
43 198092 10240 480 sh3_zsrt139d343_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d343.mem 143 15 1 sh3_zsrt139d343_pal.mem 0x158afe76
44 198092 10240 480 sh3_zsrt139d344_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d344.mem 71 7 1 sh3_zsrt139d344_pal.mem 0x158afe76
45 198092 10240 480 sh3_zsrt139d345_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d345.mem 233 25 1 sh3_zsrt139d345_pal.mem 0x158afe76
46 198092 10240 480 sh3_zsrt139d346_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d346.mem 260 28 1 sh3_zsrt139d346_pal.mem 0x158afe76
47 198092 10240 480 sh3_zsrt139d347_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d347.mem 350 38 1 sh3_zsrt139d347_pal.mem 0x158afe76
48 198092 10240 480 sh3_zsrt139d348_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d348.mem 188 20 1 sh3_zsrt139d348_pal.mem 0x158afe76
49 198092 10240 480 sh3_zsrt139d349_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d349.mem 80 8 1 sh3_zsrt139d349_pal.mem 0x158afe76
50 198092 10240 480 sh3_zsrt139d350_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d350.mem 251 27 1 sh3_zsrt139d350_pal.mem 0x158afe76
51 198092 10240 480 sh3_zsrt139d351_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d351.mem 125 13 1 sh3_zsrt139d351_pal.mem 0x158afe76
52 198092 10240 480 sh3_zsrt139d352_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d352.mem 269 29 1 sh3_zsrt139d352_pal.mem 0x158afe76
53 198092 10240 480 sh3_zsrt139d353_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d353.mem 179 19 1 sh3_zsrt139d353_pal.mem 0x158afe76
54 198092 10240 480 sh3_zsrt139d354_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d354.mem 341 37 1 sh3_zsrt139d354_pal.mem 0x158afe76
55 198092 10240 480 sh3_zsrt139d355_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d355.mem 206 22 1 sh3_zsrt139d355_pal.mem 0x158afe76
56 198092 10240 480 sh3_zsrt139d356_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d356.mem 179 19 1 sh3_zsrt139d356_pal.mem 0x158afe76
57 198092 10240 480 sh3_zsrt139d357_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d357.mem 98 10 1 sh3_zsrt139d357_pal.mem 0x158afe76
58 198092 10240 480 sh3_zsrt139d358_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d358.mem 242 26 1 sh3_zsrt139d358_pal.mem 0x158afe76
59 198092 10240 480 sh3_zsrt139d359_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d359.mem 80 8 1 sh3_zsrt139d359_pal.mem 0x158afe76
60 198092 10240 480 sh3_zsrt139d360_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d360.mem 53 5 1 sh3_zsrt139d360_pal.mem 0x158afe76
61 198092 10240 480 sh3_zsrt139d361_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d361.mem 44 4 1 sh3_zsrt139d361_pal.mem 0x158afe76
62 198092 10240 480 sh3_zsrt139d362_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d362.mem 116 12 1 sh3_zsrt139d362_pal.mem 0x158afe76
63 198092 10240 480 sh3_zsrt139d363_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d363.mem 107 11 1 sh3_zsrt139d363_pal.mem 0x158afe76
64 198092 10240 480 sh3_zsrt139d364_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d364.mem 224 24 1 sh3_zsrt139d364_pal.mem 0x158afe76
65 198092 10240 480 sh3_zsrt139d365_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d365.mem 107 11 1 sh3_zsrt139d365_pal.mem 0x158afe76
66 198092 10240 480 sh3_zsrt139d366_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d366.mem 629 69 1 sh3_zsrt139d366_pal.mem 0x158afe76
67 198092 10240 480 sh3_zsrt139d367_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d367.mem 287 31 1 sh3_zsrt139d367_pal.mem 0x158afe76
68 198092 10240 480 sh3_zsrt139d368_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d368.mem 116 12 1 sh3_zsrt139d368_pal.mem 0x158afe76
69 198092 10240 480 sh3_zsrt139d369_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d369.mem 134 14 1 sh3_zsrt139d369_pal.mem 0x158afe76
70 198092 10240 480 sh3_zsrt139d370_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d370.mem 287 31 1 sh3_zsrt139d370_pal.mem 0x158afe76
71 198092 10240 480 sh3_zsrt139d371_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d371.mem 224 24 1 sh3_zsrt139d371_pal.mem 0x158afe76
72 198092 10240 480 sh3_zsrt139d372_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d372.mem 431 47 1 sh3_zsrt139d372_pal.mem 0x158afe76
73 198092 10240 480 sh3_zsrt139d373_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d373.mem 53 5 1 sh3_zsrt139d373_pal.mem 0x158afe76
74 198092 10240 480 sh3_zsrt139d374_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d374.mem 53 5 1 sh3_zsrt139d374_pal.mem 0x158afe76
75 198092 10240 480 sh3_zsrt139d375_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d375.mem 71 7 1 sh3_zsrt139d375_pal.mem 0x158afe76
76 198092 10240 480 sh3_zsrt139d376_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d376.mem 161 17 1 sh3_zsrt139d376_pal.mem 0x158afe76
77 198092 10240 480 sh3_zsrt139d377_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d377.mem 206 22 1 sh3_zsrt139d377_pal.mem 0x158afe76
78 198092 10240 480 sh3_zsrt139d378_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d378.mem 89 9 1 sh3_zsrt139d378_pal.mem 0x158afe76
79 198092 10240 480 sh3_zsrt139d379_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d379.mem 89 9 1 sh3_zsrt139d379_pal.mem 0x158afe76
80 198092 10240 480 sh3_zsrt139d380_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d380.mem 143 15 1 sh3_zsrt139d380_pal.mem 0x158afe76
81 198092 10240 480 sh3_zsrt139d381_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d381.mem 368 40 1 sh3_zsrt139d381_pal.mem 0x158afe76
82 198092 10240 480 sh3_zsrt139d382_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d382.mem 80 8 1 sh3_zsrt139d382_pal.mem 0x158afe76
83 198092 10240 480 sh3_zsrt139d383_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d383.mem 152 16 1 sh3_zsrt139d383_pal.mem 0x158afe76
84 198092 10240 480 sh3_zsrt139d384_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d384.mem 314 34 1 sh3_zsrt139d384_pal.mem 0x158afe76
85 198092 10240 480 sh3_zsrt139d385_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d385.mem 116 12 1 sh3_zsrt139d385_pal.mem 0x158afe76
86 198092 10240 480 sh3_zsrt139d386_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d386.mem 179 19 1 sh3_zsrt139d386_pal.mem 0x158afe76
87 198092 10240 480 sh3_zsrt139d387_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d387.mem 62 6 1 sh3_zsrt139d387_pal.mem 0x158afe76
88 198092 10240 480 sh3_zsrt139d388_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d388.mem 89 9 1 sh3_zsrt139d388_pal.mem 0x158afe76
89 198092 10240 480 sh3_zsrt139d389_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d389.mem 278 30 1 sh3_zsrt139d389_pal.mem 0x158afe76
90 198092 10240 480 sh3_zsrt139d390_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d390.mem 350 38 1 sh3_zsrt139d390_pal.mem 0x158afe76
91 198092 10240 480 sh3_zsrt139d391_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d391.mem 134 14 1 sh3_zsrt139d391_pal.mem 0x158afe76
92 198092 10240 480 sh3_zsrt139d392_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d392.mem 332 36 1 sh3_zsrt139d392_pal.mem 0x158afe76
93 198092 10240 480 sh3_zsrt139d393_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d393.mem 404 44 1 sh3_zsrt139d393_pal.mem 0x158afe76
94 198092 10240 480 sh3_zsrt139d394_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d394.mem 179 19 1 sh3_zsrt139d394_pal.mem 0x158afe76
95 198092 10240 480 sh3_zsrt139d395_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d395.mem 107 11 1 sh3_zsrt139d395_pal.mem 0x158afe76
96 198092 10240 480 sh3_zsrt139d396_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d396.mem 161 17 1 sh3_zsrt139d396_pal.mem 0x158afe76
97 198092 10240 480 sh3_zsrt139d397_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d397.mem 539 59 1 sh3_zsrt139d397_pal.mem 0x158afe76
98 198092 10240 480 sh3_zsrt139d398_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d398.mem 143 15 1 sh3_zsrt139d398_pal.mem 0x158afe76
99 198092 10240 480 sh3_zsrt139d399_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d399.mem 332 36 1 sh3_zsrt139d399_pal.mem 0x158afe76
100 198092 10240 480 sh3_zsrt139d3100_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3100.mem 161 17 1 sh3_zsrt139d3100_pal.mem 0x158afe76
101 198092 10240 480 sh3_zsrt139d3101_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3101.mem 107 11 1 sh3_zsrt139d3101_pal.mem 0x158afe76
102 198092 10240 480 sh3_zsrt139d3102_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3102.mem 368 40 1 sh3_zsrt139d3102_pal.mem 0x158afe76
103 198092 10240 480 sh3_zsrt139d3103_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3103.mem 368 40 1 sh3_zsrt139d3103_pal.mem 0x158afe76
104 198092 10240 480 sh3_zsrt139d3104_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3104.mem 80 8 1 sh3_zsrt139d3104_pal.mem 0x158afe76
105 198092 10240 480 sh3_zsrt139d3105_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3105.mem 62 6 1 sh3_zsrt139d3105_pal.mem 0x158afe76
106 198092 10240 480 sh3_zsrt139d3106_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3106.mem 53 5 1 sh3_zsrt139d3106_pal.mem 0x158afe76
107 198092 10240 480 sh3_zsrt139d3107_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3107.mem 143 15 1 sh3_zsrt139d3107_pal.mem 0x158afe76
108 198092 10240 480 sh3_zsrt139d3108_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3108.mem 107 11 1 sh3_zsrt139d3108_pal.mem 0x158afe76
109 198092 10240 480 sh3_zsrt139d3109_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3109.mem 89 9 1 sh3_zsrt139d3109_pal.mem 0x158afe76
110 198092 10240 480 sh3_zsrt139d3110_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3110.mem 152 16 1 sh3_zsrt139d3110_pal.mem 0x158afe76
111 198092 10240 480 sh3_zsrt139d3111_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3111.mem 314 34 1 sh3_zsrt139d3111_pal.mem 0x158afe76
112 198092 10240 480 sh3_zsrt139d3112_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3112.mem 44 4 1 sh3_zsrt139d3112_pal.mem 0x158afe76
113 198092 10240 480 sh3_zsrt139d3113_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3113.mem 44 4 1 sh3_zsrt139d3113_pal.mem 0x158afe76
114 198092 10240 480 sh3_zsrt139d3114_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3114.mem 62 6 1 sh3_zsrt139d3114_pal.mem 0x158afe76
115 198092 10240 480 sh3_zsrt139d3115_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3115.mem 206 22 1 sh3_zsrt139d3115_pal.mem 0x158afe76
116 198092 10240 480 sh3_zsrt139d3116_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3116.mem 359 39 1 sh3_zsrt139d3116_pal.mem 0x158afe76
117 198092 10240 480 sh3_zsrt139d3117_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3117.mem 215 23 1 sh3_zsrt139d3117_pal.mem 0x158afe76
118 198092 10240 480 sh3_zsrt139d3118_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3118.mem 206 22 1 sh3_zsrt139d3118_pal.mem 0x158afe76
119 198092 10240 480 sh3_zsrt139d3119_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3119.mem 116 12 1 sh3_zsrt139d3119_pal.mem 0x158afe76
120 198092 10240 480 sh3_zsrt139d3120_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3120.mem 638 70 1 sh3_zsrt139d3120_pal.mem 0x158afe76
121 198092 10240 480 sh3_zsrt139d3121_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3121.mem 179 19 1 sh3_zsrt139d3121_pal.mem 0x158afe76
122 198092 10240 480 sh3_zsrt139d3122_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3122.mem 152 16 1 sh3_zsrt139d3122_pal.mem 0x158afe76
123 198092 10240 480 sh3_zsrt139d3123_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3123.mem 368 40 1 sh3_zsrt139d3123_pal.mem 0x158afe76
124 198092 10240 480 sh3_zsrt139d3124_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3124.mem 125 13 1 sh3_zsrt139d3124_pal.mem 0x158afe76
125 198092 10240 480 sh3_zsrt139d3125_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3125.mem 53 5 1 sh3_zsrt139d3125_pal.mem 0x158afe76
126 198092 10240 480 sh3_zsrt139d3126_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3126.mem 71 7 1 sh3_zsrt139d3126_pal.mem 0x158afe76
127 198092 10240 480 sh3_zsrt139d3127_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3127.mem 431 47 1 sh3_zsrt139d3127_pal.mem 0x158afe76
128 198092 10240 480 sh3_zsrt139d3128_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3128.mem 143 15 1 sh3_zsrt139d3128_pal.mem 0x158afe76
129 198092 10240 480 sh3_zsrt139d3129_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3129.mem 125 13 1 sh3_zsrt139d3129_pal.mem 0x158afe76
130 198092 10240 480 sh3_zsrt139d3130_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3130.mem 503 55 1 sh3_zsrt139d3130_pal.mem 0x158afe76
131 198092 10240 480 sh3_zsrt139d3131_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3131.mem 116 12 1 sh3_zsrt139d3131_pal.mem 0x158afe76
132 198092 10240 480 sh3_zsrt139d3132_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3132.mem 62 6 1 sh3_zsrt139d3132_pal.mem 0x158afe76
133 198092 10240 480 sh3_zsrt139d3133_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3133.mem 53 5 1 sh3_zsrt139d3133_pal.mem 0x158afe76
134 198092 10240 480 sh3_zsrt139d3134_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3134.mem 188 20 1 sh3_zsrt139d3134_pal.mem 0x158afe76
135 198092 10240 480 sh3_zsrt139d3135_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3135.mem 251 27 1 sh3_zsrt139d3135_pal.mem 0x158afe76
136 198092 10240 480 sh3_zsrt139d3136_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3136.mem 89 9 1 sh3_zsrt139d3136_pal.mem 0x158afe76
137 198092 10240 480 sh3_zsrt139d3137_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3137.mem 71 7 1 sh3_zsrt139d3137_pal.mem 0x158afe76
138 198092 10240 480 sh3_zsrt139d3138_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3138.mem 71 7 1 sh3_zsrt139d3138_pal.mem 0x158afe76
139 198092 10240 480 sh3_zsrt139d3139_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3139.mem 80 8 1 sh3_zsrt139d3139_pal.mem 0x158afe76
140 198092 10240 480 sh3_zsrt139d3140_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3140.mem 179 19 1 sh3_zsrt139d3140_pal.mem 0x158afe76
141 198092 10240 480 sh3_zsrt139d3141_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3141.mem 251 27 1 sh3_zsrt139d3141_pal.mem 0x158afe76
142 198092 10240 480 sh3_zsrt139d3142_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3142.mem 161 17 1 sh3_zsrt139d3142_pal.mem 0x158afe76
143 198092 10240 480 sh3_zsrt139d3143_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3143.mem 161 17 1 sh3_zsrt139d3143_pal.mem 0x158afe76
144 198092 10240 480 sh3_zsrt139d3144_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3144.mem 71 7 1 sh3_zsrt139d3144_pal.mem 0x158afe76
145 198092 10240 480 sh3_zsrt139d3145_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3145.mem 71 7 1 sh3_zsrt139d3145_pal.mem 0x158afe76
146 198092 10240 480 sh3_zsrt139d3146_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3146.mem 80 8 1 sh3_zsrt139d3146_pal.mem 0x158afe76
147 198092 10240 480 sh3_zsrt139d3147_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3147.mem 125 13 1 sh3_zsrt139d3147_pal.mem 0x158afe76
148 198092 10240 480 sh3_zsrt139d3148_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3148.mem 251 27 1 sh3_zsrt139d3148_pal.mem 0x158afe76
149 198092 10240 480 sh3_zsrt139d3149_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3149.mem 80 8 1 sh3_zsrt139d3149_pal.mem 0x158afe76
150 198092 10240 480 sh3_zsrt139d3150_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3150.mem 62 6 1 sh3_zsrt139d3150_pal.mem 0x158afe76
151 198092 10240 480 sh3_zsrt139d3151_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3151.mem 44 4 1 sh3_zsrt139d3151_pal.mem 0x158afe76
152 198092 10240 480 sh3_zsrt139d3152_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3152.mem 44 4 1 sh3_zsrt139d3152_pal.mem 0x158afe76
153 198092 10240 480 sh3_zsrt139d3153_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3153.mem 35 3 1 sh3_zsrt139d3153_pal.mem 0x158afe76
154 198092 10240 480 sh3_zsrt139d3154_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3154.mem 35 3 1 sh3_zsrt139d3154_pal.mem 0x158afe76
155 198092 10240 480 sh3_zsrt139d3155_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3155.mem 35 3 1 sh3_zsrt139d3155_pal.mem 0x158afe76
156 198092 10240 480 sh3_zsrt139d3156_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3156.mem 53 5 1 sh3_zsrt139d3156_pal.mem 0x158afe76
157 198092 10240 480 sh3_zsrt139d3157_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3157.mem 107 11 1 sh3_zsrt139d3157_pal.mem 0x158afe76
158 198092 10240 480 sh3_zsrt139d3158_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3158.mem 71 7 1 sh3_zsrt139d3158_pal.mem 0x158afe76
159 198092 10240 480 sh3_zsrt139d3159_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3159.mem 71 7 1 sh3_zsrt139d3159_pal.mem 0x158afe76
160 198092 10240 480 sh3_zsrt139d3160_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3160.mem 98 10 1 sh3_zsrt139d3160_pal.mem 0x158afe76
161 198092 10240 480 sh3_zsrt139d3161_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3161.mem 215 23 1 sh3_zsrt139d3161_pal.mem 0x158afe76
162 198092 10240 480 sh3_zsrt139d3162_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3162.mem 521 57 1 sh3_zsrt139d3162_pal.mem 0x158afe76
163 198092 10240 480 sh3_zsrt139d3163_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3163.mem 701 77 1 sh3_zsrt139d3163_pal.mem 0x158afe76
164 198092 10240 480 sh3_zsrt139d3164_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3164.mem 80 8 1 sh3_zsrt139d3164_pal.mem 0x158afe76
165 198092 10240 480 sh3_zsrt139d3165_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3165.mem 125 13 1 sh3_zsrt139d3165_pal.mem 0x158afe76
166 198092 10240 480 sh3_zsrt139d3166_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3166.mem 287 31 1 sh3_zsrt139d3166_pal.mem 0x158afe76
167 198092 10240 480 sh3_zsrt139d3167_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3167.mem 107 11 1 sh3_zsrt139d3167_pal.mem 0x158afe76
168 198092 10240 480 sh3_zsrt139d3168_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3168.mem 89 9 1 sh3_zsrt139d3168_pal.mem 0x158afe76
169 198092 10240 480 sh3_zsrt139d3169_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3169.mem 161 17 1 sh3_zsrt139d3169_pal.mem 0x158afe76
170 198092 10240 480 sh3_zsrt139d3170_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3170.mem 125 13 1 sh3_zsrt139d3170_pal.mem 0x158afe76
171 198092 10240 480 sh3_zsrt139d3171_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3171.mem 80 8 1 sh3_zsrt139d3171_pal.mem 0x158afe76
172 198092 10240 480 sh3_zsrt139d3172_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3172.mem 53 5 1 sh3_zsrt139d3172_pal.mem 0x158afe76
173 198092 10240 480 sh3_zsrt139d3173_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3173.mem 53 5 1 sh3_zsrt139d3173_pal.mem 0x158afe76
174 198092 10240 480 sh3_zsrt139d3174_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3174.mem 62 6 1 sh3_zsrt139d3174_pal.mem 0x158afe76
175 198092 10240 480 sh3_zsrt139d3175_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3175.mem 98 10 1 sh3_zsrt139d3175_pal.mem 0x158afe76
176 198092 10240 480 sh3_zsrt139d3176_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3176.mem 170 18 1 sh3_zsrt139d3176_pal.mem 0x158afe76
177 198092 10240 480 sh3_zsrt139d3177_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3177.mem 341 37 1 sh3_zsrt139d3177_pal.mem 0x158afe76
178 198092 10240 480 sh3_zsrt139d3178_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3178.mem 242 26 1 sh3_zsrt139d3178_pal.mem 0x158afe76
179 198092 10240 480 sh3_zsrt139d3179_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3179.mem 53 5 1 sh3_zsrt139d3179_pal.mem 0x158afe76
180 198092 10240 480 sh3_zsrt139d3180_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3180.mem 35 3 1 sh3_zsrt139d3180_pal.mem 0x158afe76
181 198092 10240 480 sh3_zsrt139d3181_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3181.mem 35 3 1 sh3_zsrt139d3181_pal.mem 0x158afe76
182 198092 10240 480 sh3_zsrt139d3182_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3182.mem 35 3 1 sh3_zsrt139d3182_pal.mem 0x158afe76
183 198092 10240 480 sh3_zsrt139d3183_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3183.mem 35 3 1 sh3_zsrt139d3183_pal.mem 0x158afe76
184 198092 10240 480 sh3_zsrt139d3184_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3184.mem 44 4 1 sh3_zsrt139d3184_pal.mem 0x158afe76
185 198092 10240 480 sh3_zsrt139d3185_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3185.mem 62 6 1 sh3_zsrt139d3185_pal.mem 0x158afe76
186 198092 10240 480 sh3_zsrt139d3186_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d3186.mem 98 10 1 sh3_zsrt139d3186_pal.mem 0x158afe76
