# Ch404 epoch descriptor table (35 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 35 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 153218 11264 480 sh3_zsrt139b10_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b10.mem 1142 126 0 sh3_zsrt139b10_pal.mem 0xc6784386
1 153643 11264 480 sh3_zsrt139b11_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b11.mem 1034 114 1 sh3_zsrt139b11_pal.mem 0xc6784386
2 154029 11264 480 sh3_zsrt139b12_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b12.mem 1070 118 1 sh3_zsrt139b12_pal.mem 0xc6784386
3 154428 11264 480 sh3_zsrt139b13_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b13.mem 1142 126 1 sh3_zsrt139b13_pal.mem 0xc6784386
4 154853 11264 480 sh3_zsrt139b14_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b14.mem 1106 122 1 sh3_zsrt139b14_pal.mem 0xc6784386
5 155265 11264 480 sh3_zsrt139b15_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b15.mem 1070 118 1 sh3_zsrt139b15_pal.mem 0xc6784386
6 155664 11264 480 sh3_zsrt139b16_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b16.mem 1070 118 1 sh3_zsrt139b16_pal.mem 0xc6784386
7 156063 11264 480 sh3_zsrt139b17_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139b17.mem 1358 150 1 sh3_zsrt139b17_pal.mem 0xc6784386
8 156566 10240 480 sh3_zsrt139b18_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b18.mem 998 110 0 sh3_zsrt139b18_pal.mem 0x00fd9028
9 156939 10240 480 sh3_zsrt139b19_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b19.mem 890 98 1 sh3_zsrt139b19_pal.mem 0x00fd9028
10 157273 10240 480 sh3_zsrt139b110_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b110.mem 890 98 1 sh3_zsrt139b110_pal.mem 0x00fd9028
11 157607 10240 480 sh3_zsrt139b111_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b111.mem 962 106 1 sh3_zsrt139b111_pal.mem 0x00fd9028
12 157967 10240 480 sh3_zsrt139b112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b112.mem 926 102 1 sh3_zsrt139b112_pal.mem 0x00fd9028
13 158314 10240 480 sh3_zsrt139b113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b113.mem 962 106 1 sh3_zsrt139b113_pal.mem 0x00fd9028
14 158674 10240 480 sh3_zsrt139b114_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b114.mem 962 106 1 sh3_zsrt139b114_pal.mem 0x00fd9028
15 159034 10240 480 sh3_zsrt139b115_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b115.mem 1034 114 1 sh3_zsrt139b115_pal.mem 0x00fd9028
16 159420 10240 480 sh3_zsrt139b116_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b116.mem 890 98 1 sh3_zsrt139b116_pal.mem 0x00fd9028
17 159754 10240 480 sh3_zsrt139b117_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b117.mem 962 106 1 sh3_zsrt139b117_pal.mem 0x00fd9028
18 160114 10240 480 sh3_zsrt139b118_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b118.mem 566 62 1 sh3_zsrt139b118_pal.mem 0x00fd9028
19 160331 10240 480 sh3_zsrt139b119_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b119.mem 1178 130 0 sh3_zsrt139b119_pal.mem 0xd8d19684
20 160769 10240 480 sh3_zsrt139b120_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b120.mem 1070 118 1 sh3_zsrt139b120_pal.mem 0xd8d19684
21 161168 10240 480 sh3_zsrt139b121_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b121.mem 1070 118 1 sh3_zsrt139b121_pal.mem 0xd8d19684
22 161567 10240 480 sh3_zsrt139b122_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b122.mem 1250 138 1 sh3_zsrt139b122_pal.mem 0xd8d19684
23 162031 10240 480 sh3_zsrt139b123_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b123.mem 710 78 1 sh3_zsrt139b123_pal.mem 0xd8d19684
24 162300 10240 480 sh3_zsrt139b124_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b124.mem 1142 126 1 sh3_zsrt139b124_pal.mem 0xd8d19684
25 162725 10240 480 sh3_zsrt139b125_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b125.mem 1178 130 1 sh3_zsrt139b125_pal.mem 0xd8d19684
26 163163 10240 480 sh3_zsrt139b126_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b126.mem 1106 122 1 sh3_zsrt139b126_pal.mem 0xd8d19684
27 163575 10240 480 sh3_zsrt139b127_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b127.mem 1142 126 1 sh3_zsrt139b127_pal.mem 0xd8d19684
28 164000 10240 480 sh3_zsrt139b128_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b128.mem 530 58 1 sh3_zsrt139b128_pal.mem 0xd8d19684
29 164204 10240 480 sh3_zsrt139b129_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b129.mem 1322 146 0 sh3_zsrt139b129_pal.mem 0xaa4e7e05
30 164694 10240 480 sh3_zsrt139b130_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b130.mem 674 74 1 sh3_zsrt139b130_pal.mem 0xaa4e7e05
31 164950 10240 480 sh3_zsrt139b131_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b131.mem 602 66 1 sh3_zsrt139b131_pal.mem 0xaa4e7e05
32 165180 10240 480 sh3_zsrt139b132_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139b132.mem 458 50 1 sh3_zsrt139b132_pal.mem 0xaa4e7e05
33 175995 12288 480 sh3_zsrt139b133_tex_lpddr.mem 0x200000 262144 0xf2553358 feeder_sh3_zsrt139b133.mem 1214 134 0 sh3_zsrt139b133_pal.mem 0x56ebf1d1
34 176446 12288 480 sh3_zsrt139b134_tex_lpddr.mem 0x200000 262144 0xf2553358 feeder_sh3_zsrt139b134.mem 1376 152 1 sh3_zsrt139b134_pal.mem 0x56ebf1d1
