# Ch401 epoch descriptor table (28 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 28 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 5328 11264 480 sh3_zsrt139a70_tex_lpddr.mem 0x200000 262144 0x55070afa feeder_sh3_zsrt139a70.mem 493 54 0 sh3_zsrt139a70_pal.mem 0x32ed74c4
1 11671 10240 480 sh3_zsrt139a71_tex_lpddr.mem 0x200000 262144 0x26a88b77 feeder_sh3_zsrt139a71.mem 1060 117 0 sh3_zsrt139a71_pal.mem 0x3cd88c98
2 12757 10240 480 sh3_zsrt139a72_tex_lpddr.mem 0x200000 262144 0x26a88b77 feeder_sh3_zsrt139a72.mem 529 58 1 sh3_zsrt139a72_pal.mem 0x3cd88c98
3 15277 12288 480 sh3_zsrt139a73_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139a73.mem 781 86 0 sh3_zsrt139a73_pal.mem 0x4812d6f2
4 16217 11264 480 sh3_zsrt139a74_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a74.mem 1231 136 0 sh3_zsrt139a74_pal.mem 0x5cbf8bb4
5 16643 11264 480 sh3_zsrt139a75_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a75.mem 1231 136 1 sh3_zsrt139a75_pal.mem 0x5cbf8bb4
6 17069 11264 480 sh3_zsrt139a76_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a76.mem 763 84 1 sh3_zsrt139a76_pal.mem 0x5cbf8bb4
7 17339 11264 480 sh3_zsrt139a77_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a77.mem 1231 136 1 sh3_zsrt139a77_pal.mem 0x5cbf8bb4
8 17765 11264 480 sh3_zsrt139a78_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a78.mem 709 78 1 sh3_zsrt139a78_pal.mem 0x5cbf8bb4
9 19136 11264 480 sh3_zsrt139a79_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a79.mem 1231 136 1 sh3_zsrt139a79_pal.mem 0x5cbf8bb4
10 19562 11264 480 sh3_zsrt139a710_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a710.mem 1231 136 1 sh3_zsrt139a710_pal.mem 0x5cbf8bb4
11 20246 11264 480 sh3_zsrt139a711_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a711.mem 952 105 1 sh3_zsrt139a711_pal.mem 0x5cbf8bb4
12 20579 11264 480 sh3_zsrt139a712_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a712.mem 1231 136 1 sh3_zsrt139a712_pal.mem 0x5cbf8bb4
13 21005 11264 480 sh3_zsrt139a713_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a713.mem 1096 121 1 sh3_zsrt139a713_pal.mem 0x5cbf8bb4
14 21599 11264 480 sh3_zsrt139a714_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a714.mem 169 18 1 sh3_zsrt139a714_pal.mem 0x5cbf8bb4
15 26066 11264 480 sh3_zsrt139a715_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a715.mem 61 6 0 sh3_zsrt139a715_pal.mem 0x44679578
16 30859 10240 480 sh3_zsrt139a716_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139a716.mem 619 68 0 sh3_zsrt139a716_pal.mem 0x47405cb0
17 31075 13824 480 sh3_zsrt139a717_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a717.mem 619 68 0 sh3_zsrt139a717_pal.mem 0x566e7c38
18 77112 10240 480 sh3_zsrt139a718_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139a718.mem 619 68 0 sh3_zsrt139a718_pal.mem 0x43ece1ae
19 89164 9216 480 sh3_zsrt139a719_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139a719.mem 619 68 0 sh3_zsrt139a719_pal.mem 0x5dfce0a2
20 119471 8192 480 sh3_zsrt139a720_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a720.mem 1843 204 0 sh3_zsrt139a720_pal.mem 0x47097d4c
21 120110 8192 480 sh3_zsrt139a721_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a721.mem 1843 204 1 sh3_zsrt139a721_pal.mem 0x47097d4c
22 120749 8192 480 sh3_zsrt139a722_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a722.mem 1843 204 1 sh3_zsrt139a722_pal.mem 0x47097d4c
23 121388 8192 480 sh3_zsrt139a723_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a723.mem 1843 204 1 sh3_zsrt139a723_pal.mem 0x47097d4c
24 122027 8192 480 sh3_zsrt139a724_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a724.mem 1843 204 1 sh3_zsrt139a724_pal.mem 0x47097d4c
25 129389 8192 480 sh3_zsrt139a725_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a725.mem 1843 204 1 sh3_zsrt139a725_pal.mem 0x47097d4c
26 130241 8192 480 sh3_zsrt139a726_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a726.mem 1843 204 1 sh3_zsrt139a726_pal.mem 0x47097d4c
27 130880 8192 480 sh3_zsrt139a727_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139a727.mem 1843 204 1 sh3_zsrt139a727_pal.mem 0x47097d4c
