# Ch435 epoch descriptor table (39 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 39 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e0.mem 35 3 0 sh3_zsrt139l7e0_pal.mem 0x00000000
1 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e1.mem 35 3 1 sh3_zsrt139l7e0_pal.mem 0x00000000
2 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e2.mem 35 3 1 sh3_zsrt139l7e0_pal.mem 0x00000000
3 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e3.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
4 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e4.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
5 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e5.mem 53 5 1 sh3_zsrt139l7e0_pal.mem 0x00000000
6 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e6.mem 53 5 1 sh3_zsrt139l7e0_pal.mem 0x00000000
7 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e7.mem 62 6 1 sh3_zsrt139l7e0_pal.mem 0x00000000
8 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e8.mem 89 9 1 sh3_zsrt139l7e0_pal.mem 0x00000000
9 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e9.mem 476 52 1 sh3_zsrt139l7e0_pal.mem 0x00000000
10 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e10.mem 359 39 1 sh3_zsrt139l7e0_pal.mem 0x00000000
11 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e11.mem 98 10 1 sh3_zsrt139l7e0_pal.mem 0x00000000
12 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e12.mem 71 7 1 sh3_zsrt139l7e0_pal.mem 0x00000000
13 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e13.mem 62 6 1 sh3_zsrt139l7e0_pal.mem 0x00000000
14 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e14.mem 53 5 1 sh3_zsrt139l7e0_pal.mem 0x00000000
15 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e15.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
16 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e16.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
17 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e17.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
18 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e18.mem 35 3 1 sh3_zsrt139l7e0_pal.mem 0x00000000
19 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e19.mem 35 3 1 sh3_zsrt139l7e0_pal.mem 0x00000000
20 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e20.mem 35 3 1 sh3_zsrt139l7e0_pal.mem 0x00000000
21 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e21.mem 35 3 1 sh3_zsrt139l7e0_pal.mem 0x00000000
22 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e22.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
23 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e23.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
24 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e24.mem 53 5 1 sh3_zsrt139l7e0_pal.mem 0x00000000
25 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e25.mem 53 5 1 sh3_zsrt139l7e0_pal.mem 0x00000000
26 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e26.mem 62 6 1 sh3_zsrt139l7e0_pal.mem 0x00000000
27 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e27.mem 80 8 1 sh3_zsrt139l7e0_pal.mem 0x00000000
28 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e28.mem 278 30 1 sh3_zsrt139l7e0_pal.mem 0x00000000
29 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e29.mem 539 59 1 sh3_zsrt139l7e0_pal.mem 0x00000000
30 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e30.mem 107 11 1 sh3_zsrt139l7e0_pal.mem 0x00000000
31 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e31.mem 71 7 1 sh3_zsrt139l7e0_pal.mem 0x00000000
32 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e32.mem 62 6 1 sh3_zsrt139l7e0_pal.mem 0x00000000
33 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e33.mem 53 5 1 sh3_zsrt139l7e0_pal.mem 0x00000000
34 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e34.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
35 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e35.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
36 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e36.mem 44 4 1 sh3_zsrt139l7e0_pal.mem 0x00000000
37 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e37.mem 35 3 1 sh3_zsrt139l7e0_pal.mem 0x00000000
38 196167 11264 480 sh3_zsrt139l7e0_tex_lpddr.mem 0x200000 262144 0xfcffae83 feeder_sh3_zsrt139l7e38.mem 26 2 1 sh3_zsrt139l7e0_pal.mem 0x00000000
