# Ch438 epoch descriptor table (125 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 125 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 603072 12288 480 sh3_zsrt139f530_tex_lpddr.mem 0x200000 262144 0x42d367ae feeder_sh3_zsrt139f530.mem 44 4 0 sh3_zsrt139f530_pal.mem 0x60778774
1 608122 11264 480 sh3_zsrt139f531_tex_lpddr.mem 0x200000 262144 0x55070afa feeder_sh3_zsrt139f531.mem 1583 175 0 sh3_zsrt139f531_pal.mem 0x32ed74c4
2 609451 11264 480 sh3_zsrt139f531_tex_lpddr.mem 0x200000 262144 0x55070afa feeder_sh3_zsrt139f532.mem 1835 203 1 sh3_zsrt139f531_pal.mem 0x32ed74c4
3 614057 10240 480 sh3_zsrt139f533_tex_lpddr.mem 0x200000 262144 0x26a88b77 feeder_sh3_zsrt139f533.mem 350 38 0 sh3_zsrt139f533_pal.mem 0x3cd88c98
4 616577 12288 480 sh3_zsrt139f534_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139f534.mem 1322 146 0 sh3_zsrt139f534_pal.mem 0x4812d6f2
5 616577 12288 480 sh3_zsrt139f534_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139f535.mem 116 12 1 sh3_zsrt139f534_pal.mem 0x4812d6f2
6 617231 12288 480 sh3_zsrt139f534_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139f536.mem 629 69 1 sh3_zsrt139f534_pal.mem 0x4812d6f2
7 621546 11264 480 sh3_zsrt139f537_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139f537.mem 260 28 0 sh3_zsrt139f537_pal.mem 0x5cbf8bb4
8 622092 11264 480 sh3_zsrt139f537_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139f538.mem 593 65 1 sh3_zsrt139f537_pal.mem 0x5cbf8bb4
9 622686 11264 480 sh3_zsrt139f537_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139f539.mem 341 37 1 sh3_zsrt139f537_pal.mem 0x5cbf8bb4
10 631761 10240 480 sh3_zsrt139f5310_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5310.mem 35 3 0 sh3_zsrt139f5310_pal.mem 0x47405cb0
11 633215 10240 480 sh3_zsrt139f5310_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5311.mem 350 38 1 sh3_zsrt139f5310_pal.mem 0x47405cb0
12 634603 10240 480 sh3_zsrt139f5310_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5312.mem 602 66 1 sh3_zsrt139f5310_pal.mem 0x47405cb0
13 635905 10240 480 sh3_zsrt139f5310_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5313.mem 944 104 1 sh3_zsrt139f5310_pal.mem 0x47405cb0
14 637207 10240 480 sh3_zsrt139f5310_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5314.mem 593 65 1 sh3_zsrt139f5310_pal.mem 0x47405cb0
15 638509 10240 480 sh3_zsrt139f5310_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5315.mem 728 80 1 sh3_zsrt139f5310_pal.mem 0x47405cb0
16 639811 10240 480 sh3_zsrt139f5310_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5316.mem 1196 132 1 sh3_zsrt139f5310_pal.mem 0x47405cb0
17 672448 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5317.mem 683 75 0 sh3_zsrt139f5317_pal.mem 0x43ece1ae
18 673087 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5318.mem 323 35 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
19 673726 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5319.mem 296 32 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
20 674365 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5320.mem 530 58 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
21 675004 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5321.mem 701 77 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
22 675643 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5322.mem 422 46 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
23 676282 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5323.mem 683 75 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
24 676921 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5324.mem 1070 118 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
25 677560 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5325.mem 539 59 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
26 678199 10240 480 sh3_zsrt139f5317_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f5326.mem 674 74 1 sh3_zsrt139f5317_pal.mem 0x43ece1ae
27 679619 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5327.mem 476 52 0 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
28 684020 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5328.mem 449 49 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
29 684623 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5329.mem 809 89 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
30 685244 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5330.mem 593 65 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
31 685865 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5331.mem 701 77 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
32 686486 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5332.mem 476 52 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
33 687107 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5333.mem 935 103 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
34 687728 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5334.mem 584 64 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
35 688349 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5335.mem 314 34 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
36 690218 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5336.mem 26 2 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
37 690848 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5337.mem 2042 226 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
38 690848 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5338.mem 1016 112 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
39 691487 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5339.mem 1808 200 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
40 691487 9216 480 sh3_zsrt139f5327_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5340.mem 494 54 1 sh3_zsrt139f5327_pal.mem 0x5dfce0a2
41 692978 9216 480 sh3_zsrt139f5341_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f5341.mem 188 20 0 sh3_zsrt139f5341_pal.mem 0x181b2ac2
42 715731 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5342.mem 1466 162 0 sh3_zsrt139f5342_pal.mem 0x47097d4c
43 716316 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5343.mem 2042 226 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
44 716316 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5344.mem 287 31 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
45 716955 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5345.mem 2042 226 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
46 716955 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5346.mem 395 43 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
47 717651 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5347.mem 1754 194 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
48 718350 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5348.mem 1556 172 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
49 718899 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5349.mem 2042 226 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
50 718899 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5350.mem 98 10 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
51 719538 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5351.mem 1808 200 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
52 720177 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5352.mem 1178 130 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
53 720771 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5353.mem 485 53 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
54 721410 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5354.mem 1889 209 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
55 722049 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5355.mem 1502 166 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
56 722049 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5356.mem 575 63 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
57 722688 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5357.mem 1016 112 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
58 723327 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5358.mem 872 96 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
59 723900 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5359.mem 782 86 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
60 724539 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5360.mem 161 17 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
61 725169 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5361.mem 251 27 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
62 725808 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5362.mem 323 35 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
63 726447 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5363.mem 89 9 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
64 727086 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5364.mem 557 61 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
65 727734 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5365.mem 368 40 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
66 728268 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5366.mem 647 71 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
67 728907 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5367.mem 530 58 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
68 729546 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5368.mem 431 47 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
69 730185 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5369.mem 62 6 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
70 730689 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5370.mem 1493 165 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
71 731328 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5371.mem 1214 134 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
72 731967 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5372.mem 1628 180 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
73 731967 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5373.mem 224 24 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
74 732606 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5374.mem 485 53 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
75 732606 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5375.mem 566 62 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
76 732606 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5376.mem 512 56 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
77 732606 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5377.mem 764 84 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
78 733245 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5378.mem 1439 159 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
79 733884 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5379.mem 953 105 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
80 734562 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5380.mem 620 68 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
81 734562 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5381.mem 53 5 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
82 737169 8192 480 sh3_zsrt139f5342_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f5382.mem 26 2 1 sh3_zsrt139f5342_pal.mem 0x47097d4c
83 746190 12288 480 sh3_zsrt139f5383_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrt139f5383.mem 179 19 0 sh3_zsrt139f5383_pal.mem 0x3e849a98
84 747012 12288 480 sh3_zsrt139f5383_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrt139f5384.mem 116 12 1 sh3_zsrt139f5383_pal.mem 0x3e849a98
85 747505 11264 480 sh3_zsrt139f5385_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5385.mem 998 110 0 sh3_zsrt139f5385_pal.mem 0xfd978fd9
86 747930 11264 480 sh3_zsrt139f5385_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5386.mem 287 31 1 sh3_zsrt139f5385_pal.mem 0xfd978fd9
87 748368 11264 480 sh3_zsrt139f5385_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5387.mem 332 36 1 sh3_zsrt139f5385_pal.mem 0xfd978fd9
88 748780 11264 480 sh3_zsrt139f5388_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5388.mem 674 74 0 sh3_zsrt139f5388_pal.mem 0xd5ed05ff
89 749188 11264 480 sh3_zsrt139f5388_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5389.mem 665 73 1 sh3_zsrt139f5388_pal.mem 0xd5ed05ff
90 749564 11264 480 sh3_zsrt139f5388_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5390.mem 980 108 1 sh3_zsrt139f5388_pal.mem 0xd5ed05ff
91 750219 11264 480 sh3_zsrt139f5391_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5391.mem 1016 112 0 sh3_zsrt139f5391_pal.mem 0xcdf8a4d8
92 750809 11264 480 sh3_zsrt139f5391_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5392.mem 809 89 1 sh3_zsrt139f5391_pal.mem 0xcdf8a4d8
93 751425 11264 480 sh3_zsrt139f5391_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5393.mem 737 81 1 sh3_zsrt139f5391_pal.mem 0xcdf8a4d8
94 752041 11264 480 sh3_zsrt139f5391_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5394.mem 674 74 1 sh3_zsrt139f5391_pal.mem 0xcdf8a4d8
95 752644 11264 480 sh3_zsrt139f5391_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5395.mem 458 50 1 sh3_zsrt139f5391_pal.mem 0xcdf8a4d8
96 753321 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5396.mem 188 20 0 sh3_zsrt139f5396_pal.mem 0xc6784386
97 753720 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5397.mem 251 27 1 sh3_zsrt139f5396_pal.mem 0xc6784386
98 754106 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5398.mem 359 39 1 sh3_zsrt139f5396_pal.mem 0xc6784386
99 754518 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f5399.mem 143 15 1 sh3_zsrt139f5396_pal.mem 0xc6784386
100 754943 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f53100.mem 35 3 1 sh3_zsrt139f5396_pal.mem 0xc6784386
101 755329 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f53101.mem 278 30 1 sh3_zsrt139f5396_pal.mem 0xc6784386
102 755728 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f53102.mem 188 20 1 sh3_zsrt139f5396_pal.mem 0xc6784386
103 756153 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f53103.mem 134 14 1 sh3_zsrt139f5396_pal.mem 0xc6784386
104 756565 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f53104.mem 161 17 1 sh3_zsrt139f5396_pal.mem 0xc6784386
105 756964 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f53105.mem 98 10 1 sh3_zsrt139f5396_pal.mem 0xc6784386
106 757363 11264 480 sh3_zsrt139f5396_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f53106.mem 62 6 1 sh3_zsrt139f5396_pal.mem 0xc6784386
107 757866 10240 480 sh3_zsrt139f53107_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53107.mem 1232 136 0 sh3_zsrt139f53107_pal.mem 0x00fd9028
108 758573 10240 480 sh3_zsrt139f53107_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53108.mem 1034 114 1 sh3_zsrt139f53107_pal.mem 0x00fd9028
109 759267 10240 480 sh3_zsrt139f53107_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53109.mem 755 83 1 sh3_zsrt139f53107_pal.mem 0x00fd9028
110 759974 10240 480 sh3_zsrt139f53107_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53110.mem 863 95 1 sh3_zsrt139f53107_pal.mem 0x00fd9028
111 760720 10240 480 sh3_zsrt139f53107_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53111.mem 503 55 1 sh3_zsrt139f53107_pal.mem 0x00fd9028
112 761414 10240 480 sh3_zsrt139f53107_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53112.mem 116 12 1 sh3_zsrt139f53107_pal.mem 0x00fd9028
113 761631 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53113.mem 269 29 0 sh3_zsrt139f53113_pal.mem 0xd8d19684
114 762069 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53114.mem 269 29 1 sh3_zsrt139f53113_pal.mem 0xd8d19684
115 762468 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53115.mem 314 34 1 sh3_zsrt139f53113_pal.mem 0xd8d19684
116 762867 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53116.mem 287 31 1 sh3_zsrt139f53113_pal.mem 0xd8d19684
117 763600 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53117.mem 332 36 1 sh3_zsrt139f53113_pal.mem 0xd8d19684
118 764025 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53118.mem 287 31 1 sh3_zsrt139f53113_pal.mem 0xd8d19684
119 764463 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53119.mem 215 23 1 sh3_zsrt139f53113_pal.mem 0xd8d19684
120 764875 10240 480 sh3_zsrt139f53113_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53120.mem 206 22 1 sh3_zsrt139f53113_pal.mem 0xd8d19684
121 765504 10240 480 sh3_zsrt139f53121_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53121.mem 629 69 0 sh3_zsrt139f53121_pal.mem 0xaa4e7e05
122 766250 10240 480 sh3_zsrt139f53121_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f53122.mem 341 37 1 sh3_zsrt139f53121_pal.mem 0xaa4e7e05
123 777295 12288 480 sh3_zsrt139f53123_tex_lpddr.mem 0x200000 262144 0xf2553358 feeder_sh3_zsrt139f53123.mem 386 42 0 sh3_zsrt139f53123_pal.mem 0x56ebf1d1
124 777746 12288 480 sh3_zsrt139f53123_tex_lpddr.mem 0x200000 262144 0xf2553358 feeder_sh3_zsrt139f53124.mem 206 22 1 sh3_zsrt139f53123_pal.mem 0x56ebf1d1
