# Ch419 epoch descriptor table (20 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 20 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 71361 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r0.mem 2042 226 0 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
1 71361 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r1.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
2 71361 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r2.mem 161 17 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
3 72213 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r3.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
4 72213 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r4.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
5 72213 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r5.mem 26 2 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
6 73278 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r6.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
7 73278 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r7.mem 1916 212 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
8 74130 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r8.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
9 74130 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r9.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
10 74130 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r10.mem 629 69 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
11 75195 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r11.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
12 75195 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r12.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
13 75195 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r13.mem 1052 116 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
14 76047 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r14.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
15 76047 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r15.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
16 76047 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r16.mem 800 88 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
17 77112 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r17.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
18 77112 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r18.mem 2042 226 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
19 77112 10240 480 sh3_zsrt139f18r0_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f18r19.mem 458 50 1 sh3_zsrt139f18r0_pal.mem 0x43ece1ae
